From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id E3C433858CDB for ; Wed, 13 Mar 2024 09:16:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E3C433858CDB Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E3C433858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710321420; cv=none; b=bFdA6Fsr83QvzNCadcC0xSB07kBGc5Xovah7w6chuOAZp8ccXBdbuMOJlOXZYJEFTqfpt3x0P6A1FNnpiiXlVDLHST6BSUaoUpdH0/1DSivbK9yDcP5g8Pvdfl2vXdD52qBW+0roX+LavfhB7nJJqWre754kxorzIBQ5OuII3qg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1710321420; c=relaxed/simple; bh=CDk7ZoO0eJyY+0j3reXI83dT+igVzGjHEE5wSFf4RBc=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=IcSL8z2DVXGIl7mXS1bJIHo9wfUmRSyTictxhlwaVSsXE8bvv7/9CGdr0WZcYSP6XDvqz6vA66BKP1o0AQFUX9bXe9KfWoFEb0OHXu3+lPWYje+/GP7dy8wxEr9GNOeXEAoQZrKeUUoFeK5yKhuYlD7xk73837ZBzaBCdwAEwPw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1710321416; bh=CDk7ZoO0eJyY+0j3reXI83dT+igVzGjHEE5wSFf4RBc=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=k/zRpU2ZptxGS5yHUbCOgh7ADV5Tg7lLN2iir1G4eaRq0xr4Oy17uJyR4lvCSEWn+ en5Z8AEI8V9bs0JZciLiClfuJmCA7vIc91TrkJhk7xdQDm10U0x/MzniphTcbQyHx0 eEDNHBJXNEYNCgLluzHw/jTzFDbAWLfPSgLeVJfY= Received: from [127.0.0.1] (unknown [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id DDEDE67155; Wed, 13 Mar 2024 05:16:53 -0400 (EDT) Message-ID: <028e5c8c78921e11f6a4f3d088841f9314054c19.camel@xry111.site> Subject: Re: [PATCH v4] LoongArch: Add support for TLS descriptors From: Xi Ruoyao To: mengqinggang , gcc-patches@gcc.gnu.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, cailulu@loongson.cn, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn Date: Wed, 13 Mar 2024 17:16:51 +0800 In-Reply-To: <98ac81d9-8c33-b12d-a341-c65a5a3924a8@loongson.cn> References: <20240312092002.1335661-1-mengqinggang@loongson.cn> <98ac81d9-8c33-b12d-a341-c65a5a3924a8@loongson.cn> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.4 MIME-Version: 1.0 X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 2024-03-13 at 11:06 +0800, mengqinggang wrote: >=20 > =E5=9C=A8 2024/3/13 =E4=B8=8A=E5=8D=886:15, Xi Ruoyao =E5=86=99=E9=81=93: > > On Tue, 2024-03-12 at 17:20 +0800, mengqinggang wrote: > > > +(define_insn "@got_load_tls_desc" > > > +=C2=A0 [(set (match_operand:P 0 "register_operand" "=3Dr") > > > + (unspec:P > > > + =C2=A0=C2=A0=C2=A0 [(match_operand:P 1 "symbolic_operand" "")] > > > + =C2=A0=C2=A0=C2=A0 UNSPEC_TLS_DESC)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC0_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC1_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC2_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC3_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC4_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC5_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC6_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC7_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI RETURN_ADDR_REGNUM))] > > > +=C2=A0 "TARGET_TLS_DESC" > > > +{ > > > +=C2=A0 return TARGET_EXPLICIT_RELOCS > > > +=C2=A0=C2=A0=C2=A0 ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\= n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tld.d\t$r1,$r4,%%desc_ld(%1)\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tjirl\t$r1,$r1,%%desc_call(%1)" > > Use something like > >=20 > > =C2=A0=C2=A0=C2=A0=C2=A0 ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\t" > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "addi.d\t$r4,$r4,%%desc_pc_lo12(%1= )\n\t" > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "ld.d\t$r1,$r4,%%desc_ld(%1)\n\t" > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "jirl\t$r1,$r1,%%desc_call(%1)" > > =C2=A0=C2=A0=C2=A0=C2=A0 : "la.tls.desc\t%0,%1"; > >=20 > > to prevent additional white spaces in the output asm before tabs. > >=20 > > > +=C2=A0=C2=A0=C2=A0 : "la.tls.desc\t%0,%1"; > > > +} > > > +=C2=A0 [(set_attr "got" "load") > > > +=C2=A0=C2=A0 (set_attr "mode" "") > > > +=C2=A0=C2=A0 (set_attr "length" "16")]) > > > + > > > +(define_insn "got_load_tls_desc_off64" > > > +=C2=A0 [(set (match_operand:DI 0 "register_operand" "=3Dr") > > > + (unspec:DI > > > + =C2=A0=C2=A0=C2=A0 [(match_operand:DI 1 "symbolic_operand" "")] > > > + =C2=A0=C2=A0=C2=A0 UNSPEC_TLS_DESC_OFF64)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC0_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC1_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC2_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC3_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC4_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC5_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC6_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI FCC7_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (reg:SI RETURN_ADDR_REGNUM)) > > > +=C2=A0=C2=A0=C2=A0 (clobber (match_operand:DI 2 "register_operand" "= =3D&r"))] > > > +=C2=A0 "TARGET_TLS_DESC && TARGET_CMODEL_EXTREME" > > > +{ > > > +=C2=A0 return TARGET_EXPLICIT_RELOCS > > > +=C2=A0=C2=A0=C2=A0 ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n= \ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)= \n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tadd.d\t$r4,$r4,%2\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tld.d\t$r1,$r4,%%desc_ld(%1)\n\ > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \tjirl\t$r1,$r1,%%desc_call(%1)" > > > +=C2=A0=C2=A0=C2=A0 : "la.tls.desc\t%0,%2,%1"; > > Likewise. > >=20 > > > +} > > > +=C2=A0 [(set_attr "got" "load") > > > +=C2=A0=C2=A0 (set_attr "length" "28")]) > > Otherwise OK. > >=20 > > It's better to allow splitting these two instructions but we can do it > > in another patch.=C2=A0 And IMO it's better to enable TLS desc by defau= lt if > > supported by both the assembler and the libc, but we'll have to defer i= t > > until Glibc 2.40 release. >=20 >=20 > Do we need to wait until LLVM also supports TLS DESC=C2=A0 before setting= it=20 > as default? Hmm, maybe... I remember when we added R_LARCH_ALIGN lld was being broken for a while. --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University