From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 90C273858D28 for ; Fri, 3 Dec 2021 19:42:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 90C273858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=eC1R3zS/J8lO0tc+ZKWPhgdEeIC4BmwcsjgzvNAs28A=; b=KXjFmE3f5cHoHcOQjLmiAKPCKt Xv5LkXZE8wLShtRCIzphi0sNIqghicVjs3hmEht0WoKzWC1yogAmCQAP6t30jEAQS4Bz7Ill9Ryaz KYSXOFzsJ/VzjzSM/+ONvTot077hAz3u0dASukChEuc22HYch8AC36NMAwr2hIN515kZC8xEb+Vmy xpXn85dtOU4akedbKv57GkwMT1XfqIVjxw1+x7gmjbT4ehOwnCVbaFe2XuM2Ho3aJNXwNyg4fyLc4 W1lkyFcQSoNotWo/FLH35Jke3ul6c+AhkCH5G+Or4RvwfIfqHKflKbYT4xXSW82d90NbMuSJYGCGt BsId4Ubw==; Received: from [185.62.158.67] (port=50832 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mtESM-0002dg-HE for gcc-patches@gcc.gnu.org; Fri, 03 Dec 2021 14:42:54 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH take #2] PR target/43892: Some carry flag (CA) optimizations on PowerPC. Date: Fri, 3 Dec 2021 19:42:52 -0000 Message-ID: <03ae01d7e87d$f67f1a80$e37d4f80$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_03AF_01D7E87D.F6949E50" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdfofYDKMcGpqekGRL+MIMwsp2vfAA== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Dec 2021 19:42:57 -0000 This is a multipart message in MIME format. ------=_NextPart_000_03AF_01D7E87D.F6949E50 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Doh! This time with the patch attached... This patch resolves PR target/43892 (suboptimal add with carry) by adding four new define_insn_and_split to the rs6000 backend, that all recognize pairs of instructions where the first instruction sets the carry flag and the second one consumes it. It also adds a commutative variant of add3_carry_in_0 (aka "addze") to catch cases, not caught by recog's insn canonicalization, where CA_REG appears first. For the add32carry function in the original PR: unsigned int add32carry(unsigned int sum, unsigned int x) { unsigned int z = sum + x; if (sum + x < x) z++; return z; } previously "-O2 -m32" would generate: add32carry: add 3,3,4 subfc 4,4,3 subfe 9,9,9 subf 3,9,3 blr with this patch we now generate: add32carry: addc 3,3,4 addze 3,3 blr And for the related examples in the new test case, unsigned long add_leu(unsigned long a, unsigned long b, unsigned long c) { return a + (b <= c); } unsigned long add_geu(unsigned long a, unsigned long b, unsigned long c) { return a + (b >= c); } On powerpc64 with -O2 we'd previously generate: add_leu: subfc 4,4,5 subfe 9,9,9 addi 9,9,1 add 3,9,3 blr add_geu: subfc 5,5,4 subfe 9,9,9 addi 9,9,1 add 3,9,3 blr but with this patch we now generate: add_leu: subfc 4,4,5 addze 3,3 blr add_geu: subfc 5,5,4 addze 3,3 blr This patch has been tested on powerpc64-unknown-linux-gnu (many thanks to gcc203.fsffrance.org on the GCC compile farm) with a make bootstrap and make -k check with now new failures. Ok for mainline? 2021-12-03 Roger Sayle gcc/ChangeLog PR target/43892 * config/rs6000/rs6000.md (*add3_carry_in_0_2): New define_insn to recognize commutative form of add3_carry_in_0. (*add3_geu, *add3_leu, *subf3_carry_in_xx_subf, *add3_carry_in_addc): New define_insn_and_split patterns. gcc/testsuite/ChangeLog PR target/43892 * gcc.target/powerpc/addcmp.c: New test case. * gcc.target/powerpc/pr43892.c: New test case. Many thanks in advance. Roger -- ------=_NextPart_000_03AF_01D7E87D.F6949E50 Content-Type: text/plain; name="patchp2b.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchp2b.txt" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md=0A= index 6bec2bddbde..90c23556ccb 100644=0A= --- a/gcc/config/rs6000/rs6000.md=0A= +++ b/gcc/config/rs6000/rs6000.md=0A= @@ -2067,6 +2067,16 @@=0A= "addze %0,%1"=0A= [(set_attr "type" "add")])=0A= =0A= +;; Non-canonical form of add3_carry_in_0=0A= +(define_insn "*add3_carry_in_0_2"=0A= + [(set (match_operand:GPR 0 "gpc_reg_operand" "=3Dr")=0A= + (plus:GPR (reg:GPR CA_REGNO)=0A= + (match_operand:GPR 1 "gpc_reg_operand" "r")))=0A= + (clobber (reg:GPR CA_REGNO))]=0A= + ""=0A= + "addze %0,%1"=0A= + [(set_attr "type" "add")])=0A= +=0A= (define_insn "add3_carry_in_m1"=0A= [(set (match_operand:GPR 0 "gpc_reg_operand" "=3Dr")=0A= (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")=0A= @@ -2078,6 +2088,95 @@=0A= [(set_attr "type" "add")])=0A= =0A= =0A= +;; PR target/43892 -> subf3_carry ; add3_carry_in_0=0A= +(define_insn_and_split "*add3_geu"=0A= + [(set (match_operand:P 0 "gpc_reg_operand" "=3Dr")=0A= + (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r")=0A= + (match_operand:P 2 "gpc_reg_operand" "r"))=0A= + (match_operand:P 3 "gpc_reg_operand" "r")))=0A= + (clobber (match_scratch:P 4 "=3Dr"))=0A= + (clobber (reg:P CA_REGNO))]=0A= + ""=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + if (GET_CODE (operands[4]) =3D=3D SCRATCH)=0A= + operands[4] =3D gen_reg_rtx (mode);=0A= + emit_insn (gen_subf3_carry (operands[4], operands[1], = operands[2]));=0A= + emit_insn (gen_add3_carry_in_0 (operands[0], operands[3]));=0A= + DONE;=0A= +}=0A= + [(set_attr "type" "two")=0A= + (set_attr "length" "8")])=0A= +=0A= +;; PR target/43892 -> subf3_carry ; add3_carry_in_0=0A= +(define_insn_and_split "*add3_leu"=0A= + [(set (match_operand:P 0 "gpc_reg_operand" "=3Dr")=0A= + (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")=0A= + (match_operand:P 2 "gpc_reg_operand" "r"))=0A= + (match_operand:P 3 "gpc_reg_operand" "r")))=0A= + (clobber (match_scratch:P 4 "=3Dr"))=0A= + (clobber (reg:P CA_REGNO))]=0A= + ""=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + if (GET_CODE (operands[4]) =3D=3D SCRATCH)=0A= + operands[4] =3D gen_reg_rtx (mode);=0A= + emit_insn (gen_subf3_carry (operands[4], operands[2], = operands[1]));=0A= + emit_insn (gen_add3_carry_in_0 (operands[0], operands[3]));=0A= + DONE;=0A= +}=0A= + [(set_attr "type" "two")=0A= + (set_attr "length" "8")])=0A= +=0A= +;; PR target/43892 -> subf3_carry_in_xx ; subf3=0A= +(define_insn_and_split "*subf3_carry_in_xx_subf"=0A= + [(set (match_operand:P 0 "gpc_reg_operand" "=3Dr")=0A= + (plus:P (minus:P (match_operand:P 1 "gpc_reg_operand" "r")=0A= + (reg:P CA_REGNO))=0A= + (const_int 1)))=0A= + (clobber (match_scratch:P 2 "=3Dr"))=0A= + (clobber (reg:P CA_REGNO))]=0A= + ""=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + if (GET_CODE (operands[2]) =3D=3D SCRATCH)=0A= + operands[2] =3D gen_reg_rtx (mode);=0A= + emit_insn (gen_subf3_carry_in_xx (operands[2]));=0A= + emit_insn (gen_sub3 (operands[0], operands[1], operands[2]));=0A= + DONE;=0A= +}=0A= + [(set_attr "type" "two")=0A= + (set_attr "length" "8")])=0A= +=0A= +;; PR target/43892 -> add3_carry ; add3_carry_in_0=0A= +(define_insn_and_split "*add3_carry_in_addc"=0A= + [(set (match_operand:P 0 "gpc_reg_operand" "=3Dr")=0A= + (plus:P (plus:P=0A= + (ltu:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")=0A= + (match_operand:P 2 "gpc_reg_operand" "r"))=0A= + (match_dup 1))=0A= + (match_dup 2))=0A= + (match_dup 1)))=0A= + (clobber (reg:P CA_REGNO))]=0A= + ""=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + emit_insn (gen_add3_carry (operands[0], operands[1], = operands[2]));=0A= + emit_insn (gen_add3_carry_in_0 (operands[0], operands[0]));=0A= + DONE;=0A= +}=0A= + [(set_attr "type" "two")=0A= + (set_attr "length" "8")])=0A= +=0A= +=0A= (define_expand "one_cmpl2"=0A= [(set (match_operand:SDI 0 "gpc_reg_operand")=0A= (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))]=0A= diff --git a/gcc/testsuite/gcc.target/powerpc/addcmp.c = b/gcc/testsuite/gcc.target/powerpc/addcmp.c=0A= new file mode 100644=0A= index 00000000000..6ca971bfc66=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/powerpc/addcmp.c=0A= @@ -0,0 +1,12 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +unsigned long add_leu(unsigned long a, unsigned long b, unsigned long = c) {=0A= + return a + (b <=3D c);=0A= +}=0A= +=0A= +unsigned long add_geu(unsigned long a, unsigned long b, unsigned long = c) {=0A= + return a + (b >=3D c);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "addze " 2 } } */=0A= diff --git a/gcc/testsuite/gcc.target/powerpc/pr43892.c = b/gcc/testsuite/gcc.target/powerpc/pr43892.c=0A= new file mode 100644=0A= index 00000000000..f5d6b852c5f=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/powerpc/pr43892.c=0A= @@ -0,0 +1,11 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +unsigned long foo(unsigned long sum, unsigned long x)=0A= +{=0A= + unsigned long z =3D sum + x;=0A= + if (sum + x < x)=0A= + z++;=0A= + return z;=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler "addze " } } */=0A= ------=_NextPart_000_03AF_01D7E87D.F6949E50--