Re: [PATCH] RISC-V: Enable SLP un-order reduction

[Robin Dapp <rdapp.gcc@gmail.com>]

Hi Juzhe,

> +;; -------------------------------------------------------------------------
> +;; ---- [INT,FP] Initialize from individual elements
> +;; -------------------------------------------------------------------------
> +;; Includes:
> +;; - vslide1up.vx/vfslide1up.vf
> +;; -------------------------------------------------------------------------
> +

Wouldn't you want to add this to the already existing "section" with
the same name? (where vec_init is).

Apart from that LGTM, thanks.

> +;; Slide an RVV vector left and insert a scalar into element 0.
> +(define_expand "vec_shl_insert_<mode>"
> +  [(match_operand:VI 0 "register_operand")
> +   (match_operand:VI 1 "register_operand")
> +   (match_operand:<VEL> 2 "reg_or_0_operand")]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred_slide (UNSPEC_VSLIDE1UP, <MODE>mode);
> +  rtx ops[] = {operands[0], RVV_VUNDEF (<MODE>mode), operands[1], operands[2]};
> +  riscv_vector::emit_vlmax_slide_insn (icode, ops);
> +  DONE;
> +})
> +
> +(define_expand "vec_shl_insert_<mode>"
> +  [(match_operand:VF 0 "register_operand")
> +   (match_operand:VF 1 "register_operand")
> +   (match_operand:<VEL> 2 "register_operand")]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred_slide (UNSPEC_VFSLIDE1UP, <MODE>mode);
> +  rtx ops[] = {operands[0], RVV_VUNDEF (<MODE>mode), operands[1], operands[2]};
> +  riscv_vector::emit_vlmax_slide_insn (icode, ops);
> +  DONE;
> +})

It appears bit unfortunate here that we have two different insn patterns
for int and float when they are so similar but I guess that's the consequence
of the implicit sign extend.  We can still have emit_vlmax_slide_insn
(or some other function) differentiate between them and unify at the
expander site in the future, though.

Regards
 Robin