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[46.5.130.86]) by smtp.gmail.com with ESMTPSA id z11-20020aa7cf8b000000b0051df13f1d8fsm815193edx.71.2023.07.18.00.54.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Jul 2023 00:54:27 -0700 (PDT) Message-ID: <03b45c00-c10a-e238-429c-dd6f12467cc5@gmail.com> Date: Tue, 18 Jul 2023 09:54:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Cc: rdapp.gcc@gmail.com, kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com Subject: Re: [PATCH] RISC-V: Enable SLP un-order reduction To: Juzhe-Zhong , gcc-patches@gcc.gnu.org References: <20230718010351.240789-1-juzhe.zhong@rivai.ai> Content-Language: en-US From: Robin Dapp In-Reply-To: <20230718010351.240789-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_ASCII_DIVIDERS,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Juzhe, > +;; ------------------------------------------------------------------------- > +;; ---- [INT,FP] Initialize from individual elements > +;; ------------------------------------------------------------------------- > +;; Includes: > +;; - vslide1up.vx/vfslide1up.vf > +;; ------------------------------------------------------------------------- > + Wouldn't you want to add this to the already existing "section" with the same name? (where vec_init is). Apart from that LGTM, thanks. > +;; Slide an RVV vector left and insert a scalar into element 0. > +(define_expand "vec_shl_insert_" > + [(match_operand:VI 0 "register_operand") > + (match_operand:VI 1 "register_operand") > + (match_operand: 2 "reg_or_0_operand")] > + "TARGET_VECTOR" > +{ > + insn_code icode = code_for_pred_slide (UNSPEC_VSLIDE1UP, mode); > + rtx ops[] = {operands[0], RVV_VUNDEF (mode), operands[1], operands[2]}; > + riscv_vector::emit_vlmax_slide_insn (icode, ops); > + DONE; > +}) > + > +(define_expand "vec_shl_insert_" > + [(match_operand:VF 0 "register_operand") > + (match_operand:VF 1 "register_operand") > + (match_operand: 2 "register_operand")] > + "TARGET_VECTOR" > +{ > + insn_code icode = code_for_pred_slide (UNSPEC_VFSLIDE1UP, mode); > + rtx ops[] = {operands[0], RVV_VUNDEF (mode), operands[1], operands[2]}; > + riscv_vector::emit_vlmax_slide_insn (icode, ops); > + DONE; > +}) It appears bit unfortunate here that we have two different insn patterns for int and float when they are so similar but I guess that's the consequence of the implicit sign extend. We can still have emit_vlmax_slide_insn (or some other function) differentiate between them and unify at the expander site in the future, though. Regards Robin