From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 63EAD3858D20 for ; Fri, 28 Jul 2023 15:00:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 63EAD3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=us.ibm.com Received: from pps.filterd (m0353726.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36SElI2W021314; Fri, 28 Jul 2023 15:00:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : subject : from : to : cc : date : content-type : mime-version : content-transfer-encoding; s=pp1; bh=veDs+x5b0n5oAc/QlxmdjW60HAa0gxYdueojcFPCFAM=; b=C4gR6Ku1X4yS4PEP7uAfTNS9rnM2h+HV1/NVwpnP6d+QkrgcoPWce4gqqZGXRxZnoMgG RTMkfTennYUdB0QkNuF6e1q6xWLiZlGR/JmRUWLZ5v+PJS4Mm4A2gl97j6LCI9G7KUEl 1CtrOV6bQLKRjMAjLzt85D6cBIKTE75P1ejnqx8BXVw35579vFPNwByomRqT0X3Xrk/s 2gKmyWfak2lYdYzmOR1fWam3Mq63NrCpb00PBEzoiAzsDzHZVO7Wk3VQGm4yCbq25Ae1 TCRWs/UtT9Ws83iHAv/8z8TRatGZql1nm4PcVgPPdqB/PmlFwkSnHs93jnhZs2r69MfV dA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3s4f7shpyh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 15:00:06 +0000 Received: from m0353726.ppops.net (m0353726.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36SESnjK011323; Fri, 28 Jul 2023 15:00:05 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3s4f7shpxf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 15:00:05 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 36SD1BfW026217; Fri, 28 Jul 2023 15:00:04 GMT Received: from smtprelay06.dal12v.mail.ibm.com ([172.16.1.8]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3s0sesqcdy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 15:00:04 +0000 Received: from smtpav04.wdc07v.mail.ibm.com (smtpav04.wdc07v.mail.ibm.com [10.39.53.231]) by smtprelay06.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 36SF03L83080928 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 28 Jul 2023 15:00:03 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81B4A58054; Fri, 28 Jul 2023 15:00:03 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7AA4158056; Fri, 28 Jul 2023 15:00:02 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.61.185.149]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Fri, 28 Jul 2023 15:00:02 +0000 (GMT) Message-ID: <03ba5b4a0bdee9f3b2fd73ec15cc100f003e6868.camel@us.ibm.com> Subject: [PATCH] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation From: Carl Love To: gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn Cc: cel@us.ibm.com, Peter Bergner Date: Fri, 28 Jul 2023 08:00:01 -0700 Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: SvqYJXAVm8E7UuW42S2Ai0vPrJKUSzhi X-Proofpoint-GUID: ZC3b9RJ0x2NAq2Js7nEalbx6gNJSLd_R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 suspectscore=0 mlxlogscore=991 mlxscore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307280134 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: GCC maintainers: The following patch cleans up the definition for the __builtin_altivec_vcmpnet. The current implementation implies that the built-in is only supported on Power 9 since it is defined under the Power 9 stanza. However the built-in has no ISA restrictions as stated in the Power Vector Intrinsic Programming Reference document. The current built-in works because the built-in gets replaced during GIMPLE folding by a simple not-equal operator so it doesn't get expanded and checked for Power 9 code generation. This patch moves the definition to the Altivec stanza in the built-in definition file to make it clear the built-ins are valid for Power 8, Power 9 and beyond. The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE with no regressions. Please let me know if the patch is acceptable for mainline. Thanks. Carl -------------------------------------- rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation The current built-in definitions for vcmpneb, vcmpneh, vcmpnew are defined under the Power 9 section of r66000-builtins. This implies they are only supported on Power 9 and above when in fact they are defined and work on Power 8 as well with the appropriate Power 8 instruction generation. The vec_cmpne builtin should generate the vcmpequ{b,h,w} instruction on Power 8 and generate the vcmpne{b,h,w} on Power 9 an newer processors. This patch moves the definitions to the Altivec stanza to make it clear the built-ins are supported for all Altivec processors. The patch enables the vcmpequ{b,h,w} instruction to be generated on Power 8 and the vcmpne{b,h,w} instruction to be generated on Power 9 and beyond. There is existing test coverage for the vec_cmpne built-in for vector bool char, vector bool short, vector bool int, vector bool long long in builtins-3-p9.c and p8vector-builtin-2.c. Coverage for vector signed int, vector unsigned int is in p8vector-builtin-2.c. Coverage for unsigned long long int and long long int for Power 10 in int_128bit-runnable.c. Patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE with no regressions. gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (vcmpneb, vcmpneh, vcmpnew. vcmpnet): Move definitions to Altivec stanza. * config/rs6000/altivec.md (vcmpneb, vcmpneh, vcmpnew): New define_expand. --- gcc/config/rs6000/altivec.md | 12 ++++++++++++ gcc/config/rs6000/rs6000-builtins.def | 18 +++++++++--------- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index ad1224e0b57..31f65aa1b7a 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2631,6 +2631,18 @@ (define_insn "altivec_vcmpequt_p" "vcmpequq. %0,%1,%2" [(set_attr "type" "veccmpfx")]) +;; Expand for builtin vcmpne{b,h,w} +(define_expand "altivec_vcmpne_" + [(set (match_operand:VSX_EXTRACT_I 3 "altivec_register_operand" "=v") + (eq:VSX_EXTRACT_I (match_operand:VSX_EXTRACT_I 1 "altivec_register_operand" "v") + (match_operand:VSX_EXTRACT_I 2 "altivec_register_operand" "v"))) + (set (match_operand:VSX_EXTRACT_I 0 "altivec_register_operand" "=v") + (not:VSX_EXTRACT_I (match_dup 3)))] + "TARGET_ALTIVEC" + { + operands[3] = gen_reg_rtx (GET_MODE (operands[0])); + }); + (define_insn "*altivec_vcmpgts_p" [(set (reg:CC CR6_REGNO) (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 638d0bc72ca..6b06fa8b34d 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -641,6 +641,15 @@ const int __builtin_altivec_vcmpgtuw_p (int, vsi, vsi); VCMPGTUW_P vector_gtu_v4si_p {pred} + const vsc __builtin_altivec_vcmpneb (vsc, vsc); + VCMPNEB altivec_vcmpne_v16qi {} + + const vss __builtin_altivec_vcmpneh (vss, vss); + VCMPNEH altivec_vcmpne_v8hi {} + + const vsi __builtin_altivec_vcmpnew (vsi, vsi); + VCMPNEW altivec_vcmpne_v4si {} + const vsi __builtin_altivec_vctsxs (vf, const int<5>); VCTSXS altivec_vctsxs {} @@ -2599,9 +2608,6 @@ const signed int __builtin_altivec_vcmpaew_p (vsi, vsi); VCMPAEW_P vector_ae_v4si_p {} - const vsc __builtin_altivec_vcmpneb (vsc, vsc); - VCMPNEB vcmpneb {} - const signed int __builtin_altivec_vcmpneb_p (vsc, vsc); VCMPNEB_P vector_ne_v16qi_p {} @@ -2614,15 +2620,9 @@ const signed int __builtin_altivec_vcmpnefp_p (vf, vf); VCMPNEFP_P vector_ne_v4sf_p {} - const vss __builtin_altivec_vcmpneh (vss, vss); - VCMPNEH vcmpneh {} - const signed int __builtin_altivec_vcmpneh_p (vss, vss); VCMPNEH_P vector_ne_v8hi_p {} - const vsi __builtin_altivec_vcmpnew (vsi, vsi); - VCMPNEW vcmpnew {} - const signed int __builtin_altivec_vcmpnew_p (vsi, vsi); VCMPNEW_P vector_ne_v4si_p {} -- 2.37.2