* [PATCH 0/3] rs6000: Disparage lfiwzx and similar @ 2022-04-21 21:28 Segher Boessenkool 2022-04-21 21:28 ` [PATCH 1/3] rs6000: Add effective target has_arch_ppc64 Segher Boessenkool ` (2 more replies) 0 siblings, 3 replies; 4+ messages in thread From: Segher Boessenkool @ 2022-04-21 21:28 UTC (permalink / raw) To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool This series adds "?" on the "Z" for lfiwzx and similar, so that we preferably choose some D-form storage insn, instead of the X-form insn. The D-form insns work on GPRs only, but it is still much preferred. Committing to trunk. Segher Segher Boessenkool (3): rs6000: Add effective target has_arch_ppc64 rs6000: Disparage lfiwzx and similar rs6000/testsuite: xfail bswap-brw.c gcc/config/rs6000/rs6000.md | 22 +++++++++++----------- gcc/testsuite/gcc.target/powerpc/bswap-brw.c | 2 +- gcc/testsuite/lib/target-supports.exp | 10 ++++++++++ 3 files changed, 22 insertions(+), 12 deletions(-) -- 1.8.3.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/3] rs6000: Add effective target has_arch_ppc64 2022-04-21 21:28 [PATCH 0/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool @ 2022-04-21 21:28 ` Segher Boessenkool 2022-04-21 21:28 ` [PATCH 2/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool 2022-04-21 21:28 ` [PATCH 3/3] rs6000/testsuite: xfail bswap-brw.c Segher Boessenkool 2 siblings, 0 replies; 4+ messages in thread From: Segher Boessenkool @ 2022-04-21 21:28 UTC (permalink / raw) To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool This is true if we have -mpowerpc64. 2022-04-21 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ * lib/target-supports.exp (check_effective_target_has_arch_ppc64): New. --- gcc/testsuite/lib/target-supports.exp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 90b900956822..8bdb4a845f54 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6378,6 +6378,16 @@ proc check_effective_target_has_arch_pwr10 { } { }] } +proc check_effective_target_has_arch_ppc64 { } { + return [check_no_compiler_messages arch_ppc64 assembly { + #ifndef _ARCH_PPC64 + #error does not have ppc64 support. + #else + /* "has ppc64 support" */ + #endif + }] +} + # Return 1 if this is a PowerPC target supporting -mcpu=power10. # Limit this to 64-bit linux systems for now until other targets support # power10. -- 1.8.3.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/3] rs6000: Disparage lfiwzx and similar 2022-04-21 21:28 [PATCH 0/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool 2022-04-21 21:28 ` [PATCH 1/3] rs6000: Add effective target has_arch_ppc64 Segher Boessenkool @ 2022-04-21 21:28 ` Segher Boessenkool 2022-04-21 21:28 ` [PATCH 3/3] rs6000/testsuite: xfail bswap-brw.c Segher Boessenkool 2 siblings, 0 replies; 4+ messages in thread From: Segher Boessenkool @ 2022-04-21 21:28 UTC (permalink / raw) To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool RA now chooses GEN_OR_VSX_REGS in most cases. This is great in most cases, but we often (or always?) use {l,st}{f,xs}iwzx now, which is problematic because the integer load and store insns can use cheaper addressing modes. We can fix that by putting a small penalty on the instruction alternatives for those. 2022-04-21 Segher Boessenkool <segher@kernel.crashing.org> PR target/103197 PR target/102146 * config/rs6000/rs6000.md (zero_extendqi<mode>2 for EXTQI): Disparage the "Z" alternatives in {l,st}{f,xs}iwzx. (zero_extendhi<mode>2 for EXTHI): Ditto. (zero_extendsi<mode>2 for EXTSI): Ditto. (*movsi_internal1): Ditto. (*mov<mode>_internal1 for QHI): Ditto. (movsd_hardfloat): Ditto. --- gcc/config/rs6000/rs6000.md | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f05b8358ba0a..a39b95f7dffa 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -835,8 +835,8 @@ (define_mode_iterator ALTIVEC_DFORM [DF ;; complex forms. Basic data transfer is done later. (define_insn "zero_extendqi<mode>2" - [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v") - (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))] + [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,wa,^v") + (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,?Z,v")))] "" "@ lbz%U1%X1 %0,%1 @@ -889,8 +889,8 @@ (define_insn_and_split "*zero_extendqi<mode>2_dot2" (define_insn "zero_extendhi<mode>2" - [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v") - (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))] + [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,wa,^v") + (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,?Z,v")))] "" "@ lhz%U1%X1 %0,%1 @@ -944,7 +944,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2" (define_insn "zero_extendsi<mode>2" [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa") - (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))] + (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,?Z,?Z,r,wa,wa")))] "" "@ lwz%U1%X1 %0,%1 @@ -7496,7 +7496,7 @@ (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r, r, r, d, v, - m, Z, Z, + m, ?Z, ?Z, r, r, r, r, wa, wa, wa, v, wa, v, v, @@ -7504,7 +7504,7 @@ (define_insn "*movsi_internal1" r, *h, *h") (match_operand:SI 1 "input_operand" "r, U, - m, Z, Z, + m, ?Z, ?Z, r, d, v, I, L, eI, n, wa, O, wM, wB, @@ -7785,11 +7785,11 @@ (define_expand "mov<mode>" ;; MTVSRWZ MF%1 MT%1 NOP (define_insn "*mov<mode>_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" - "=r, r, wa, m, Z, r, + "=r, r, wa, m, ?Z, r, wa, wa, wa, v, ?v, r, wa, r, *c*l, *h") (match_operand:QHI 1 "input_operand" - "r, m, Z, r, wa, i, + "r, m, ?Z, r, wa, i, wa, O, wM, wB, wS, wa, r, *h, r, 0"))] "gpc_reg_operand (operands[0], <MODE>mode) @@ -7973,10 +7973,10 @@ (define_insn "movsf_hardfloat" ;; FMR MR MT%0 MF%1 NOP (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" - "=!r, d, m, Z, ?d, ?r, + "=!r, d, m, ?Z, ?d, ?r, f, !r, *c*l, !r, *h") (match_operand:SD 1 "input_operand" - "m, Z, r, wx, r, d, + "m, ?Z, r, wx, r, d, f, r, r, *h, 0"))] "(register_operand (operands[0], SDmode) || register_operand (operands[1], SDmode)) -- 1.8.3.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] rs6000/testsuite: xfail bswap-brw.c 2022-04-21 21:28 [PATCH 0/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool 2022-04-21 21:28 ` [PATCH 1/3] rs6000: Add effective target has_arch_ppc64 Segher Boessenkool 2022-04-21 21:28 ` [PATCH 2/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool @ 2022-04-21 21:28 ` Segher Boessenkool 2 siblings, 0 replies; 4+ messages in thread From: Segher Boessenkool @ 2022-04-21 21:28 UTC (permalink / raw) To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool This testcase does not generate anywhere near optimal code for 32-bit code. For p10 it actually now fails this testcase, after the previous patch. Let's xfail it. 2022-04-21 Segher Boessenkool <segher@kernel.crashing.org> gcc/testsuite/ PR target/103197 PR target/102146 * gcc.target/powerpc/bswap-brw.c: Add xfail on scan-assembler for -m32. --- gcc/testsuite/gcc.target/powerpc/bswap-brw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/powerpc/bswap-brw.c b/gcc/testsuite/gcc.target/powerpc/bswap-brw.c index b3f923eea848..0ed2a7bd1d25 100644 --- a/gcc/testsuite/gcc.target/powerpc/bswap-brw.c +++ b/gcc/testsuite/gcc.target/powerpc/bswap-brw.c @@ -17,6 +17,6 @@ bswap_int_dbl (unsigned int a) /* Force the value to be loaded into a vector register. */ __asm__ (" # %x0" : "+wa" (b)); - /* { dg-final { scan-assembler {\mxxbrw\M} } } */ + /* { dg-final { scan-assembler {\mxxbrw\M} {xfail {has_arch_pwr10 && {! has_arch_ppc64}}} } } */ return (double) __builtin_bswap32 (b); } -- 1.8.3.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-04-21 21:28 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-21 21:28 [PATCH 0/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool 2022-04-21 21:28 ` [PATCH 1/3] rs6000: Add effective target has_arch_ppc64 Segher Boessenkool 2022-04-21 21:28 ` [PATCH 2/3] rs6000: Disparage lfiwzx and similar Segher Boessenkool 2022-04-21 21:28 ` [PATCH 3/3] rs6000/testsuite: xfail bswap-brw.c Segher Boessenkool
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