From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 104386 invoked by alias); 30 Mar 2015 21:51:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 104376 invoked by uid 89); 30 Mar 2015 21:51:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL,BAYES_00,T_HDRS_LCASE,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: usmailout2.samsung.com Received: from mailout2.w2.samsung.com (HELO usmailout2.samsung.com) (211.189.100.12) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (DES-CBC3-SHA encrypted) ESMTPS; Mon, 30 Mar 2015 21:51:31 +0000 Received: from uscpsbgm2.samsung.com (u115.gpu85.samsung.co.kr [203.254.195.115]) by mailout2.w2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NM1009MYOPT3O50@mailout2.w2.samsung.com> for gcc-patches@gcc.gnu.org; Mon, 30 Mar 2015 17:51:29 -0400 (EDT) Received: from ussync2.samsung.com ( [203.254.195.82]) by uscpsbgm2.samsung.com (USCPMTA) with SMTP id A7.3C.10013.165C9155; Mon, 30 Mar 2015 17:51:29 -0400 (EDT) Received: from WEMENEZES ([105.140.33.224]) by ussync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NM100G2YOPSI260@ussync2.samsung.com> for gcc-patches@gcc.gnu.org; Mon, 30 Mar 2015 17:51:29 -0400 (EDT) From: Evandro Menezes To: 'GCC Patches' Subject: [PATCH] [AArch64] Add support for the Samsung Exynos M1 processor Date: Mon, 30 Mar 2015 21:51:00 -0000 Message-id: <055701d06b33$ad5afd70$0810f850$@samsung.com> MIME-version: 1.0 Content-type: multipart/mixed; boundary="----=_NextPart_000_0558_01D06B09.C4851C80" X-IsSubscribed: yes X-SW-Source: 2015-03/txt/msg01595.txt.bz2 This is a multipart message in MIME format. ------=_NextPart_000_0558_01D06B09.C4851C80 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-length: 273 The Samsung Exynos M1 implements the ARMv8 ISA and this patch adds support for it through the -mcpu command-line option. The patch was checked on aarch64-unknown-linux-gnu without new failures. OK for trunk? -- Evandro Menezes Austin, TX ------=_NextPart_000_0558_01D06B09.C4851C80 Content-Type: application/octet-stream; name="0001-AArch64-Add-option-for-the-Samsung-Exynos-M1-core-fo.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0001-AArch64-Add-option-for-the-Samsung-Exynos-M1-core-fo.patch" Content-length: 4163 >From 28ec332a929a6c4ac35a43d350c2ad72f544d2a3 Mon Sep 17 00:00:00 2001=0A= From: Evandro Menezes =0A= Date: Thu, 19 Mar 2015 16:18:58 -0500=0A= Subject: [PATCH] [AArch64] Add option for the Samsung Exynos M1 core for=0A= AArch64=0A= =0A= gcc/=0A= * doc/invoke.texi (AARCH64/mtune): Add exynos-m1 as an option.=0A= * config/aarch64/aarch64-cores.def (exynos-m1): New core.=0A= * config/aarch64/aarch64-tune.md: Regenerate.=0A= * config/aarch64/aarch64.c (exynosm1_tunings): New variable.=0A= ---=0A= gcc/config/aarch64/aarch64-cores.def | 1 +=0A= gcc/config/aarch64/aarch64-tune.md | 2 +-=0A= gcc/config/aarch64/aarch64.c | 18 ++++++++++++++++++=0A= gcc/doc/invoke.texi | 4 ++--=0A= 4 files changed, 22 insertions(+), 3 deletions(-)=0A= =0A= diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarc= h64-cores.def=0A= index 9b2eca2..d1d29e6 100644=0A= --- a/gcc/config/aarch64/aarch64-cores.def=0A= +++ b/gcc/config/aarch64/aarch64-cores.def=0A= @@ -37,6 +37,7 @@=0A= AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FOR_ARCH8= | AARCH64_FL_CRC, cortexa53)=0A= AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8, AARCH64_FL_FOR_ARCH8= | AARCH64_FL_CRC, cortexa57)=0A= AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8, AARCH64_FL_FOR_ARCH8= | AARCH64_FL_CRC, cortexa57)=0A= +AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8, AARCH64_FL_FOR_ARCH8= | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1)=0A= AARCH64_CORE("thunderx", thunderx, thunderx, 8, AARCH64_FL_FOR_ARCH8 = | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)=0A= AARCH64_CORE("xgene1", xgene1, xgene1, 8, AARCH64_FL_FOR_ARCH8= , xgene1)=0A= =20=0A= diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch6= 4-tune.md=0A= index c3305f9..7d063e4 100644=0A= --- a/gcc/config/aarch64/aarch64-tune.md=0A= +++ b/gcc/config/aarch64/aarch64-tune.md=0A= @@ -1,5 +1,5 @@=0A= ;; -*- buffer-read-only: t -*-=0A= ;; Generated automatically by gentune.sh from aarch64-cores.def=0A= (define_attr "tune"=0A= - "cortexa53,cortexa57,cortexa72,thunderx,xgene1,cortexa57cortexa53,cortexa= 72cortexa53"=0A= + "cortexa53,cortexa57,cortexa72,exynosm1,thunderx,xgene1,cortexa57cortexa5= 3,cortexa72cortexa53"=0A= (const (symbol_ref "((enum attr_tune) aarch64_tune)")))=0A= diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c=0A= index cba3c1a..ca9257c 100644=0A= --- a/gcc/config/aarch64/aarch64.c=0A= +++ b/gcc/config/aarch64/aarch64.c=0A= @@ -392,6 +392,24 @@ static const struct tune_params cortexa57_tunings =3D= =0A= 1 /* vec_reassoc_width. */=0A= };=0A= =20=0A= +static const struct tune_params exynosm1_tunings =3D=0A= +{=0A= + &cortexa57_extra_costs,=0A= + &cortexa57_addrcost_table,=0A= + &cortexa57_regmove_cost,=0A= + &cortexa57_vector_cost,=0A= + 4, /* memmov_cost */=0A= + 3, /* issue_rate */=0A= + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD=0A= + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */=0A= + 16, /* function_align. */=0A= + 8, /* jump_align. */=0A= + 4, /* loop_align. */=0A= + 2, /* int_reassoc_width. */=0A= + 4, /* fp_reassoc_width. */=0A= + 1 /* vec_reassoc_width. */=0A= +};=0A= +=0A= static const struct tune_params thunderx_tunings =3D=0A= {=0A= &thunderx_extra_costs,=0A= diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi=0A= index 4bbd3fc..19606e3 100644=0A= --- a/gcc/doc/invoke.texi=0A= +++ b/gcc/doc/invoke.texi=0A= @@ -12316,8 +12316,8 @@ architecture.=0A= @opindex mtune=0A= Specify the name of the target processor for which GCC should tune the=0A= performance of the code. Permissible values for this option are:=0A= -@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57},=0A= -@samp{cortex-a72}, @samp{thunderx}, @samp{xgene1}.=0A= +@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},= =0A= +@samp{exynos-m1}, @samp{thunderx}, @samp{xgene1}.=0A= =20=0A= Additionally, this option can specify that GCC should tune the performance= =0A= of the code for a big.LITTLE system. Permissible values for this=0A= --=20=0A= 2.1.0.243.g30d45f7=0A= =0A= ------=_NextPart_000_0558_01D06B09.C4851C80--