From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 129160 invoked by alias); 6 Sep 2017 15:12:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 129150 invoked by uid 89); 6 Sep 2017 15:12:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=processors, Best X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Sep 2017 15:12:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AFE0415AD for ; Wed, 6 Sep 2017 08:12:46 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 116743F578 for ; Wed, 6 Sep 2017 08:12:45 -0700 (PDT) References: <88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com> Subject: [arm-embedded] [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8 To: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme X-Forwarded-Message-Id: <88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com> Message-ID: <059cae6c-9591-9dd1-6a73-773e70fbc8d6@foss.arm.com> Date: Wed, 06 Sep 2017 15:12:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com> Content-Type: multipart/mixed; boundary="------------C0584B09365286F38B1B0F96" X-IsSubscribed: yes X-SW-Source: 2017-09/txt/msg00379.txt.bz2 This is a multi-part message in MIME format. --------------C0584B09365286F38B1B0F96 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 474 Hi, We have decided to apply the following patch to the embedded-7-branch as a dependency patch to enable ARMv8-R support. ChangeLog entry is as follows: *** gcc/ChangeLog.arm *** 2017-09-04 Thomas Preud'homme Backport from mainline 2017-07-04 Thomas Preud'homme * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM Cortex-R7 and Cortex-R8 processors. Best regards, Thomas --------------C0584B09365286F38B1B0F96 Content-Type: message/rfc822; name="Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8.eml" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename*0="Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-"; filename*1="R7 and Cortex-R8.eml" Content-length: 5347 Return-Path: X-Original-To: thomas.preudhomme@foss.arm.com Delivered-To: thomas.preudhomme@foss.arm.com Received: from foss.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTP id C31F03F557 for ; Tue, 4 Jul 2017 06:56:14 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC7A72B for ; Tue, 4 Jul 2017 06:56:14 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=MUPJllizzBvOTwfph r0GEo2NcVvw1kgf9bTnYBqMdUoL54Y8PKspvX8JzqezW2wCQZ5YkBHodkomQKbVp CVcVZ3HLU5/GmzEzma8slSsl+jXW83NCcTIxkwncHVfbA5n5dpvjcO42Jx4vvTbc 2Pxo2Nf/VZITfdJ6V5CHJ+py2k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=R8R1ZkmtoSa5TwvUAXSwa5A NKRA=; b=X+Ke5LwqcZ/LrEtgJlDnJTTwlPWy5dlnKBzFN8wBhokXrV62EQqj3pC VPihvJuYq1CYTTL7zTrlYDqVZIRXfJrCymVC70flG+U76ppyn6UggM07F+z/Kgkt YzBE6BgWMx1FBqYFG5aW1sxZm6ANYjvWVFyPnKMG7ty0vZXN1/fA= Received: (qmail 37908 invoked by alias); 4 Jul 2017 13:56:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 37888 invoked by uid 89); 4 Jul 2017 13:56:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Hx-languages-length:1218, Best X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Jul 2017 13:56:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE4BA2B; Tue, 4 Jul 2017 06:56:01 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EC4B83F557; Tue, 4 Jul 2017 06:56:00 -0700 (PDT) Subject: Re: [PATCH 1/3, GCC/ARM, ping] Add MIDR info for ARM Cortex-R7 and Cortex-R8 From: Thomas Preudhomme To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> Message-ID: <88ba1e93-952e-0759-9bca-ad120fff18f4@foss.arm.com> Date: Tue, 4 Jul 2017 14:55:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------7417BCA484418285FAF3E05D" X-IsSubscribed: yes This is a multi-part message in MIME format. --------------7417BCA484418285FAF3E05D Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 572 Ping? Best regards, Thomas On 29/06/17 14:55, Thomas Preudhomme wrote: > Hi, > > The driver is missing MIDR information for processors ARM Cortex-R7 and > Cortex-R8 to support -march/-mcpu/-mtune=native on the command line. > This patch adds the missing information. > > ChangeLog entry is as follows: > > *** gcc/ChangeLog *** > > 2017-01-31 Thomas Preud'homme > > * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM > Cortex-R7 and Cortex-R8 processors. > > Is this ok for master? > > Best regards, > > Thomas --------------7417BCA484418285FAF3E05D Content-Type: text/x-patch; name="1_add_cortex_r7_r8_midr.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="1_add_cortex_r7_r8_midr.patch" Content-length: 623 diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd09", "armv8-a+crc", "cortex-a73"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, + {"0xc17", "armv7-r", "cortex-r7"}, + {"0xc18", "armv7-r", "cortex-r8"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"}, --------------7417BCA484418285FAF3E05D-- --------------C0584B09365286F38B1B0F96--