* [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
@ 2023-12-08 8:00 pan2.li
2023-12-08 8:02 ` juzhe.zhong
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-12-08 8:00 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
The mode attr V_F2DI_CONVERT_BRIDGE converts the floating-point mode
to the widden floating-point by design. But we take (RVVM1HF "RVVM2SI") by
mistake.
This patch would like to fix it by replacing the
(RVVM1HF "RVVM2SI") to (RVVM1HF "RVVM2SF") as design.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
for mode attr V_F2DI_CONVERT_BRIDGE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 2 +-
.../riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 56080ed1f5f..5f5f7b5b986 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3267,7 +3267,7 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_attr V_F2DI_CONVERT_BRIDGE [
- (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SF")
+ (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF")
(RVVMF4HF "RVVMF2SF")
(RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
new file mode 100644
index 00000000000..5fb61c7b44c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
@@ -0,0 +1,7 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "test-math.h"
+
+TEST_UNARY_CALL_CVT (_Float16, long, __builtin_lroundf16)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
2023-12-08 8:00 [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE pan2.li
@ 2023-12-08 8:02 ` juzhe.zhong
2023-12-08 8:22 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: juzhe.zhong @ 2023-12-08 8:02 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 2346 bytes --]
LGTM.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-12-08 16:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
From: Pan Li <pan2.li@intel.com>
The mode attr V_F2DI_CONVERT_BRIDGE converts the floating-point mode
to the widden floating-point by design. But we take (RVVM1HF "RVVM2SI") by
mistake.
This patch would like to fix it by replacing the
(RVVM1HF "RVVM2SI") to (RVVM1HF "RVVM2SF") as design.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
for mode attr V_F2DI_CONVERT_BRIDGE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 2 +-
.../riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 56080ed1f5f..5f5f7b5b986 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3267,7 +3267,7 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_attr V_F2DI_CONVERT_BRIDGE [
- (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SF")
+ (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF")
(RVVMF4HF "RVVMF2SF")
(RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
new file mode 100644
index 00000000000..5fb61c7b44c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
@@ -0,0 +1,7 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "test-math.h"
+
+TEST_UNARY_CALL_CVT (_Float16, long, __builtin_lroundf16)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
2023-12-08 8:02 ` juzhe.zhong
@ 2023-12-08 8:22 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-12-08 8:22 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 3021 bytes --]
Committed, thanks Juzhe.
Pan
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, December 8, 2023 4:03 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
LGTM.
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-12-08 16:00
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
The mode attr V_F2DI_CONVERT_BRIDGE converts the floating-point mode
to the widden floating-point by design. But we take (RVVM1HF "RVVM2SI") by
mistake.
This patch would like to fix it by replacing the
(RVVM1HF "RVVM2SI") to (RVVM1HF "RVVM2SF") as design.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Replace RVVM2SI to RVVM2SF
for mode attr V_F2DI_CONVERT_BRIDGE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/vector-iterators.md | 2 +-
.../riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 56080ed1f5f..5f5f7b5b986 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3267,7 +3267,7 @@ (define_mode_attr v_f2di_convert [
])
(define_mode_attr V_F2DI_CONVERT_BRIDGE [
- (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SF")
+ (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF")
(RVVMF4HF "RVVMF2SF")
(RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
new file mode 100644
index 00000000000..5fb61c7b44c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
@@ -0,0 +1,7 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "test-math.h"
+
+TEST_UNARY_CALL_CVT (_Float16, long, __builtin_lroundf16)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-12-08 8:00 [PATCH v1] RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGE pan2.li
2023-12-08 8:02 ` juzhe.zhong
2023-12-08 8:22 ` Li, Pan2
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