From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 5963D3858416; Thu, 25 May 2023 05:44:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5963D3858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353727.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34P5aKP9021746; Thu, 25 May 2023 05:44:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=GJsl2tAKFV48Z0qO4+faPcXhxQ9sIyBIzvpt2kVtpqU=; b=sq0Zftt2l9wm6T00gu4/ic/ITAHlZWuceDDMG0NTBe5yY0nargfzyyesDCvWNlcyH+UI wTmh1ZOlUs8zbcOnn87icYn4SOpaquBHJ/ymFcZh9hXaKK/iucrwUm8u5JyDdO9jc2Sm iFOQm6NYVbRbbmftmgM0qpq1+tA8UehW921Y4f5kG8Fj+Buuh+bqIwmImFHyO+zoqza/ zNTVOIrPDhC7hRul4qo1DHqmlsOGXUjX9Y/rAR8UoY60xYnAgbQAj/SuEcJ6Dz8kw1FD hy74eyAKzyknV7w6scZo9unQviJbeStDynhrjUSPJETPtnJBsaclKU5AnHkZzYbkzuCy wQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qt0ynh0jm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 May 2023 05:44:10 +0000 Received: from m0353727.ppops.net (m0353727.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34P5cNcu029328; Thu, 25 May 2023 05:44:10 GMT Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qt0ynh0j4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 May 2023 05:44:10 +0000 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 34P4O94n009575; Thu, 25 May 2023 05:44:07 GMT Received: from smtprelay02.fra02v.mail.ibm.com ([9.218.2.226]) by ppma04fra.de.ibm.com (PPS) with ESMTPS id 3qppcf1vyn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 25 May 2023 05:44:07 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34P5i5SP24511108 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 25 May 2023 05:44:05 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E702C2006E; Thu, 25 May 2023 05:44:04 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A69E20049; Thu, 25 May 2023 05:44:02 +0000 (GMT) Received: from [9.177.2.126] (unknown [9.177.2.126]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 25 May 2023 05:44:01 +0000 (GMT) Message-ID: <0737fbfc-726c-ffca-5f36-d6b3f0decfec@linux.ibm.com> Date: Thu, 25 May 2023 13:44:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract* Content-Language: en-US To: Alexandre Oliva Cc: Rainer Orth , Mike Stump , David Edelsohn , Segher Boessenkool , Kewen Lin , gcc-patches@gcc.gnu.org References: From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: pzf9s-iy8eSX3-pm5Pu_HHS13Qi-2FpI X-Proofpoint-GUID: cLky0wIU0XmrOFA6zaAEKNq0v-M3KNxs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-25_02,2023-05-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305250043 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Alexandre, on 2023/5/24 13:51, Alexandre Oliva wrote: > > Codegen changes caused add instruction count mismatches on > ppc-*-linux-gnu and other 32-bit ppc targets. At some point the > expected counts were adjusted for lp64, but ilp32 differences > remained, and published test results confirm it. Thanks for fixing, I tested this on ppc64le and ppc64 {-m64,-m32} well. > > Bootstrapped on x86_64-linux-gnu. Also tested on ppc- and x86-vx7r2 > with gcc-12. > > for gcc/testsuite/ChangeLog I think this is for PR101169, could you add it as PR marker? > > * gcc.target/powerpc/fold-vec-extract-char.p7.c: Adjust addi > counts for ilp32. > * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise. > * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. > --- > .../gcc.target/powerpc/fold-vec-extract-char.p7.c | 3 ++- > .../powerpc/fold-vec-extract-double.p7.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-float.p7.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-int.p7.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-short.p7.c | 2 +- > .../gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +- > 8 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c > index 29a8aa84db282..c6647431d09c9 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c > @@ -11,7 +11,8 @@ > /* one extsb (extend sign-bit) instruction generated for each test against > unsigned types */ > > -/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */ > +/* { dg-final { scan-assembler-times {\maddi\M} 9 { target { lp64 } } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target { ilp32 } } } } */ > /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ > /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ > /* -m32 target uses rlwinm in place of rldicl. */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c > index 3cae644b90b71..db325efbb07ff 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c > @@ -14,7 +14,7 @@ > /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ > /* -m32 target has an 'add' in place of one of the 'addi'. */ > /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } } } */ So both lp64 and ilp32 have the same count, could we merge it and remove the selectors? > /* -m32 target has a rlwinm in place of a rldic . */ > /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ > /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c > index 59a4979457dcb..42ec69475fd07 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c > @@ -13,7 +13,7 @@ > /* { dg-final { scan-assembler-times {\mli\M} 1 } } */ > /* -m32 as an add in place of an addi. */ > /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } } } */ Ditto. > /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */ > /* -m32 uses rlwinm in place of rldic */ > /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c > index 4b1d75ee26d0f..68eeeede4b307 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c > @@ -26,7 +26,7 @@ > /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */ > > > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c > index 3729a1646e9c9..e8130693ee953 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c > @@ -11,7 +11,7 @@ > > /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ > /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } } } */ Ditto. > /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */ > /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ > /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c > index 75eaf25943b70..d1e3b62373f80 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c > @@ -30,7 +30,7 @@ > /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ > > > > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > index a495d9f3928fa..ec3b78bac5df6 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c > @@ -11,7 +11,7 @@ > > /* { dg-final { scan-assembler-times {\mli\M} 6 } } */ > /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } } } */ Ditto. BR, Kewen > /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */ > /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */ > /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */ > diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c > index 0ddecb4e4b55d..00685aca1367b 100644 > --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c > +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c > @@ -32,7 +32,7 @@ > /* add and rlwinm instructions only on the variable tests. */ > /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */ > -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */ > +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */ > /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */ > > >