Since according to RVV ISA, "The destination vector register can overlap the source operands, including the mask register."
That means we can have vredsum.vs v0,v8,v9,v0.t. This patch is to refine the constraint to allow this happen that the current RA constraint doesn't allow.
Since you can see "vd" to match  "vm", vd doesn't include mask register (v0). This trivial optimization can allow our RA have 1 more register to allocate.
It's overall beneficial to the RA. 



juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2023-03-15 02:05
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA
 
 
On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> According to RVV ISA:
> 14. Vector Reduction Operations
> 
> "The destination vector register can overlap the source operands, including the mask register."
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.
 
One question though, why even bother with the matching constraint at all 
in these patterns?  ISTM it doesn't really accomplish anything. 
Removing it allows a single alternative to handle all the possibilities.
 
Jeff