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From: Richard Biener <richard.guenther@gmail.com>
To: Yixuan Chen <chenyixuan@iscas.ac.cn>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, andrew@sifive.com,
	oriachiuan@gmail.com, jiawei@iscas.ac.cn
Subject: Re: [PATCH] Ver2: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
Date: Tue, 22 Nov 2022 11:03:02 +0100	[thread overview]
Message-ID: <077836FD-E58C-4A27-A470-AE46E53239DD@gmail.com> (raw)
In-Reply-To: <20221122094842.2629693-1-chenyixuan@iscas.ac.cn>



> Am 22.11.2022 um 10:49 schrieb Yixuan Chen <chenyixuan@iscas.ac.cn>:
> 
> gcc/testsuite/ChangeLog:
> 
> Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.

Ok.

Richard 

> 2022-11-22  Yixuan Chen  <chenyixuan@iscas.ac.cn>
> 
>        * gcc.dg/pr106397.c: Riscv don't support "-fprefetch-loop-arrays" option, add "-w" option.
> ---
> gcc/testsuite/gcc.dg/pr106397.c | 1 +
> 1 file changed, 1 insertion(+)
> 
> diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
> index 2bc17f8cf80..b0983b61dfc 100644
> --- a/gcc/testsuite/gcc.dg/pr106397.c
> +++ b/gcc/testsuite/gcc.dg/pr106397.c
> @@ -1,6 +1,7 @@
> /* { dg-do compile } */
> /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
> /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
> +/* { dg-additional-options "-w" { target riscv*-*-* } } */
> 
> int
> bar (void)
> -- 
> 2.37.2
> 

      reply	other threads:[~2022-11-22 10:03 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-22  9:48 Yixuan Chen
2022-11-22 10:03 ` Richard Biener [this message]

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