From: Bill Schmidt <wschmidt@linux.ibm.com>
To: gcc-patches@gcc.gnu.org
Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, willschm@linux.ibm.com
Subject: [PATCH 26/34] rs6000: Builtin expansion, part 4
Date: Thu, 29 Jul 2021 08:31:13 -0500 [thread overview]
Message-ID: <078e293801b870304865bf951287a2b068841960.1627562852.git.wschmidt@linux.ibm.com> (raw)
In-Reply-To: <cover.1627562851.git.wschmidt@linux.ibm.com>
In-Reply-To: <cover.1627562851.git.wschmidt@linux.ibm.com>
2021-07-28 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-call.c (elemrev_icode): Implement.
(ldv_expand_builtin): Likewise.
(lxvrse_expand_builtin): Likewise.
(lxvrze_expand_builtin): Likewise.
(stv_expand_builtin): Likewise.
---
gcc/config/rs6000/rs6000-call.c | 217 ++++++++++++++++++++++++++++++++
1 file changed, 217 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 4f5aed137fb..89984d65a46 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -14772,12 +14772,114 @@ new_cpu_expand_builtin (enum rs6000_gen_builtins fcode,
static insn_code
elemrev_icode (rs6000_gen_builtins fcode)
{
+ switch (fcode)
+ {
+ default:
+ gcc_unreachable ();
+ case RS6000_BIF_ST_ELEMREV_V1TI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
+ : CODE_FOR_vsx_st_elemrev_v1ti);
+ case RS6000_BIF_ST_ELEMREV_V2DF:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
+ : CODE_FOR_vsx_st_elemrev_v2df);
+ case RS6000_BIF_ST_ELEMREV_V2DI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
+ : CODE_FOR_vsx_st_elemrev_v2di);
+ case RS6000_BIF_ST_ELEMREV_V4SF:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
+ : CODE_FOR_vsx_st_elemrev_v4sf);
+ case RS6000_BIF_ST_ELEMREV_V4SI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
+ : CODE_FOR_vsx_st_elemrev_v4si);
+ case RS6000_BIF_ST_ELEMREV_V8HI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
+ : CODE_FOR_vsx_st_elemrev_v8hi);
+ case RS6000_BIF_ST_ELEMREV_V16QI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
+ : CODE_FOR_vsx_st_elemrev_v16qi);
+ case RS6000_BIF_LD_ELEMREV_V2DF:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
+ : CODE_FOR_vsx_ld_elemrev_v2df);
+ case RS6000_BIF_LD_ELEMREV_V1TI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
+ : CODE_FOR_vsx_ld_elemrev_v1ti);
+ case RS6000_BIF_LD_ELEMREV_V2DI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
+ : CODE_FOR_vsx_ld_elemrev_v2di);
+ case RS6000_BIF_LD_ELEMREV_V4SF:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
+ : CODE_FOR_vsx_ld_elemrev_v4sf);
+ case RS6000_BIF_LD_ELEMREV_V4SI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
+ : CODE_FOR_vsx_ld_elemrev_v4si);
+ case RS6000_BIF_LD_ELEMREV_V8HI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
+ : CODE_FOR_vsx_ld_elemrev_v8hi);
+ case RS6000_BIF_LD_ELEMREV_V16QI:
+ return (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
+ : CODE_FOR_vsx_ld_elemrev_v16qi);
+ }
+ gcc_unreachable ();
return (insn_code) 0;
}
static rtx
ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode)
{
+ rtx pat, addr;
+ bool blk = (icode == CODE_FOR_altivec_lvlx
+ || icode == CODE_FOR_altivec_lvlxl
+ || icode == CODE_FOR_altivec_lvrx
+ || icode == CODE_FOR_altivec_lvrxl);
+
+ if (target == 0
+ || GET_MODE (target) != tmode
+ || !(*insn_data[icode].operand[0].predicate) (target, tmode))
+ target = gen_reg_rtx (tmode);
+
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+
+ /* For LVX, express the RTL accurately by ANDing the address with -16.
+ LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
+ so the raw address is fine. */
+ if (icode == CODE_FOR_altivec_lvx_v1ti
+ || icode == CODE_FOR_altivec_lvx_v2df
+ || icode == CODE_FOR_altivec_lvx_v2di
+ || icode == CODE_FOR_altivec_lvx_v4sf
+ || icode == CODE_FOR_altivec_lvx_v4si
+ || icode == CODE_FOR_altivec_lvx_v8hi
+ || icode == CODE_FOR_altivec_lvx_v16qi)
+ {
+ rtx rawaddr;
+ if (op[0] == const0_rtx)
+ rawaddr = op[1];
+ else
+ {
+ op[0] = copy_to_mode_reg (Pmode, op[0]);
+ rawaddr = gen_rtx_PLUS (Pmode, op[1], op[0]);
+ }
+ addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
+ addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
+
+ emit_insn (gen_rtx_SET (target, addr));
+ }
+ else
+ {
+ if (op[0] == const0_rtx)
+ addr = gen_rtx_MEM (blk ? BLKmode : tmode, op[1]);
+ else
+ {
+ op[0] = copy_to_mode_reg (Pmode, op[0]);
+ addr = gen_rtx_MEM (blk ? BLKmode : tmode,
+ gen_rtx_PLUS (Pmode, op[1], op[0]));
+ }
+
+ pat = GEN_FCN (icode) (target, addr);
+ if (!pat)
+ return 0;
+ emit_insn (pat);
+ }
+
return target;
}
@@ -14785,6 +14887,42 @@ static rtx
lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op,
machine_mode tmode, machine_mode smode)
{
+ rtx pat, addr;
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+
+ if (op[0] == const0_rtx)
+ addr = gen_rtx_MEM (tmode, op[1]);
+ else
+ {
+ op[0] = copy_to_mode_reg (Pmode, op[0]);
+ addr = gen_rtx_MEM (smode,
+ gen_rtx_PLUS (Pmode, op[1], op[0]));
+ }
+
+ rtx discratch = gen_reg_rtx (DImode);
+ rtx tiscratch = gen_reg_rtx (TImode);
+
+ /* Emit the lxvr*x insn. */
+ pat = GEN_FCN (icode) (tiscratch, addr);
+ if (!pat)
+ return 0;
+ emit_insn (pat);
+
+ /* Emit a sign extension from QI,HI,WI to double (DI). */
+ rtx scratch = gen_lowpart (smode, tiscratch);
+ if (icode == CODE_FOR_vsx_lxvrbx)
+ emit_insn (gen_extendqidi2 (discratch, scratch));
+ else if (icode == CODE_FOR_vsx_lxvrhx)
+ emit_insn (gen_extendhidi2 (discratch, scratch));
+ else if (icode == CODE_FOR_vsx_lxvrwx)
+ emit_insn (gen_extendsidi2 (discratch, scratch));
+ /* Assign discratch directly if scratch is already DI. */
+ if (icode == CODE_FOR_vsx_lxvrdx)
+ discratch = scratch;
+
+ /* Emit the sign extension from DI (double) to TI (quad). */
+ emit_insn (gen_extendditi2 (target, discratch));
+
return target;
}
@@ -14792,6 +14930,22 @@ static rtx
lxvrze_expand_builtin (rtx target, insn_code icode, rtx *op,
machine_mode tmode, machine_mode smode)
{
+ rtx pat, addr;
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+
+ if (op[0] == const0_rtx)
+ addr = gen_rtx_MEM (tmode, op[1]);
+ else
+ {
+ op[0] = copy_to_mode_reg (Pmode, op[0]);
+ addr = gen_rtx_MEM (smode,
+ gen_rtx_PLUS (Pmode, op[1], op[0]));
+ }
+
+ pat = GEN_FCN (icode) (target, addr);
+ if (!pat)
+ return 0;
+ emit_insn (pat);
return target;
}
@@ -14799,6 +14953,69 @@ static rtx
stv_expand_builtin (insn_code icode, rtx *op,
machine_mode tmode, machine_mode smode)
{
+ rtx pat, addr, rawaddr, truncrtx;
+ op[2] = copy_to_mode_reg (Pmode, op[2]);
+
+ /* For STVX, express the RTL accurately by ANDing the address with -16.
+ STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
+ so the raw address is fine. */
+ if (icode == CODE_FOR_altivec_stvx_v2df
+ || icode == CODE_FOR_altivec_stvx_v2di
+ || icode == CODE_FOR_altivec_stvx_v4sf
+ || icode == CODE_FOR_altivec_stvx_v4si
+ || icode == CODE_FOR_altivec_stvx_v8hi
+ || icode == CODE_FOR_altivec_stvx_v16qi)
+ {
+ if (op[1] == const0_rtx)
+ rawaddr = op[2];
+ else
+ {
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+ rawaddr = gen_rtx_PLUS (Pmode, op[2], op[1]);
+ }
+
+ addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
+ addr = gen_rtx_MEM (tmode, addr);
+ op[0] = copy_to_mode_reg (tmode, op[0]);
+ emit_insn (gen_rtx_SET (addr, op[0]));
+ }
+ else if (icode == CODE_FOR_vsx_stxvrbx
+ || icode == CODE_FOR_vsx_stxvrhx
+ || icode == CODE_FOR_vsx_stxvrwx
+ || icode == CODE_FOR_vsx_stxvrdx)
+ {
+ truncrtx = gen_rtx_TRUNCATE (tmode, op[0]);
+ op[0] = copy_to_mode_reg (E_TImode, truncrtx);
+
+ if (op[1] == const0_rtx)
+ addr = gen_rtx_MEM (Pmode, op[2]);
+ else
+ {
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+ addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
+ }
+ pat = GEN_FCN (icode) (addr, op[0]);
+ if (pat)
+ emit_insn (pat);
+ }
+ else
+ {
+ if (! (*insn_data[icode].operand[1].predicate) (op[0], smode))
+ op[0] = copy_to_mode_reg (smode, op[0]);
+
+ if (op[1] == const0_rtx)
+ addr = gen_rtx_MEM (tmode, op[2]);
+ else
+ {
+ op[1] = copy_to_mode_reg (Pmode, op[1]);
+ addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1]));
+ }
+
+ pat = GEN_FCN (icode) (addr, op[0]);
+ if (pat)
+ emit_insn (pat);
+ }
+
return NULL_RTX;
}
--
2.27.0
next prev parent reply other threads:[~2021-07-29 13:35 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-29 13:30 [PATCHv4 00/34] Replace the Power target-specific builtin machinery Bill Schmidt
2021-07-29 13:30 ` [PATCH 01/34] rs6000: Incorporate new builtins code into the build machinery Bill Schmidt
2021-08-04 22:29 ` Segher Boessenkool
2021-08-05 13:47 ` Bill Schmidt
2021-08-05 16:04 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 02/34] rs6000: Add gengtype handling to " Bill Schmidt
2021-08-04 22:52 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 03/34] rs6000: Add the rest of the [altivec] stanza to the builtins file Bill Schmidt
2021-08-07 0:01 ` Segher Boessenkool
2021-08-08 16:53 ` Bill Schmidt
2021-08-08 20:27 ` Segher Boessenkool
2021-08-08 20:53 ` Bill Schmidt
2021-08-09 18:05 ` Segher Boessenkool
2021-08-09 19:18 ` Bill Schmidt
2021-08-09 23:44 ` Segher Boessenkool
2021-08-10 12:17 ` Bill Schmidt
2021-08-10 12:48 ` Segher Boessenkool
2021-08-10 13:02 ` Bill Schmidt
2021-08-10 13:40 ` Segher Boessenkool
2021-08-10 13:49 ` Bill Schmidt
2021-07-29 13:30 ` [PATCH 04/34] rs6000: Add VSX builtins Bill Schmidt
2021-08-10 16:14 ` will schmidt
2021-08-10 17:52 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 05/34] rs6000: Add available-everywhere and ancient builtins Bill Schmidt
2021-08-10 16:17 ` will schmidt
2021-08-10 17:34 ` Segher Boessenkool
2021-08-10 21:29 ` Bill Schmidt
2021-08-11 10:29 ` Segher Boessenkool
2021-08-10 18:38 ` Segher Boessenkool
2021-08-10 18:56 ` Bill Schmidt
2021-08-10 20:33 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 06/34] rs6000: Add power7 and power7-64 builtins Bill Schmidt
2021-08-10 16:16 ` will schmidt
2021-08-10 17:48 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 07/34] rs6000: Add power8-vector builtins Bill Schmidt
2021-08-23 21:28 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 08/34] rs6000: Add Power9 builtins Bill Schmidt
2021-08-23 21:40 ` Segher Boessenkool
2021-08-24 14:20 ` Bill Schmidt
2021-08-24 15:38 ` Segher Boessenkool
2021-08-24 16:27 ` Bill Schmidt
2021-07-29 13:30 ` [PATCH 09/34] rs6000: Add more type nodes to support builtin processing Bill Schmidt
2021-08-23 22:15 ` Segher Boessenkool
2021-08-24 14:38 ` Bill Schmidt
2021-07-29 13:30 ` [PATCH 10/34] rs6000: Add Power10 builtins Bill Schmidt
2021-08-23 23:48 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 11/34] rs6000: Add MMA builtins Bill Schmidt
2021-08-25 22:56 ` Segher Boessenkool
2021-07-29 13:30 ` [PATCH 12/34] rs6000: Add miscellaneous builtins Bill Schmidt
2021-08-25 22:58 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 13/34] rs6000: Add Cell builtins Bill Schmidt
2021-08-25 22:59 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 14/34] rs6000: Add remaining overloads Bill Schmidt
2021-08-25 23:27 ` Segher Boessenkool
2021-08-26 12:59 ` Bill Schmidt
2021-08-26 13:58 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 15/34] rs6000: Execute the automatic built-in initialization code Bill Schmidt
2021-08-26 23:15 ` Segher Boessenkool
2021-08-27 12:35 ` Bill Schmidt
2021-08-27 12:49 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 16/34] rs6000: Darwin builtin support Bill Schmidt
2021-08-27 18:01 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 17/34] rs6000: Add sanity to V2DI_type_node definitions Bill Schmidt
2021-08-27 19:27 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 18/34] rs6000: Always initialize vector_pair and vector_quad nodes Bill Schmidt
2021-08-27 19:34 ` Segher Boessenkool
2021-07-29 13:31 ` [PATCH 19/34] rs6000: Handle overloads during program parsing Bill Schmidt
2021-08-27 23:07 ` Segher Boessenkool
2021-08-31 3:34 ` Bill Schmidt
2021-07-29 13:31 ` [PATCH 20/34] rs6000: Handle gimple folding of target built-ins Bill Schmidt
2021-07-29 13:31 ` [PATCH 21/34] rs6000: Handle some recent MMA builtin changes Bill Schmidt
2021-07-29 13:31 ` [PATCH 22/34] rs6000: Support for vectorizing built-in functions Bill Schmidt
2021-07-29 13:31 ` [PATCH 23/34] rs6000: Builtin expansion, part 1 Bill Schmidt
2021-07-29 13:31 ` [PATCH 24/34] rs6000: Builtin expansion, part 2 Bill Schmidt
2021-07-29 13:31 ` [PATCH 25/34] rs6000: Builtin expansion, part 3 Bill Schmidt
2021-07-29 13:31 ` Bill Schmidt [this message]
2021-07-29 13:31 ` [PATCH 27/34] rs6000: Builtin expansion, part 5 Bill Schmidt
2021-07-29 13:31 ` [PATCH 28/34] rs6000: Builtin expansion, part 6 Bill Schmidt
2021-07-29 13:31 ` [PATCH 29/34] rs6000: Update rs6000_builtin_decl Bill Schmidt
2021-07-29 13:31 ` [PATCH 30/34] rs6000: Miscellaneous uses of rs6000_builtins_decl_x Bill Schmidt
2021-07-29 13:31 ` [PATCH 31/34] rs6000: Debug support Bill Schmidt
2021-07-29 13:31 ` [PATCH 32/34] rs6000: Update altivec.h for automated interfaces Bill Schmidt
2021-07-29 13:31 ` [PATCH 33/34] rs6000: Test case adjustments Bill Schmidt
2021-07-29 13:31 ` [PATCH 34/34] rs6000: Enable the new builtin support Bill Schmidt
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