* [PATCH 0/7] rs6000: More constraint updates
@ 2019-06-04 16:19 Segher Boessenkool
2019-06-04 16:20 ` [PATCH 4/7] rs6000: Delete VS_64reg Segher Boessenkool
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:19 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
All tested on p7, p8, p9, powerpc64-linux {-m32,-m64} and powerpc64le-linux.
Committing to trunk.
Segher
gcc/config/rs6000/constraints.md | 18 ----
gcc/config/rs6000/rs6000.c | 28 +-----
gcc/config/rs6000/rs6000.h | 6 --
gcc/config/rs6000/rs6000.md | 205 +++++++++++++++++++--------------------
gcc/config/rs6000/vsx.md | 191 +++++++++++++++++-------------------
gcc/doc/md.texi | 24 +----
6 files changed, 192 insertions(+), 280 deletions(-)
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 6/7] rs6000: wd -> wa
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
2019-06-04 16:20 ` [PATCH 4/7] rs6000: Delete VS_64reg Segher Boessenkool
2019-06-04 16:20 ` [PATCH 2/7] rs6000: wv -> v+p7v Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 5/7] rs6000: Delete Fv2 Segher Boessenkool
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"wd" is just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wd"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wd.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 --
gcc/config/rs6000/rs6000.c | 4 ---
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/vsx.md | 70 +++++++++++++++++++---------------------
gcc/doc/md.texi | 5 +--
6 files changed, 35 insertions(+), 50 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 2228667..763e892 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -59,9 +59,6 @@ (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits.
;; It is currently used for that purpose in LLVM.
-(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]"
- "VSX vector register to hold vector double data or NO_REGS.")
-
(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
"VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 87f8bdf..2b996db 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2508,7 +2508,6 @@ rs6000_debug_reg_global (void)
"f reg_class = %s\n"
"v reg_class = %s\n"
"wa reg_class = %s\n"
- "wd reg_class = %s\n"
"we reg_class = %s\n"
"wf reg_class = %s\n"
"wp reg_class = %s\n"
@@ -2522,7 +2521,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
@@ -3138,7 +3136,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
v - Altivec register.
wa - Any VSX register.
wc - Reserved to represent individual CR bits (used in LLVM).
- wd - Preferred register class for V2DFmode.
wf - Preferred register class for V4SFmode.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
@@ -3154,7 +3151,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_VSX)
{
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
}
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index c7fd7a2..6719cc4 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1256,7 +1256,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_f, /* fpr registers for single values */
RS6000_CONSTRAINT_v, /* Altivec registers */
RS6000_CONSTRAINT_wa, /* Any VSX register */
- RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8053d5a..4cf9082 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -625,7 +625,7 @@ (define_mode_attr rreg [(SF "f")
(TF "f")
(TD "f")
(V4SF "wf")
- (V2DF "wd")])
+ (V2DF "wa")])
(define_mode_attr rreg2 [(SF "f")
(DF "d")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60b3a8d..70276a8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -112,8 +112,8 @@ (define_mode_attr VSr [(V16QI "v")
(V8HI "v")
(V4SI "v")
(V4SF "wf")
- (V2DI "wd")
- (V2DF "wd")
+ (V2DI "wa")
+ (V2DF "wa")
(DI "wa")
(DF "wa")
(SF "ww")
@@ -125,7 +125,7 @@ (define_mode_attr VSr [(V16QI "v")
;; Map the register class used for float<->int conversions (floating point side)
;; VSr2 is the preferred register class, VSr3 is any register class that will
;; hold the data
-(define_mode_attr VSr2 [(V2DF "wd")
+(define_mode_attr VSr2 [(V2DF "wa")
(V4SF "wf")
(DF "wa")
(SF "ww")
@@ -144,14 +144,14 @@ (define_mode_attr VSr3 [(V2DF "wa")
;; Map the register class for sp<->dp float conversions, destination
(define_mode_attr VSr4 [(SF "wa")
(DF "f")
- (V2DF "wd")
+ (V2DF "wa")
(V4SF "v")])
;; Map the register class for sp<->dp float conversions, source
(define_mode_attr VSr5 [(SF "wa")
(DF "f")
(V2DF "v")
- (V4SF "wd")])
+ (V4SF "wa")])
;; The VSX register class that a type can occupy, even if it is not the
;; preferred register class (VSr is the preferred register class that will get
@@ -1919,16 +1919,14 @@ (define_insn "*vsx_fmav4sf4"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_fmav2df4"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa")
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
(fma:V2DF
- (match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa")
- (match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0")
- (match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))]
+ (match_operand:V2DF 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:V2DF 2 "vsx_register_operand" "wa,0")
+ (match_operand:V2DF 3 "vsx_register_operand" "0,wa")))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"@
xvmaddadp %x0,%x1,%x2
- xvmaddmdp %x0,%x1,%x3
- xvmaddadp %x0,%x1,%x2
xvmaddmdp %x0,%x1,%x3"
[(set_attr "type" "vecdouble")])
@@ -1980,18 +1978,16 @@ (define_insn "*vsx_nfmsv4sf4"
[(set_attr "type" "vecfloat")])
(define_insn "*vsx_nfmsv2df4"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,wd,?wa,?wa")
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,wa")
(neg:V2DF
(fma:V2DF
- (match_operand:V2DF 1 "vsx_register_operand" "%wd,wd,wa,wa")
- (match_operand:V2DF 2 "vsx_register_operand" "wd,0,wa,0")
+ (match_operand:V2DF 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:V2DF 2 "vsx_register_operand" "wa,0")
(neg:V2DF
- (match_operand:V2DF 3 "vsx_register_operand" "0,wd,0,wa")))))]
+ (match_operand:V2DF 3 "vsx_register_operand" "0,wa")))))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"@
xvnmsubadp %x0,%x1,%x2
- xvnmsubmdp %x0,%x1,%x3
- xvnmsubadp %x0,%x1,%x2
xvnmsubmdp %x0,%x1,%x3"
[(set_attr "type" "vecdouble")])
@@ -2399,7 +2395,7 @@ (define_insn "vsx_xvcvdpuxds"
(define_insn "vsx_xvcvdpsxws"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
- (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wd,wa")]
+ (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVDPSXWS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvdpsxws %x0,%x1"
@@ -2407,14 +2403,14 @@ (define_insn "vsx_xvcvdpsxws"
(define_insn "vsx_xvcvdpuxws"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
- (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wd,wa")]
+ (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVDPUXWS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvdpuxws %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvsxdsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVSXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
@@ -2422,7 +2418,7 @@ (define_insn "vsx_xvcvsxdsp"
[(set_attr "type" "vecfloat")])
(define_insn "vsx_xvcvuxdsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVUXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
@@ -2430,7 +2426,7 @@ (define_insn "vsx_xvcvuxdsp"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcdpsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_XVCDPSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
@@ -2440,7 +2436,7 @@ (define_insn "vsx_xvcdpsp"
;; Convert from 32-bit to 64-bit types
;; Provide both vector and scalar targets
(define_insn "vsx_xvcvsxwdp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVSXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
@@ -2456,7 +2452,7 @@ (define_insn "vsx_xvcvsxwdp_df"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVUXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
@@ -2473,7 +2469,7 @@ (define_insn "vsx_xvcvuxwdp_df"
(define_insn "vsx_xvcvspsxds"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
- (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wd,wa")]
+ (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVSPSXDS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvspsxds %x0,%x1"
@@ -2481,7 +2477,7 @@ (define_insn "vsx_xvcvspsxds"
(define_insn "vsx_xvcvspuxds"
[(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
- (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wd,wa")]
+ (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
UNSPEC_VSX_CVSPUXDS))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvspuxds %x0,%x1"
@@ -2826,10 +2822,10 @@ (define_expand "vunsignede_v2df"
;; since the xvrdpiz instruction does not truncate the value if the floating
;; point value is < LONG_MIN or > LONG_MAX.
(define_insn "*vsx_float_fix_v2df2"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wd,?wa")
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
(float:V2DF
(fix:V2DI
- (match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))]
+ (match_operand:V2DF 1 "vsx_register_operand" "wa,?wa"))))]
"TARGET_HARD_FLOAT
&& VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
@@ -3452,11 +3448,11 @@ (define_expand "vsx_xxpermdi_<mode>_be"
})
(define_insn "vsx_xxpermdi2_<mode>_1"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
(vec_select:VSX_D
(vec_concat:<VS_double>
- (match_operand:VSX_D 1 "vsx_register_operand" "wd")
- (match_operand:VSX_D 2 "vsx_register_operand" "wd"))
+ (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_D 2 "vsx_register_operand" "wa"))
(parallel [(match_operand 3 "const_0_to_1_operand" "")
(match_operand 4 "const_2_to_3_operand" "")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4277,17 +4273,17 @@ (define_insn "vsx_xxsldwi_<mode>"
;; Vector reduction insns and splitters
(define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v2df"
- [(set (match_operand:V2DF 0 "vfloat_operand" "=&wd,&?wa,wd,?wa")
+ [(set (match_operand:V2DF 0 "vfloat_operand" "=&wa,wa")
(VEC_reduc:V2DF
(vec_concat:V2DF
(vec_select:DF
- (match_operand:V2DF 1 "vfloat_operand" "wd,wa,wd,wa")
+ (match_operand:V2DF 1 "vfloat_operand" "wa,wa")
(parallel [(const_int 1)]))
(vec_select:DF
(match_dup 1)
(parallel [(const_int 0)])))
(match_dup 1)))
- (clobber (match_scratch:V2DF 2 "=0,0,&wd,&wa"))]
+ (clobber (match_scratch:V2DF 2 "=0,&wa"))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"#"
""
@@ -4345,19 +4341,19 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
;; to the top element of the V2DF array without doing an extract.
(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
- [(set (match_operand:DF 0 "vfloat_operand" "=&wa,&?wa,wa,?wa")
+ [(set (match_operand:DF 0 "vfloat_operand" "=&wa,wa")
(vec_select:DF
(VEC_reduc:V2DF
(vec_concat:V2DF
(vec_select:DF
- (match_operand:V2DF 1 "vfloat_operand" "wd,wa,wd,wa")
+ (match_operand:V2DF 1 "vfloat_operand" "wa,wa")
(parallel [(const_int 1)]))
(vec_select:DF
(match_dup 1)
(parallel [(const_int 0)])))
(match_dup 1))
(parallel [(const_int 1)])))
- (clobber (match_scratch:DF 2 "=0,0,&wd,&wa"))]
+ (clobber (match_scratch:DF 2 "=0,&wa"))]
"BYTES_BIG_ENDIAN && VECTOR_UNIT_VSX_P (V2DFmode)"
"#"
""
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index b0a7454..7be8521 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3196,7 +3196,7 @@ Altivec vector register
@item wa
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
-When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
+When using any of the register constraints (@code{wa}, @code{wf},
@code{wp}, @code{wq}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
@@ -3244,9 +3244,6 @@ asm ("xsaddqp %x0,%x1,%x2"
@noindent
is incorrect.
-@item wd
-VSX vector register to hold vector double data or NO_REGS.
-
@item we
VSX register if the @option{-mcpu=power9} and @option{-m64} options
were used or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/7] rs6000: ws -> wa
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
` (4 preceding siblings ...)
2019-06-04 16:20 ` [PATCH 1/7] rs6000: wi->wa, wt->wa Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 7/7] rs6000: wf " Segher Boessenkool
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"ws" is just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "ws"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_ws.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 4 ----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 30 +++++++++++++++---------------
gcc/config/rs6000/vsx.md | 30 +++++++++++++++---------------
gcc/doc/md.texi | 5 +----
6 files changed, 31 insertions(+), 42 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index afc071f..2228667 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -82,9 +82,6 @@ (define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]"
(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
"General purpose register if 64-bit instructions are enabled or NO_REGS.")
-(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
- "VSX vector register to hold scalar double values or NO_REGS.")
-
(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
"FP or VSX register to perform float operations under -mvsx or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 767721f..87f8bdf 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2514,7 +2514,6 @@ rs6000_debug_reg_global (void)
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
- "ws reg_class = %s\n"
"ww reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
@@ -2529,7 +2528,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3144,7 +3142,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wf - Preferred register class for V4SFmode.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
- ws - Register class to do ISA 2.06 DF operations.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
@@ -3159,7 +3156,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
- rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
}
/* Add conditional constraints based on various options, to allow us to
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index c91854a..c7fd7a2 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1262,7 +1262,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
- RS6000_CONSTRAINT_ws, /* VSX register for DF */
RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 45e0347..a0628c1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -469,10 +469,10 @@ (define_mode_attr zero_fp [(SF "j")
(TD "wn")])
; Definitions for 64-bit VSX
-(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
+(define_mode_attr f64_vsx [(DF "wa") (DD "wn")])
; Definitions for 64-bit direct move
-(define_mode_attr f64_dm [(DF "ws") (DD "d")])
+(define_mode_attr f64_dm [(DF "wa") (DD "d")])
; Definitions for 64-bit use of altivec registers
(define_mode_attr f64_av [(DF "v") (DD "wn")])
@@ -526,12 +526,12 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
; format.
-(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wa")])
+(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
; SF/DF constraint for arithmetic on VSX registers. This is intended to be
; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wa")])
+(define_mode_attr Fv2 [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -626,7 +626,7 @@ (define_mode_attr ptrm [(SI "m")
(DI "Y")])
(define_mode_attr rreg [(SF "f")
- (DF "ws")
+ (DF "wa")
(TF "f")
(TD "f")
(V4SF "wf")
@@ -4783,7 +4783,7 @@ (define_expand "extendsfdf2"
})
(define_insn_and_split "*extendsfdf2_fpr"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wa,?wa,wa,v")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
"TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
"@
@@ -4804,7 +4804,7 @@ (define_insn_and_split "*extendsfdf2_fpr"
(set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
(define_insn "*extendsfdf2_snan"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
"TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
"@
@@ -4821,7 +4821,7 @@ (define_expand "truncdfsf2"
(define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
+ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT"
"@
frsp %0,%1
@@ -6027,8 +6027,8 @@ (define_insn "fctiwuz_<mode>"
;; since the friz instruction does not truncate the value if the floating
;; point value is < LONG_MIN or > LONG_MAX.
(define_insn "*friz"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
- (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
+ (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
"TARGET_HARD_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
@@ -6223,7 +6223,7 @@ (define_expand "floatsisf2"
})
(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_FCFID && TARGET_HARD_FLOAT"
"@
@@ -6237,7 +6237,7 @@ (define_insn "floatdidf2"
; hit. We will split after reload to avoid the trip through the GPRs
(define_insn_and_split "*floatdidf2_mem"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
@@ -6257,7 +6257,7 @@ (define_expand "floatunsdidf2"
"")
(define_insn "*floatunsdidf2_fcfidu"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDU"
"@
@@ -6266,7 +6266,7 @@ (define_insn "*floatunsdidf2_fcfidu"
[(set_attr "type" "fp")])
(define_insn_and_split "*floatunsdidf2_mem"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
@@ -7855,7 +7855,7 @@ (define_insn_and_split "extenddf<mode>2_fprs"
(define_insn_and_split "extenddf<mode>2_vsx"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
(float_extend:IBM128
- (match_operand:DF 1 "nonimmediate_operand" "ws,m")))]
+ (match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
"TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bc12158..57f9963 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -115,7 +115,7 @@ (define_mode_attr VSr [(V16QI "v")
(V2DI "wd")
(V2DF "wd")
(DI "wa")
- (DF "ws")
+ (DF "wa")
(SF "ww")
(TF "wp")
(KF "wq")
@@ -127,7 +127,7 @@ (define_mode_attr VSr [(V16QI "v")
;; hold the data
(define_mode_attr VSr2 [(V2DF "wd")
(V4SF "wf")
- (DF "ws")
+ (DF "wa")
(SF "ww")
(DI "wa")
(KF "wq")
@@ -135,20 +135,20 @@ (define_mode_attr VSr2 [(V2DF "wd")
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
- (DF "ws")
+ (DF "wa")
(SF "ww")
(DI "wa")
(KF "wq")
(TF "wp")])
;; Map the register class for sp<->dp float conversions, destination
-(define_mode_attr VSr4 [(SF "ws")
+(define_mode_attr VSr4 [(SF "wa")
(DF "f")
(V2DF "wd")
(V4SF "v")])
;; Map the register class for sp<->dp float conversions, source
-(define_mode_attr VSr5 [(SF "ws")
+(define_mode_attr VSr5 [(SF "wa")
(DF "f")
(V2DF "v")
(V4SF "wd")])
@@ -163,7 +163,7 @@ (define_mode_attr VSa [(V16QI "wa")
(V2DI "wa")
(V2DF "wa")
(DI "wa")
- (DF "ws")
+ (DF "wa")
(SF "ww")
(V1TI "wa")
(TI "wa")
@@ -277,7 +277,7 @@ (define_mode_attr VS_double [(V4SI "V8SI")
;; Map register class for 64-bit element in 128-bit vector for normal register
;; to register moves
-(define_mode_attr VS_64reg [(V2DF "ws")
+(define_mode_attr VS_64reg [(V2DF "wa")
(V2DI "wa")])
;; Iterators for loading constants with xxspltib
@@ -2199,7 +2199,7 @@ (define_insn "vsx_<VS_spdp_insn>"
;; xscvspdp, represent the scalar SF type as V4SF
(define_insn "vsx_xscvspdp"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+ [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
@@ -2237,14 +2237,14 @@ (define_insn "vsx_xscvdpsp_scalar"
;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
(define_insn "vsx_xscvdpspn"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=ww")
- (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "ws")]
+ (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
"xscvdpspn %x0,%x1"
[(set_attr "type" "fp")])
(define_insn "vsx_xscvspdpn"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+ [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDPN))]
"TARGET_XSCVSPDPN"
@@ -2453,7 +2453,7 @@ (define_insn "vsx_xvcvsxwdp"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvsxwdp_df"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+ [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXWDP))]
"TARGET_VSX"
@@ -2469,7 +2469,7 @@ (define_insn "vsx_xvcvuxwdp"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp_df"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+ [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXWDP))]
"TARGET_VSX"
@@ -3771,7 +3771,7 @@ (define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
;; Optimize double d = (double) vec_extract (vi, <n>)
;; Get the element into the top position and use XVCVSWDP/XVCVUWDP
(define_insn_and_split "*vsx_extract_si_<uns>float_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=ws")
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
(any_float:DF
(vec_select:SI
(match_operand:V4SI 1 "gpc_reg_operand" "v")
@@ -3818,7 +3818,7 @@ (define_insn_and_split "*vsx_extract_si_<uns>float_<mode>"
(match_operand:V4SI 1 "gpc_reg_operand" "v")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
(clobber (match_scratch:V4SI 3 "=v"))
- (clobber (match_scratch:DF 4 "=ws"))]
+ (clobber (match_scratch:DF 4 "=wa"))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& 1"
@@ -4350,7 +4350,7 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
;; to the top element of the V2DF array without doing an extract.
(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
- [(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws")
+ [(set (match_operand:DF 0 "vfloat_operand" "=&wa,&?wa,wa,?wa")
(vec_select:DF
(VEC_reduc:V2DF
(vec_concat:V2DF
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0fbe332..b0a7454 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
-@code{wp}, @code{wq}, @code{ws}, or @code{ww})
+@code{wp}, @code{wq}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@@ -3266,9 +3266,6 @@ VSX register to use for IEEE 128-bit floating point, or NO_REGS.
@item wr
General purpose register if 64-bit instructions are enabled or NO_REGS.
-@item ws
-VSX vector register to hold scalar double values or NO_REGS.
-
@item ww
FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/7] rs6000: Delete VS_64reg
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 2/7] rs6000: wv -> v+p7v Segher Boessenkool
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
<VS_64reg> now always is "wa". Make that simplification.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete.
(*vsx_extract_<P:mode>_<VSX_D:mode>_load): Adjust.
(vsx_splat_<mode>_reg): Adjust.
---
gcc/config/rs6000/vsx.md | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 57f9963..60b3a8d 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -275,11 +275,6 @@ (define_mode_attr VS_double [(V4SI "V8SI")
(V2DF "V4DF")
(V1TI "V2TI")])
-;; Map register class for 64-bit element in 128-bit vector for normal register
-;; to register moves
-(define_mode_attr VS_64reg [(V2DF "wa")
- (V2DI "wa")])
-
;; Iterators for loading constants with xxspltib
(define_mode_iterator VSINT_84 [V4SI V2DI DI SI])
(define_mode_iterator VSINT_842 [V8HI V4SI V2DI])
@@ -3252,7 +3247,7 @@ (define_insn "vsx_extract_<mode>"
;; Optimize extracting a single scalar element from memory.
(define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
- [(set (match_operand:<VS_scalar> 0 "register_operand" "=<VSX_D:VS_64reg>,wr")
+ [(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr")
(vec_select:<VSX_D:VS_scalar>
(match_operand:VSX_D 1 "memory_operand" "m,m")
(parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")])))
@@ -4118,7 +4113,7 @@ (define_expand "vsx_splat_<mode>"
(define_insn "vsx_splat_<mode>_reg"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>,we")
(vec_duplicate:VSX_D
- (match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VSX_D:VS_64reg>,b")))]
+ (match_operand:<VS_scalar> 1 "gpc_reg_operand" "wa,b")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 7/7] rs6000: wf -> wa
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
` (5 preceding siblings ...)
2019-06-04 16:20 ` [PATCH 3/7] rs6000: ws -> wa Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"wf" is just "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wf"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wf.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 --
gcc/config/rs6000/rs6000.c | 8 +----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/vsx.md | 74 +++++++++++++++++++---------------------
gcc/doc/md.texi | 5 +--
6 files changed, 38 insertions(+), 55 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 763e892..f45102b 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -62,9 +62,6 @@ (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"
(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
"VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
-(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
- "VSX vector register to hold vector float data or NO_REGS.")
-
;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
;; direct move directly, and movsf can't to move between the register sets.
;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2b996db..058b5ea 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2509,7 +2509,6 @@ rs6000_debug_reg_global (void)
"v reg_class = %s\n"
"wa reg_class = %s\n"
"we reg_class = %s\n"
- "wf reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
@@ -2522,7 +2521,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
@@ -3136,7 +3134,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
v - Altivec register.
wa - Any VSX register.
wc - Reserved to represent individual CR bits (used in LLVM).
- wf - Preferred register class for V4SFmode.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ww - Register class to do SF conversions in with VSX operations.
@@ -3149,10 +3146,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
if (TARGET_VSX)
- {
- rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
- }
+ rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
/* Add conditional constraints based on various options, to allow us to
collapse multiple insn patterns. */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 6719cc4..d59f925 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1257,7 +1257,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_v, /* Altivec registers */
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
- RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4cf9082..f596987 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -624,7 +624,7 @@ (define_mode_attr rreg [(SF "f")
(DF "wa")
(TF "f")
(TD "f")
- (V4SF "wf")
+ (V4SF "wa")
(V2DF "wa")])
(define_mode_attr rreg2 [(SF "f")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 70276a8..4450537 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -111,7 +111,7 @@ (define_mode_attr VSs [(V16QI "sp")
(define_mode_attr VSr [(V16QI "v")
(V8HI "v")
(V4SI "v")
- (V4SF "wf")
+ (V4SF "wa")
(V2DI "wa")
(V2DF "wa")
(DI "wa")
@@ -126,7 +126,7 @@ (define_mode_attr VSr [(V16QI "v")
;; VSr2 is the preferred register class, VSr3 is any register class that will
;; hold the data
(define_mode_attr VSr2 [(V2DF "wa")
- (V4SF "wf")
+ (V4SF "wa")
(DF "wa")
(SF "ww")
(DI "wa")
@@ -1904,17 +1904,15 @@ (define_insn "*vsx_tsqrt<mode>2_internal"
;; multiply.
(define_insn "*vsx_fmav4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v")
- (match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v")
- (match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))]
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
- xvmaddasp %x0,%x1,%x2
- xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
@@ -1961,19 +1959,17 @@ (define_insn "*vsx_nfma<mode>4"
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
- (match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v")
- (match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v")
+ (match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
+ (match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
- (match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))))]
+ (match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
- xvnmsubasp %x0,%x1,%x2
- xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
@@ -2410,24 +2406,24 @@ (define_insn "vsx_xvcvdpuxws"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvsxdsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
- (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxdsp %x0,%x1"
[(set_attr "type" "vecfloat")])
(define_insn "vsx_xvcvuxdsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
- (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxdsp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcdpsp"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
- (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+ (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_XVCDPSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvdpsp %x0,%x1"
@@ -2436,8 +2432,8 @@ (define_insn "vsx_xvcdpsp"
;; Convert from 32-bit to 64-bit types
;; Provide both vector and scalar targets
(define_insn "vsx_xvcvsxwdp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
- (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+ (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxwdp %x0,%x1"
@@ -2452,8 +2448,8 @@ (define_insn "vsx_xvcvsxwdp_df"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp"
- [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
- (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
+ [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+ (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxwdp %x0,%x1"
@@ -4225,11 +4221,11 @@ (define_insn "vsx_xxspltd_<mode>"
;; V4SF/V4SI interleave
(define_insn "vsx_xxmrghw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
- (match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wa,<VSa>"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4242,11 +4238,11 @@ (define_insn "vsx_xxmrghw_<mode>"
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxmrglw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
- (match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wa,?<VSa>"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -4300,12 +4296,12 @@ (define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v2df"
(set_attr "type" "veccomplex")])
(define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
- [(set (match_operand:V4SF 0 "vfloat_operand" "=wf,?wa")
+ [(set (match_operand:V4SF 0 "vfloat_operand" "=wa")
(VEC_reduc:V4SF
(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
- (match_operand:V4SF 1 "vfloat_operand" "wf,wa")))
- (clobber (match_scratch:V4SF 2 "=&wf,&wa"))
- (clobber (match_scratch:V4SF 3 "=&wf,&wa"))]
+ (match_operand:V4SF 1 "vfloat_operand" "wa")))
+ (clobber (match_scratch:V4SF 2 "=&wa"))
+ (clobber (match_scratch:V4SF 3 "=&wa"))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""
@@ -4372,15 +4368,15 @@ (define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
(set_attr "type" "veccomplex")])
(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf_scalar"
- [(set (match_operand:SF 0 "vfloat_operand" "=f,?f")
+ [(set (match_operand:SF 0 "vfloat_operand" "=f")
(vec_select:SF
(VEC_reduc:V4SF
(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
- (match_operand:V4SF 1 "vfloat_operand" "wf,wa"))
+ (match_operand:V4SF 1 "vfloat_operand" "wa"))
(parallel [(const_int 3)])))
- (clobber (match_scratch:V4SF 2 "=&wf,&wa"))
- (clobber (match_scratch:V4SF 3 "=&wf,&wa"))
- (clobber (match_scratch:V4SF 4 "=0,0"))]
+ (clobber (match_scratch:V4SF 2 "=&wa"))
+ (clobber (match_scratch:V4SF 3 "=&wa"))
+ (clobber (match_scratch:V4SF 4 "=0"))]
"BYTES_BIG_ENDIAN && VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 7be8521..453296d 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3196,7 +3196,7 @@ Altivec vector register
@item wa
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
-When using any of the register constraints (@code{wa}, @code{wf},
+When using any of the register constraints (@code{wa},
@code{wp}, @code{wq}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
@@ -3248,9 +3248,6 @@ is incorrect.
VSX register if the @option{-mcpu=power9} and @option{-m64} options
were used or NO_REGS.
-@item wf
-VSX vector register to hold vector float data or NO_REGS.
-
@item wn
No register (NO_REGS).
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/7] rs6000: wi->wa, wt->wa
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
` (3 preceding siblings ...)
2019-06-04 16:20 ` [PATCH 5/7] rs6000: Delete Fv2 Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 3/7] rs6000: ws -> wa Segher Boessenkool
2019-06-04 16:20 ` [PATCH 7/7] rs6000: wf " Segher Boessenkool
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"wi" and "wt" mean just the same as "wa" these days. Change them to
the simpler name.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wi"):
Delete.
(define_register_constraint "wt"): Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wi and RS6000_CONSTRAINT_wt.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 6 ----
gcc/config/rs6000/rs6000.c | 8 -----
gcc/config/rs6000/rs6000.h | 2 --
gcc/config/rs6000/rs6000.md | 78 ++++++++++++++++++++--------------------
gcc/config/rs6000/vsx.md | 16 ++++-----
gcc/doc/md.texi | 12 ++-----
6 files changed, 49 insertions(+), 73 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 844e947..edf825d 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -68,9 +68,6 @@ (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
"VSX vector register to hold vector float data or NO_REGS.")
-(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
- "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
-
;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
;; direct move directly, and movsf can't to move between the register sets.
;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode
@@ -88,9 +85,6 @@ (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
"VSX vector register to hold scalar double values or NO_REGS.")
-(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
- "VSX vector register to hold 128 bit integer or NO_REGS.")
-
(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
"Altivec register to use for double loads/stores or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 3aa19db..83def7c2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2511,12 +2511,10 @@ rs6000_debug_reg_global (void)
"wd reg_class = %s\n"
"we reg_class = %s\n"
"wf reg_class = %s\n"
- "wi reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
"ws reg_class = %s\n"
- "wt reg_class = %s\n"
"wv reg_class = %s\n"
"ww reg_class = %s\n"
"wx reg_class = %s\n"
@@ -2529,12 +2527,10 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
@@ -3148,11 +3144,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wc - Reserved to represent individual CR bits (used in LLVM).
wd - Preferred register class for V2DFmode.
wf - Preferred register class for V4SFmode.
- wi - FP or VSX register to hold 64-bit integers for VSX insns.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ws - Register class to do ISA 2.06 DF operations.
- wt - VSX register for TImode in VSX registers.
wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
@@ -3170,8 +3164,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
- rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
}
/* Add conditional constraints based on various options, to allow us to
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3201152..6cfb0ad 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1259,12 +1259,10 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
- RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_ws, /* VSX register for DF */
- RS6000_CONSTRAINT_wt, /* VSX register for TImode */
RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c49614c..07c27a1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -526,12 +526,12 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
; format.
-(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")])
+(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wa")])
; SF/DF constraint for arithmetic on VSX registers. This is intended to be
; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wi")])
+(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -656,7 +656,7 @@ (define_mode_iterator BOOL_128 [TI
;; either.
;; Mode attribute for boolean operation register constraints for output
-(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
+(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
(PTI "&r,r,r")
(V16QI "wa,v,&?r,?r,?r")
(V8HI "wa,v,&?r,?r,?r")
@@ -667,7 +667,7 @@ (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
(V1TI "wa,v,&?r,?r,?r")])
;; Mode attribute for boolean operation register constraints for operand1
-(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
+(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
(PTI "r,0,r")
(V16QI "wa,v,r,0,r")
(V8HI "wa,v,r,0,r")
@@ -678,7 +678,7 @@ (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
(V1TI "wa,v,r,0,r")])
;; Mode attribute for boolean operation register constraints for operand2
-(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
+(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
(PTI "r,r,0")
(V16QI "wa,v,r,r,0")
(V8HI "wa,v,r,r,0")
@@ -691,7 +691,7 @@ (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
;; Mode attribute for boolean operation register constraints for operand1
;; for one_cmpl. To simplify things, we repeat the constraint where 0
;; is used for operand1 or operand2
-(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
+(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
(PTI "r,0,0")
(V16QI "wa,v,r,0,0")
(V8HI "wa,v,r,0,0")
@@ -835,7 +835,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2"
(define_insn "zero_extendsi<mode>2"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wi,r,wa")
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
(zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
""
"@
@@ -1020,7 +1020,7 @@ (define_insn_and_split "*extendhi<mode>2_dot2"
(define_insn "extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand"
- "=r, r, d, wa, wi, v, v, wr")
+ "=r, r, d, wa, wa, v, v, wr")
(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
"YZ, r, Z, Z, r, v, v, ?wa")))]
""
@@ -5234,7 +5234,7 @@ (define_insn "*xxsel<mode>"
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,v")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,v")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX"
@@ -5254,7 +5254,7 @@ (define_insn "lfiwax"
(define_insn_and_split "floatsi<mode>2_lfiwax"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
- (clobber (match_scratch:DI 2 "=wi"))]
+ (clobber (match_scratch:DI 2 "=wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
@@ -5295,7 +5295,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
(float:SFDF
(sign_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
- (clobber (match_scratch:DI 2 "=wi"))]
+ (clobber (match_scratch:DI 2 "=wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
@@ -5315,7 +5315,7 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,wi,wa")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa,wa,wa")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX"
@@ -5330,7 +5330,7 @@ (define_insn "lfiwzx"
(define_insn_and_split "floatunssi<mode>2_lfiwzx"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
- (clobber (match_scratch:DI 2 "=wi"))]
+ (clobber (match_scratch:DI 2 "=wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
@@ -5370,7 +5370,7 @@ (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
(unsigned_float:SFDF
(zero_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
- (clobber (match_scratch:DI 2 "=wi"))]
+ (clobber (match_scratch:DI 2 "=wa"))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
@@ -5569,7 +5569,7 @@ (define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
(float:FP_ISA3
(match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
- (clobber (match_scratch:DI 2 "=v,wi,v"))
+ (clobber (match_scratch:DI 2 "=v,wa,v"))
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,v"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
@@ -5622,7 +5622,7 @@ (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
(unsigned_float:FP_ISA3
(match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
- (clobber (match_scratch:DI 2 "=v,wi,wa"))
+ (clobber (match_scratch:DI 2 "=v,wa,wa"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
@@ -5748,7 +5748,7 @@ (define_expand "fix_trunc<mode>di2"
"")
(define_insn "*fix_trunc<mode>di2_fctidz"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"@
@@ -5765,7 +5765,7 @@ (define_insn "*fix_trunc<mode>di2_fctidz"
(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
[(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=d,wa,r")
(any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")))
- (clobber (match_scratch:SI 2 "=X,X,wi"))]
+ (clobber (match_scratch:SI 2 "=X,X,wa"))]
"TARGET_DIRECT_MOVE"
"@
fctiw<u>z %0,%1
@@ -5867,7 +5867,7 @@ (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
(set_attr "type" "fp")])
(define_insn "fixuns_trunc<mode>di2"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
"TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
"@
@@ -6002,7 +6002,7 @@ (define_expand "rs6000_set_fpscr_drn"
;; because the first makes it clear that operand 0 is not live
;; before the instruction.
(define_insn "fctiwz_<mode>"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(unspec:DI [(fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWZ))]
@@ -6013,7 +6013,7 @@ (define_insn "fctiwz_<mode>"
[(set_attr "type" "fp")])
(define_insn "fctiwuz_<mode>"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa")
(unspec:DI [(unsigned_fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWUZ))]
@@ -6224,7 +6224,7 @@ (define_expand "floatsisf2"
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
- (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
+ (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_FCFID && TARGET_HARD_FLOAT"
"@
fcfid %0,%1
@@ -6239,7 +6239,7 @@ (define_insn "floatdidf2"
(define_insn_and_split "*floatdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
- (clobber (match_scratch:DI 2 "=d,wi"))]
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"#"
"&& reload_completed"
@@ -6258,7 +6258,7 @@ (define_expand "floatunsdidf2"
(define_insn "*floatunsdidf2_fcfidu"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
- (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
+ (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDU"
"@
fcfidu %0,%1
@@ -6268,7 +6268,7 @@ (define_insn "*floatunsdidf2_fcfidu"
(define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
- (clobber (match_scratch:DI 2 "=d,wi"))]
+ (clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"#"
"&& reload_completed"
@@ -6301,7 +6301,7 @@ (define_expand "floatdisf2"
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
- (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
+ (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDS"
"@
fcfids %0,%1
@@ -6312,7 +6312,7 @@ (define_insn "floatdisf2_fcfids"
(define_insn_and_split "*floatdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
(float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
- (clobber (match_scratch:DI 2 "=d,d,wi"))]
+ (clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDS"
"#"
"&& reload_completed"
@@ -6382,7 +6382,7 @@ (define_expand "floatunsdisf2"
(define_insn "floatunsdisf2_fcfidus"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
- (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
+ (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
"TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"@
fcfidus %0,%1
@@ -6393,7 +6393,7 @@ (define_insn "floatunsdisf2_fcfidus"
(define_insn_and_split "*floatunsdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
(unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
- (clobber (match_scratch:DI 2 "=d,d,wi"))]
+ (clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"#"
"&& reload_completed"
@@ -8742,12 +8742,12 @@ (define_insn_and_split "reload_gpr_from_vsxsf"
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- r, wY, Z, ^v, $wv, ^wi,
- wa, wa, wv, wi, *i, wv,
+ r, wY, Z, ^v, $wv, ^wa,
+ wa, wa, wv, wa, *i, wv,
wv")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- IJKnF, ^v, $wv, wY, Z, ^wi,
+ IJKnF, ^v, $wv, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
"! TARGET_POWERPC64
@@ -8826,15 +8826,15 @@ (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
m, ^d, ^d, wY, Z, $v,
- $wv, ^wi, wa, wa, wv, wi,
- wi, wv, wv, r, *h, *h,
- ?r, ?wi")
+ $wv, ^wa, wa, wa, wv, wa,
+ wa, wv, wv, r, *h, *h,
+ ?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r, I, L, nF,
^d, m, ^d, ^v, $wv, wY,
- Z, ^wi, Oj, wM, OjwM, Oj,
+ Z, ^wa, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
- wi, r"))]
+ wa, r"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -12654,7 +12654,7 @@ (define_insn "<bd>_<mode>"
(const_int 1))
(label_ref (match_operand 0))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
@@ -12730,7 +12730,7 @@ (define_insn "<bd>tf_<mode>"
(const_int 0)]))
(label_ref (match_operand 0))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:P 5 "=X,X,&r,r"))
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6108451..f5ef5b8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -114,13 +114,13 @@ (define_mode_attr VSr [(V16QI "v")
(V4SF "wf")
(V2DI "wd")
(V2DF "wd")
- (DI "wi")
+ (DI "wa")
(DF "ws")
(SF "ww")
(TF "wp")
(KF "wq")
(V1TI "v")
- (TI "wt")])
+ (TI "wa")])
;; Map the register class used for float<->int conversions (floating point side)
;; VSr2 is the preferred register class, VSr3 is any register class that will
@@ -129,7 +129,7 @@ (define_mode_attr VSr2 [(V2DF "wd")
(V4SF "wf")
(DF "ws")
(SF "ww")
- (DI "wi")
+ (DI "wa")
(KF "wq")
(TF "wp")])
@@ -137,7 +137,7 @@ (define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
(DF "ws")
(SF "ww")
- (DI "wi")
+ (DI "wa")
(KF "wq")
(TF "wp")])
@@ -162,11 +162,11 @@ (define_mode_attr VSa [(V16QI "wa")
(V4SF "wa")
(V2DI "wa")
(V2DF "wa")
- (DI "wi")
+ (DI "wa")
(DF "ws")
(SF "ww")
(V1TI "wa")
- (TI "wt")
+ (TI "wa")
(TF "wp")
(KF "wq")])
@@ -278,7 +278,7 @@ (define_mode_attr VS_double [(V4SI "V8SI")
;; Map register class for 64-bit element in 128-bit vector for normal register
;; to register moves
(define_mode_attr VS_64reg [(V2DF "ws")
- (V2DI "wi")])
+ (V2DI "wa")])
;; Iterators for loading constants with xxspltib
(define_mode_iterator VSINT_84 [V4SI V2DI DI SI])
@@ -4151,7 +4151,7 @@ (define_insn "vsx_splat_v4si_di"
[(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
(vec_duplicate:V4SI
(truncate:SI
- (match_operand:DI 1 "gpc_reg_operand" "wi,r"))))]
+ (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))]
"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
"@
xxspltw %x0,%x1,1
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index cf51326..ccab18b 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3196,10 +3196,8 @@ Altivec vector register
@item wa
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
-When using any of the register constraints (@code{wa}, @code{wd},
-@code{wf}, @code{wi},
-@code{wp}, @code{wq}, @code{ws},
-@code{wt}, @code{wv}, or @code{ww})
+When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
+@code{wp}, @code{wq}, @code{ws}, @code{wv}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@@ -3256,9 +3254,6 @@ were used or NO_REGS.
@item wf
VSX vector register to hold vector float data or NO_REGS.
-@item wi
-FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
-
@item wn
No register (NO_REGS).
@@ -3274,9 +3269,6 @@ General purpose register if 64-bit instructions are enabled or NO_REGS.
@item ws
VSX vector register to hold scalar double values or NO_REGS.
-@item wt
-VSX vector register to hold 128 bit integer or NO_REGS.
-
@item wv
Altivec register to use for double loads/stores or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/7] rs6000: Delete Fv2
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
` (2 preceding siblings ...)
2019-06-04 16:20 ` [PATCH 6/7] rs6000: wd -> wa Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 1/7] rs6000: wi->wa, wt->wa Segher Boessenkool
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
<Fv2> always is "wa".
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (define_mode_attr Fv2): Delete.
(rest of file): Adjust.
---
gcc/config/rs6000/rs6000.md | 77 +++++++++++++++++++++------------------------
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a0628c1..8053d5a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -528,11 +528,6 @@ (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
; format.
(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
-; SF/DF constraint for arithmetic on VSX registers. This is intended to be
-; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
-; instructions added in ISA 2.07 (power8)
-(define_mode_attr Fv2 [(SF "wa") (DF "wa") (DI "wa")])
-
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
@@ -4638,9 +4633,9 @@ (define_expand "add<mode>3"
"")
(define_insn "*add<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
fadd<Ftrad> %0,%1,%2
@@ -4656,9 +4651,9 @@ (define_expand "sub<mode>3"
"")
(define_insn "*sub<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
fsub<Ftrad> %0,%1,%2
@@ -4674,9 +4669,9 @@ (define_expand "mul<mode>3"
"")
(define_insn "*mul<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
fmul<Ftrad> %0,%1,%2
@@ -4700,9 +4695,9 @@ (define_expand "div<mode>3"
})
(define_insn "*div<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
fdiv<Ftrad> %0,%1,%2
@@ -4711,8 +4706,8 @@ (define_insn "*div<mode>3_fpr"
(set_attr "isa" "*,<Fisa>")])
(define_insn "*sqrt<mode>2_internal"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@
fsqrt<Ftrad> %0,%1
@@ -4739,8 +4734,8 @@ (define_expand "sqrt<mode>2"
;; Floating point reciprocal approximation
(define_insn "fre<Fs>"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_FRES))]
"TARGET_<FFRE>"
"@
@@ -4750,8 +4745,8 @@ (define_insn "fre<Fs>"
(set_attr "isa" "*,<Fisa>")])
(define_insn "*rsqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")]
UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@
@@ -4763,8 +4758,8 @@ (define_insn "*rsqrt<mode>2"
;; Floating point comparisons
(define_insn "*cmp<mode>_fpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
- (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa")))]
"TARGET_HARD_FLOAT"
"@
fcmpu %0,%1,%2
@@ -13374,11 +13369,11 @@ (define_expand "fma<mode>4"
"")
(define_insn "*fma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))]
"TARGET_HARD_FLOAT"
"@
fmadd<Ftrad> %0,%1,%2,%3
@@ -13398,11 +13393,11 @@ (define_expand "fms<mode>4"
"")
(define_insn "*fms<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
- (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
fmsub<Ftrad> %0,%1,%2,%3
@@ -13445,12 +13440,12 @@ (define_expand "nfma<mode>4"
"")
(define_insn "*nfma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa"))))]
"TARGET_HARD_FLOAT"
"@
fnmadd<Ftrad> %0,%1,%2,%3
@@ -13471,13 +13466,13 @@ (define_expand "nfms<mode>4"
"")
(define_insn "*nfmssf4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,wa,wa")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,wa,wa")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,wa,0")
(neg:SFDF
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))]
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,wa")))))]
"TARGET_HARD_FLOAT"
"@
fnmsub<Ftrad> %0,%1,%2,%3
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/7] rs6000: wv -> v+p7v
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
2019-06-04 16:20 ` [PATCH 4/7] rs6000: Delete VS_64reg Segher Boessenkool
@ 2019-06-04 16:20 ` Segher Boessenkool
2019-06-04 16:20 ` [PATCH 6/7] rs6000: wd -> wa Segher Boessenkool
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Segher Boessenkool @ 2019-06-04 16:20 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
"wv" is "v", but only if VSX is enabled (otherwise it's NO_REGS). So
this patch sets "isa" "p7v" to all alternatives that used "wv" before
(and that do not already need a later ISA), and changes the constraint.
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wv"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wv.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
---
gcc/config/rs6000/constraints.md | 3 ---
gcc/config/rs6000/rs6000.c | 4 ----
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.md | 32 ++++++++++++++++----------------
gcc/config/rs6000/vsx.md | 8 ++++----
gcc/doc/md.texi | 5 +----
6 files changed, 21 insertions(+), 32 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index edf825d..afc071f 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -85,9 +85,6 @@ (define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
"VSX vector register to hold scalar double values or NO_REGS.")
-(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]"
- "Altivec register to use for double loads/stores or NO_REGS.")
-
(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
"FP or VSX register to perform float operations under -mvsx or NO_REGS.")
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 83def7c2..767721f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2515,7 +2515,6 @@ rs6000_debug_reg_global (void)
"wq reg_class = %s\n"
"wr reg_class = %s\n"
"ws reg_class = %s\n"
- "wv reg_class = %s\n"
"ww reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
@@ -2531,7 +2530,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -3147,7 +3145,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ws - Register class to do ISA 2.06 DF operations.
- wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
@@ -3163,7 +3160,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
}
/* Add conditional constraints based on various options, to allow us to
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 6cfb0ad..c91854a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1263,7 +1263,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
RS6000_CONSTRAINT_ws, /* VSX register for DF */
- RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 07c27a1..45e0347 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -475,7 +475,7 @@ (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
(define_mode_attr f64_dm [(DF "ws") (DD "d")])
; Definitions for 64-bit use of altivec registers
-(define_mode_attr f64_av [(DF "wv") (DD "wn")])
+(define_mode_attr f64_av [(DF "v") (DD "wn")])
; Definitions for 64-bit access to ISA 3.0 (power9) vector
(define_mode_attr f64_p9 [(DF "v") (DD "wn")])
@@ -7611,7 +7611,7 @@ (define_insn "*mov<mode>_hardfloat32"
8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
- *, *, *, *, *,
+ p7v, p7v, *, *, *,
*, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -7682,7 +7682,7 @@ (define_insn "*mov<mode>_hardfloat64"
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
- *, *, *, *, *,
+ p7v, p7v, *, *, *,
*, *, *, *, *,
*, p8v, p8v")])
@@ -8742,12 +8742,12 @@ (define_insn_and_split "reload_gpr_from_vsxsf"
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- r, wY, Z, ^v, $wv, ^wa,
- wa, wa, wv, wa, *i, wv,
- wv")
+ r, wY, Z, ^v, $v, ^wa,
+ wa, wa, v, wa, *i, v,
+ v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- IJKnF, ^v, $wv, wY, Z, ^wa,
+ IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
"! TARGET_POWERPC64
@@ -8786,9 +8786,9 @@ (define_insn "*movdi_internal32"
4")
(set_attr "isa"
"*, *, *, *, *, *,
- *, p9v, *, p9v, *, *,
- p9v, p9v, *, *, *, *,
- *")])
+ *, p9v, p7v, p9v, p7v, *,
+ p9v, p9v, p7v, *, *, p7v,
+ p7v")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand")
@@ -8826,12 +8826,12 @@ (define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
m, ^d, ^d, wY, Z, $v,
- $wv, ^wa, wa, wa, wv, wa,
- wa, wv, wv, r, *h, *h,
+ $v, ^wa, wa, wa, v, wa,
+ wa, v, v, r, *h, *h,
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r, I, L, nF,
- ^d, m, ^d, ^v, $wv, wY,
+ ^d, m, ^d, ^v, $v, wY,
Z, ^wa, Oj, wM, OjwM, Oj,
wM, wS, wB, *h, r, 0,
wa, r"))]
@@ -8880,9 +8880,9 @@ (define_insn "*movdi_internal64"
4, 4")
(set_attr "isa"
"*, *, *, *, *, *,
- *, *, *, p9v, *, p9v,
- *, *, p9v, p9v, *, *,
- *, *, *, *, *, *,
+ *, *, *, p9v, p7v, p9v,
+ p7v, *, p9v, p9v, p7v, *,
+ *, p7v, p7v, *, *, *,
p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f5ef5b8..bc12158 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3273,7 +3273,7 @@ (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
(define_insn "*vsx_extract_<mode>_store"
[(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,wY")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "register_operand" "d,wv,v")
+ (match_operand:VSX_D 1 "register_operand" "d,v,v")
(parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
@@ -3281,7 +3281,7 @@ (define_insn "*vsx_extract_<mode>_store"
stxsdx %x1,%y0
stxsd %1,%0"
[(set_attr "type" "fpstore")
- (set_attr "isa" "*,*,p9v")])
+ (set_attr "isa" "*,p7v,p9v")])
;; Variable V2DI/V2DF extract shift
(define_insn "vsx_vslo_<mode>"
@@ -3346,7 +3346,7 @@ (define_insn_and_split "vsx_extract_v4sf"
(set_attr "type" "fp")])
(define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
- [(set (match_operand:SF 0 "register_operand" "=f,wv,v,?r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
(match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
@@ -3361,7 +3361,7 @@ (define_insn_and_split "*vsx_extract_v4sf_<mode>_load"
}
[(set_attr "type" "fpload,fpload,fpload,load")
(set_attr "length" "8")
- (set_attr "isa" "*,*,p9v,*")])
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract
(define_insn_and_split "vsx_extract_v4sf_var"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index ccab18b..0fbe332 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3197,7 +3197,7 @@ Altivec vector register
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
-@code{wp}, @code{wq}, @code{ws}, @code{wv}, or @code{ww})
+@code{wp}, @code{wq}, @code{ws}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@@ -3269,9 +3269,6 @@ General purpose register if 64-bit instructions are enabled or NO_REGS.
@item ws
VSX vector register to hold scalar double values or NO_REGS.
-@item wv
-Altivec register to use for double loads/stores or NO_REGS.
-
@item ww
FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
--
1.8.3.1
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-06-04 16:20 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-04 16:19 [PATCH 0/7] rs6000: More constraint updates Segher Boessenkool
2019-06-04 16:20 ` [PATCH 4/7] rs6000: Delete VS_64reg Segher Boessenkool
2019-06-04 16:20 ` [PATCH 2/7] rs6000: wv -> v+p7v Segher Boessenkool
2019-06-04 16:20 ` [PATCH 6/7] rs6000: wd -> wa Segher Boessenkool
2019-06-04 16:20 ` [PATCH 5/7] rs6000: Delete Fv2 Segher Boessenkool
2019-06-04 16:20 ` [PATCH 1/7] rs6000: wi->wa, wt->wa Segher Boessenkool
2019-06-04 16:20 ` [PATCH 3/7] rs6000: ws -> wa Segher Boessenkool
2019-06-04 16:20 ` [PATCH 7/7] rs6000: wf " Segher Boessenkool
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