Hi,

> AFAICT, you use hardware synchronisation instruction for EMMODEL_SEQ,
> and compiler memory barriers for all other memory models (except
> MEMMODEL_RELAXED).  That makes no sense; either the platform needs
> explicit instructions for memory coherency, or it doesn't.

Indeed, we on purpose misused the sync primitive to compensate for the lack of data memory barrier (dmb) primitive in the early SMP-HS cores. Now, I've checked and we can safely use the dmb primitive for all HS cores present today (no old HS ip without dmb is out there). Hence, I've refurbish the patch (attached) removing the old sync/software memory barrier combinations and use the newer dmb instruction for it.

Tested with dg.exp (when passing -matomic to gcc compiler line, the atomic tests are also successfully executed).

Thanks,
Claudiu