[PATCH 5/7] [ARC] Update (non)commutative_binary_comparison patterns.

[PATCH 5/7] [ARC] Update (non)commutative_binary_comparison patterns.

[Claudiu Zissulescu]

gcc/
2016-12-20  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (commutative_binary_comparison): Remove 'I'
	constraint. It is not valid for the pattern.
	(noncommutative_binary_comparison): Likewise.
---
 gcc/config/arc/arc.md | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index c0ad86c..743a844 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -948,15 +948,15 @@
   [(set (match_operand:CC_ZN 0 "cc_set_register" "")
 	(match_operator:CC_ZN 5 "zn_compare_operator"
 	  [(match_operator:SI 4 "commutative_operator"
-	     [(match_operand:SI 1 "register_operand" "%c,c,c")
-	      (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")])
+	     [(match_operand:SI 1 "register_operand" "%c,c")
+	      (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
 	   (const_int 0)]))
-   (clobber (match_scratch:SI 3 "=X,1,X"))]
+   (clobber (match_scratch:SI 3 "=X,X"))]
   ""
   "%O4.f 0,%1,%2"
   [(set_attr "type" "compare")
    (set_attr "cond" "set_zn")
-   (set_attr "length" "4,4,8")])
+   (set_attr "length" "4,8")])
 
 ; for flag setting 'add' instructions like if (a+b) { ...}
 ; the combiner needs this pattern
@@ -1050,15 +1050,15 @@
   [(set (match_operand:CC_ZN 0 "cc_set_register" "")
 	(match_operator:CC_ZN 5 "zn_compare_operator"
 	  [(match_operator:SI 4 "noncommutative_operator"
-	     [(match_operand:SI 1 "register_operand" "c,c,c")
-	      (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")])
+	     [(match_operand:SI 1 "register_operand" "c,c")
+	      (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
 	   (const_int 0)]))
-   (clobber (match_scratch:SI 3 "=X,1,X"))]
+   (clobber (match_scratch:SI 3 "=X,X"))]
   "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS"
   "%O4.f 0,%1,%2"
   [(set_attr "type" "compare")
    (set_attr "cond" "set_zn")
-   (set_attr "length" "4,4,8")])
+   (set_attr "length" "4,8")])
 
 (define_expand "bic_f_zn"
   [(parallel
-- 
1.9.1

[PATCH 6/7] [ARC] Prevent moving stores to the frame before the stack adjustment.

[Claudiu Zissulescu]

From: Claudiu Zissulescu <claziss@gmail.com>

If the stack pointer is needed, emit a special barrier that will prevent
the scheduler from moving stores to the frame before the stack adjustment.

2017-01-03  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_expand_prologue): Emit a special barrier
	to prevent store reordering.
	* config/arc/arc.md (UNSPEC_ARC_STKTIE): Define.
	(type): Add block type.
	(stack_tie): Define special instruction to be used in
	expand_prologue.
---
 gcc/config/arc/arc.c  | 10 +++++++++-
 gcc/config/arc/arc.md | 15 ++++++++++++++-
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index ff86f6c..0c4c901 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -3030,7 +3030,15 @@ arc_expand_prologue (void)
   frame_size_to_allocate -= first_offset;
   /* Allocate the stack frame.  */
   if (frame_size_to_allocate > 0)
-    frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
+    {
+      frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
+      /* If the frame pointer is needed, emit a special barrier that
+	 will prevent the scheduler from moving stores to the frame
+	 before the stack adjustment.  */
+      if (arc_frame_pointer_needed ())
+	emit_insn (gen_stack_tie (stack_pointer_rtx,
+				  hard_frame_pointer_rtx));
+    }
 
   /* Setup the gp register, if needed.  */
   if (crtl->uses_pic_offset_table)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 743a844..6cd192a 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -135,6 +135,7 @@
   UNSPEC_ARC_VMAC2HU
   UNSPEC_ARC_VMPY2H
   UNSPEC_ARC_VMPY2HU
+  UNSPEC_ARC_STKTIE
   ])
 
 (define_c_enum "vunspec" [
@@ -205,7 +206,7 @@
    simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc,
    simd_valign, simd_valign_with_acc, simd_vcontrol,
    simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem,
-   fpu"
+   fpu, block"
   (cond [(eq_attr "is_sfunc" "yes")
 	 (cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call")
 		(match_test "flag_pic") (const_string "sfunc")]
@@ -6547,6 +6548,18 @@
   (set_attr "predicable" "yes,no,no,yes,no")
   (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")])
 
+(define_insn "stack_tie"
+  [(set (mem:BLK (scratch))
+	(unspec:BLK [(match_operand:SI 0 "register_operand" "rb")
+		     (match_operand:SI 1 "register_operand" "rb")]
+		    UNSPEC_ARC_STKTIE))]
+  ""
+  ""
+  [(set_attr "length" "0")
+   (set_attr "iscompact" "false")
+   (set_attr "type" "block")]
+  )
+
 ;; include the arc-FPX instructions
 (include "fpx.md")
 
-- 
1.9.1

[PATCH 4/7] [ARC] Change predicate movv2hi to avoid scaled addresses.

[Claudiu Zissulescu]

From: Claudiu Zissulescu <claziss@gmail.com>

2016-12-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/simdext.md (movv2hi_insn): Change predicate to avoid
	scaled addresses.
---
 gcc/config/arc/simdext.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 5253033..6c102d3 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1356,7 +1356,7 @@
    }")
 
 (define_insn_and_split "*movv2hi_insn"
-  [(set (match_operand:V2HI 0 "nonimmediate_operand" "=r,r,r,m")
+  [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m")
 	(match_operand:V2HI 1 "general_operand"       "i,r,m,r"))]
   "(register_operand (operands[0], V2HImode)
     || register_operand (operands[1], V2HImode))"
-- 
1.9.1

[PATCH 1/7] [ARC] Make mulsi for A700 pattern commutative.

[Claudiu Zissulescu]

gcc/
2016-11-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (mulsi3_700): Make it commutative.
---
 gcc/config/arc/arc.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 71d076c..db5867c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2127,7 +2127,7 @@
 ; like MPY or MPYU.
 (define_insn "mulsi3_700"
  [(set (match_operand:SI 0 "mpy_dest_reg_operand"        "=Rcr,r,r,Rcr,r")
-	(mult:SI (match_operand:SI 1 "register_operand"  " 0,c,0,0,c")
+	(mult:SI (match_operand:SI 1 "register_operand"  "%0,c,0,0,c")
 		 (match_operand:SI 2 "nonmemory_operand" "cL,cL,I,Cal,Cal")))]
  "TARGET_ARC700_MPY"
   "mpyu%? %0,%1,%2"
-- 
1.9.1

[PATCH 7/7] [ARC] Test against frame_pointer_needed in arc_can_eliminate.

[Claudiu Zissulescu]

arc_can_eliminate is using arc_frmae_pointer_required() which is wrong
as the frame_pointer_needed can be set on different conditions. Fix it
by calling arc_frame_pointer_needed().

gcc/
2017-01-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_can_eliminate): Test against
	arc_frame_pointer_needed.
---
 gcc/config/arc/arc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 0c4c901..aac1952 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -4733,7 +4733,7 @@ arc_final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED,
 static bool
 arc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
 {
-  return to == FRAME_POINTER_REGNUM || !arc_frame_pointer_required ();
+  return ((to == FRAME_POINTER_REGNUM) || !arc_frame_pointer_needed ());
 }
 
 /* Define the offset between two registers, one to be eliminated, and
-- 
1.9.1

[PATCH 0/7] [ARC] Patterns update and fixes

[Claudiu Zissulescu]

From: claziss <claziss@synopsys.com>

Hi Andrew,

Please fing a set of 7 small patches which are upgrating/fixing wrong
patterns.  Please let me know if you need more info.

Cheers,
Claudiu

Claudiu Zissulescu (7):
  [ARC] Make mulsi for A700 pattern commutative.
  [ARC] Avoid use of hard registers before reg-alloc.
  [ARC] Allow r30 to be used by the reg-alloc.
  [ARC] Change predicate movv2hi to avoid scaled addresses.
  [ARC] Update (non)commutative_binary_comparison patterns.
  [ARC] Prevent moving stores to the frame before the stack adjustment.
  [ARC] Test against frame_pointer_needed in arc_can_eliminate.

 gcc/config/arc/arc.c      |  21 ++++-
 gcc/config/arc/arc.h      |   3 +-
 gcc/config/arc/arc.md     | 201 ++++++++++++++++++++++++++++++++--------------
 gcc/config/arc/simdext.md |   2 +-
 4 files changed, 163 insertions(+), 64 deletions(-)

-- 
1.9.1

[PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

[Claudiu Zissulescu]

gcc/
2017-04-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (mulsi3): Avoid use of hard registers before
	reg-alloc when having mul64 or mul32x16 instructions.
	(mulsidi3): Likewise.
	(umulsidi3): Likewise.
	(mulsi32x16): New pattern.
	(mulsi64): Likewise.
	(mulsidi64): Likewise.
	(umulsidi64): Likewise.
	(MUL32x16_REG): Define.
	(mul64_600): Use MUL32x16_REG.
	(mac64_600): Likewise.
	(umul64_600): Likewise.
	(umac64_600): Likewise.
---
 gcc/config/arc/arc.md | 168 +++++++++++++++++++++++++++++++++++---------------
 1 file changed, 119 insertions(+), 49 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index db5867c..c0ad86c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -176,6 +176,7 @@
    (ILINK2_REGNUM 30)
    (RETURN_ADDR_REGNUM 31)
    (MUL64_OUT_REG 58)
+   (MUL32x16_REG 56)
    (ARCV2_ACC 58)
 
    (LP_COUNT 60)
@@ -1940,29 +1941,17 @@
     }
   else if (TARGET_MUL64_SET)
     {
-      emit_insn (gen_mulsi_600 (operands[1], operands[2],
-				gen_mlo (), gen_mhi ()));
-      emit_move_insn (operands[0], gen_mlo ());
-      DONE;
+     rtx tmp = gen_reg_rtx (SImode);
+     emit_insn (gen_mulsi64 (tmp, operands[1], operands[2]));
+     emit_move_insn (operands[0], tmp);
+     DONE;
     }
   else if (TARGET_MULMAC_32BY16_SET)
     {
-      if (immediate_operand (operands[2], SImode)
-	  && INTVAL (operands[2]) >= 0
-	  && INTVAL (operands[2]) <= 65535)
-	{
-	  emit_insn (gen_umul_600 (operands[1], operands[2],
-				     gen_acc2 (), gen_acc1 ()));
-	  emit_move_insn (operands[0], gen_acc2 ());
-	  DONE;
-	}
-      operands[2] = force_reg (SImode, operands[2]);
-      emit_insn (gen_umul_600 (operands[1], operands[2],
-			       gen_acc2 (), gen_acc1 ()));
-      emit_insn (gen_mac_600 (operands[1], operands[2],
-			       gen_acc2 (), gen_acc1 ()));
-      emit_move_insn (operands[0], gen_acc2 ());
-      DONE;
+     rtx tmp = gen_reg_rtx (SImode);
+     emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2]));
+     emit_move_insn (operands[0], tmp);
+     DONE;
     }
   else
     {
@@ -1974,6 +1963,35 @@
     }
 })
 
+(define_insn_and_split "mulsi32x16"
+ [(set (match_operand:SI 0 "register_operand"            "=w")
+	(mult:SI (match_operand:SI 1 "register_operand"  "%c")
+		 (match_operand:SI 2 "nonmemory_operand" "ci")))
+  (clobber (reg:DI MUL32x16_REG))]
+ "TARGET_MULMAC_32BY16_SET"
+ "#"
+ "TARGET_MULMAC_32BY16_SET && reload_completed"
+ [(const_int 0)]
+ {
+  if (immediate_operand (operands[2], SImode)
+    && INTVAL (operands[2]) >= 0
+    && INTVAL (operands[2]) <= 65535)
+     {
+      emit_insn (gen_umul_600 (operands[1], operands[2],
+				       gen_acc2 (), gen_acc1 ()));
+      emit_move_insn (operands[0], gen_acc2 ());
+      DONE;
+     }
+   emit_insn (gen_umul_600 (operands[1], operands[2],
+				   gen_acc2 (), gen_acc1 ()));
+   emit_insn (gen_mac_600 (operands[1], operands[2],
+				   gen_acc2 (), gen_acc1 ()));
+   emit_move_insn (operands[0], gen_acc2 ());
+   DONE;
+  }
+ [(set_attr "type" "multi")
+  (set_attr "length" "8")])
+
 ; mululw conditional execution without a LIMM clobbers an input register;
 ; we'd need a different pattern to describe this.
 ; To make the conditional execution valid for the LIMM alternative, we
@@ -2011,6 +2029,24 @@
    (set_attr "predicable" "no, no, yes")
    (set_attr "cond" "nocond, canuse_limm, canuse")])
 
+(define_insn_and_split "mulsi64"
+ [(set (match_operand:SI 0 "register_operand"            "=w")
+	(mult:SI (match_operand:SI 1 "register_operand"  "%c")
+		 (match_operand:SI 2 "nonmemory_operand" "ci")))
+  (clobber (reg:DI MUL64_OUT_REG))]
+ "TARGET_MUL64_SET"
+ "#"
+ "TARGET_MUL64_SET && reload_completed"
+  [(const_int 0)]
+{
+  emit_insn (gen_mulsi_600 (operands[1], operands[2],
+			gen_mlo (), gen_mhi ()));
+  emit_move_insn (operands[0], gen_mlo ());
+  DONE;
+}
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 (define_insn "mulsi_600"
   [(set (match_operand:SI 2 "mlo_operand" "")
 	(mult:SI (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c")
@@ -2155,8 +2191,7 @@
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 		 (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))))]
   "TARGET_ANY_MPY"
-"
-{
+  {
   if (TARGET_PLUS_MACD)
     {
      if (CONST_INT_P (operands[2]))
@@ -2189,18 +2224,37 @@
     }
   else if (TARGET_MULMAC_32BY16_SET)
     {
-      rtx result_hi = gen_highpart(SImode, operands[0]);
-      rtx result_low = gen_lowpart(SImode, operands[0]);
-
-      emit_insn (gen_mul64_600 (operands[1], operands[2]));
-      emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2]));
-      emit_move_insn (result_low, gen_acc2 ());
+      operands[2] = force_reg (SImode, operands[2]);
+      emit_insn (gen_mulsidi64 (operands[0], operands[1], operands[2]));
       DONE;
     }
-}")
+  operands[2] = force_reg (SImode, operands[2]);
+  })
+
+(define_insn_and_split "mulsidi64"
+  [(set (match_operand:DI 0 "register_operand" "=w")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%c"))
+		 (sign_extend:DI (match_operand:SI 2 "extend_operand" "ci"))))
+   (clobber (reg:DI MUL32x16_REG))]
+  "TARGET_MULMAC_32BY16_SET"
+  "#"
+  "TARGET_MULMAC_32BY16_SET && reload_completed"
+  [(const_int 0)]
+  {
+   rtx result_hi = gen_highpart (SImode, operands[0]);
+   rtx result_low = gen_lowpart (SImode, operands[0]);
+
+   emit_insn (gen_mul64_600 (operands[1], operands[2]));
+   emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2]));
+   emit_move_insn (result_low, gen_acc2 ());
+   DONE;
+  }
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 
 (define_insn "mul64_600"
-  [(set (reg:DI 56)
+  [(set (reg:DI MUL32x16_REG)
 	(mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand"
 				  "c,c,c"))
 		 (zero_extract:DI (match_operand:SI 1 "nonmemory_operand"
@@ -2218,14 +2272,14 @@
 
 ;; ??? check if this is canonical rtl
 (define_insn "mac64_600"
-  [(set (reg:DI 56)
+  [(set (reg:DI MUL32x16_REG)
 	(plus:DI
 	  (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "c,c,c"))
 		   (ashift:DI
 		     (sign_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal")
 				      (const_int 16) (const_int 16))
 		     (const_int 16)))
-	  (reg:DI 56)))
+	  (reg:DI MUL32x16_REG)))
    (set (match_operand:SI 0 "register_operand" "=w,w,w")
 	(zero_extract:SI
 	  (plus:DI
@@ -2234,7 +2288,7 @@
 		       (sign_extract:DI (match_dup 2)
 					(const_int 16) (const_int 16))
 			  (const_int 16)))
-	    (reg:DI 56))
+	    (reg:DI MUL32x16_REG))
 	  (const_int 32) (const_int 32)))]
   "TARGET_MULMAC_32BY16_SET"
   "machlw%? %0, %1, %2"
@@ -2428,20 +2482,14 @@
     }
   else if (TARGET_MUL64_SET)
     {
-      emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
+     operands[2] = force_reg (SImode, operands[2]);
+     emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
       DONE;
     }
   else if (TARGET_MULMAC_32BY16_SET)
     {
-      rtx result_hi = gen_reg_rtx (SImode);
-      rtx result_low = gen_reg_rtx (SImode);
-
-      result_hi = gen_highpart(SImode , operands[0]);
-      result_low = gen_lowpart(SImode , operands[0]);
-
-      emit_insn (gen_umul64_600 (operands[1], operands[2]));
-      emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2]));
-      emit_move_insn (result_low, gen_acc2 ());
+     operands[2] = force_reg (SImode, operands[2]);
+     emit_insn (gen_umulsidi64 (operands[0], operands[1], operands[2]));
       DONE;
     }
   else
@@ -2454,8 +2502,32 @@
     }
 })
 
+(define_insn_and_split "umulsidi64"
+  [(set (match_operand:DI 0 "register_operand" "=w")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c"))
+		 (zero_extend:DI (match_operand:SI 2 "extend_operand" "ci"))))
+   (clobber (reg:DI MUL32x16_REG))]
+  "TARGET_MULMAC_32BY16_SET"
+  "#"
+  "TARGET_MULMAC_32BY16_SET && reload_completed"
+  [(const_int 0)]
+  {
+   rtx result_hi;
+   rtx result_low;
+
+   result_hi = gen_highpart (SImode, operands[0]);
+   result_low = gen_lowpart (SImode, operands[0]);
+
+   emit_insn (gen_umul64_600 (operands[1], operands[2]));
+   emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2]));
+   emit_move_insn (result_low, gen_acc2 ());
+   DONE;
+   }
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 (define_insn "umul64_600"
-  [(set (reg:DI 56)
+  [(set (reg:DI MUL32x16_REG)
 	(mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand"
 				  "c,c,c"))
 		 (zero_extract:DI (match_operand:SI 1 "nonmemory_operand"
@@ -2472,14 +2544,14 @@
 
 
 (define_insn "umac64_600"
-  [(set (reg:DI 56)
+  [(set (reg:DI MUL32x16_REG)
 	(plus:DI
 	  (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "c,c,c"))
 		   (ashift:DI
 		     (zero_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal")
 				      (const_int 16) (const_int 16))
 		     (const_int 16)))
-	  (reg:DI 56)))
+	  (reg:DI MUL32x16_REG)))
    (set (match_operand:SI 0 "register_operand" "=w,w,w")
 	(zero_extract:SI
 	  (plus:DI
@@ -2488,7 +2560,7 @@
 		       (zero_extract:DI (match_dup 2)
 					(const_int 16) (const_int 16))
 			  (const_int 16)))
-	    (reg:DI 56))
+	    (reg:DI MUL32x16_REG))
 	  (const_int 32) (const_int 32)))]
   "TARGET_MULMAC_32BY16_SET"
   "machulw%? %0, %1, %2"
@@ -2497,8 +2569,6 @@
    (set_attr "predicable" "no,no,yes")
    (set_attr "cond" "nocond, canuse_limm, canuse")])
 
-
-
 ;; DI <- DI(unsigned SI) * DI(unsigned SI)
 (define_insn_and_split "umulsidi3_700"
   [(set (match_operand:DI 0 "dest_reg_operand" "=&r")
-- 
1.9.1

[PATCH 3/7] [ARC] Allow r30 to be used by the reg-alloc.

[Claudiu Zissulescu]

gcc/
2016-12-12  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_conditional_register_usage): Allow r30 to
	be used by the reg-alloc.
---
 gcc/config/arc/arc.c | 9 ++++++++-
 gcc/config/arc/arc.h | 3 ++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index fd4bf2c..ff86f6c 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1551,7 +1551,14 @@ arc_conditional_register_usage (void)
       /* For ARCv2 the core register set is changed.  */
       strcpy (rname29, "ilink");
       strcpy (rname30, "r30");
-      fixed_regs[30] = call_used_regs[30] = 1;
+      call_used_regs[30] = 1;
+      fixed_regs[30] = 0;
+
+      arc_regno_reg_class[30] = WRITABLE_CORE_REGS;
+      SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], 30);
+      SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], 30);
+      SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], 30);
+      SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], 30);
    }
 
   if (TARGET_MUL64_SET)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 0a4c745..fbc1195 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -641,7 +641,8 @@ extern enum reg_class arc_regno_reg_class[];
   ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63)	\
    || ((unsigned) reg_renumber[REGNO] < 29)				\
    || ((unsigned) (REGNO) == (unsigned) arc_tp_regno)			\
-   || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)))
+   || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59))		\
+   || ((REGNO) == 30 && fixed_regs[REGNO] == 0))
 
 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
 
-- 
1.9.1

Re: [PATCH 1/7] [ARC] Make mulsi for A700 pattern commutative.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:30:56 +0200]:

> gcc/
> 2016-11-10  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.md (mulsi3_700): Make it commutative.

Looks good thanks,

Andrew


> ---
>  gcc/config/arc/arc.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 71d076c..db5867c 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2127,7 +2127,7 @@
>  ; like MPY or MPYU.
>  (define_insn "mulsi3_700"
>   [(set (match_operand:SI 0 "mpy_dest_reg_operand"        "=Rcr,r,r,Rcr,r")
> -	(mult:SI (match_operand:SI 1 "register_operand"  " 0,c,0,0,c")
> +	(mult:SI (match_operand:SI 1 "register_operand"  "%0,c,0,0,c")
>  		 (match_operand:SI 2 "nonmemory_operand" "cL,cL,I,Cal,Cal")))]
>   "TARGET_ARC700_MPY"
>    "mpyu%? %0,%1,%2"
> -- 
> 1.9.1
> 

Re: [PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:30:57 +0200]:

> gcc/
> 2017-04-10  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.md (mulsi3): Avoid use of hard registers before
> 	reg-alloc when having mul64 or mul32x16 instructions.
> 	(mulsidi3): Likewise.
> 	(umulsidi3): Likewise.
> 	(mulsi32x16): New pattern.
> 	(mulsi64): Likewise.
> 	(mulsidi64): Likewise.
> 	(umulsidi64): Likewise.
> 	(MUL32x16_REG): Define.
> 	(mul64_600): Use MUL32x16_REG.
> 	(mac64_600): Likewise.
> 	(umul64_600): Likewise.
> 	(umac64_600): Likewise.


Looks good, thanks,

Andrew

> ---
>  gcc/config/arc/arc.md | 168 +++++++++++++++++++++++++++++++++++---------------
>  1 file changed, 119 insertions(+), 49 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index db5867c..c0ad86c 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -176,6 +176,7 @@
>     (ILINK2_REGNUM 30)
>     (RETURN_ADDR_REGNUM 31)
>     (MUL64_OUT_REG 58)
> +   (MUL32x16_REG 56)
>     (ARCV2_ACC 58)
>  
>     (LP_COUNT 60)
> @@ -1940,29 +1941,17 @@
>      }
>    else if (TARGET_MUL64_SET)
>      {
> -      emit_insn (gen_mulsi_600 (operands[1], operands[2],
> -				gen_mlo (), gen_mhi ()));
> -      emit_move_insn (operands[0], gen_mlo ());
> -      DONE;
> +     rtx tmp = gen_reg_rtx (SImode);
> +     emit_insn (gen_mulsi64 (tmp, operands[1], operands[2]));
> +     emit_move_insn (operands[0], tmp);
> +     DONE;
>      }
>    else if (TARGET_MULMAC_32BY16_SET)
>      {
> -      if (immediate_operand (operands[2], SImode)
> -	  && INTVAL (operands[2]) >= 0
> -	  && INTVAL (operands[2]) <= 65535)
> -	{
> -	  emit_insn (gen_umul_600 (operands[1], operands[2],
> -				     gen_acc2 (), gen_acc1 ()));
> -	  emit_move_insn (operands[0], gen_acc2 ());
> -	  DONE;
> -	}
> -      operands[2] = force_reg (SImode, operands[2]);
> -      emit_insn (gen_umul_600 (operands[1], operands[2],
> -			       gen_acc2 (), gen_acc1 ()));
> -      emit_insn (gen_mac_600 (operands[1], operands[2],
> -			       gen_acc2 (), gen_acc1 ()));
> -      emit_move_insn (operands[0], gen_acc2 ());
> -      DONE;
> +     rtx tmp = gen_reg_rtx (SImode);
> +     emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2]));
> +     emit_move_insn (operands[0], tmp);
> +     DONE;
>      }
>    else
>      {
> @@ -1974,6 +1963,35 @@
>      }
>  })
>  
> +(define_insn_and_split "mulsi32x16"
> + [(set (match_operand:SI 0 "register_operand"            "=w")
> +	(mult:SI (match_operand:SI 1 "register_operand"  "%c")
> +		 (match_operand:SI 2 "nonmemory_operand" "ci")))
> +  (clobber (reg:DI MUL32x16_REG))]
> + "TARGET_MULMAC_32BY16_SET"
> + "#"
> + "TARGET_MULMAC_32BY16_SET && reload_completed"
> + [(const_int 0)]
> + {
> +  if (immediate_operand (operands[2], SImode)
> +    && INTVAL (operands[2]) >= 0
> +    && INTVAL (operands[2]) <= 65535)
> +     {
> +      emit_insn (gen_umul_600 (operands[1], operands[2],
> +				       gen_acc2 (), gen_acc1 ()));
> +      emit_move_insn (operands[0], gen_acc2 ());
> +      DONE;
> +     }
> +   emit_insn (gen_umul_600 (operands[1], operands[2],
> +				   gen_acc2 (), gen_acc1 ()));
> +   emit_insn (gen_mac_600 (operands[1], operands[2],
> +				   gen_acc2 (), gen_acc1 ()));
> +   emit_move_insn (operands[0], gen_acc2 ());
> +   DONE;
> +  }
> + [(set_attr "type" "multi")
> +  (set_attr "length" "8")])
> +
>  ; mululw conditional execution without a LIMM clobbers an input register;
>  ; we'd need a different pattern to describe this.
>  ; To make the conditional execution valid for the LIMM alternative, we
> @@ -2011,6 +2029,24 @@
>     (set_attr "predicable" "no, no, yes")
>     (set_attr "cond" "nocond, canuse_limm, canuse")])
>  
> +(define_insn_and_split "mulsi64"
> + [(set (match_operand:SI 0 "register_operand"            "=w")
> +	(mult:SI (match_operand:SI 1 "register_operand"  "%c")
> +		 (match_operand:SI 2 "nonmemory_operand" "ci")))
> +  (clobber (reg:DI MUL64_OUT_REG))]
> + "TARGET_MUL64_SET"
> + "#"
> + "TARGET_MUL64_SET && reload_completed"
> +  [(const_int 0)]
> +{
> +  emit_insn (gen_mulsi_600 (operands[1], operands[2],
> +			gen_mlo (), gen_mhi ()));
> +  emit_move_insn (operands[0], gen_mlo ());
> +  DONE;
> +}
> +  [(set_attr "type" "multi")
> +   (set_attr "length" "8")])
> +
>  (define_insn "mulsi_600"
>    [(set (match_operand:SI 2 "mlo_operand" "")
>  	(mult:SI (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c")
> @@ -2155,8 +2191,7 @@
>  	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
>  		 (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))))]
>    "TARGET_ANY_MPY"
> -"
> -{
> +  {
>    if (TARGET_PLUS_MACD)
>      {
>       if (CONST_INT_P (operands[2]))
> @@ -2189,18 +2224,37 @@
>      }
>    else if (TARGET_MULMAC_32BY16_SET)
>      {
> -      rtx result_hi = gen_highpart(SImode, operands[0]);
> -      rtx result_low = gen_lowpart(SImode, operands[0]);
> -
> -      emit_insn (gen_mul64_600 (operands[1], operands[2]));
> -      emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2]));
> -      emit_move_insn (result_low, gen_acc2 ());
> +      operands[2] = force_reg (SImode, operands[2]);
> +      emit_insn (gen_mulsidi64 (operands[0], operands[1], operands[2]));
>        DONE;
>      }
> -}")
> +  operands[2] = force_reg (SImode, operands[2]);
> +  })
> +
> +(define_insn_and_split "mulsidi64"
> +  [(set (match_operand:DI 0 "register_operand" "=w")
> +	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%c"))
> +		 (sign_extend:DI (match_operand:SI 2 "extend_operand" "ci"))))
> +   (clobber (reg:DI MUL32x16_REG))]
> +  "TARGET_MULMAC_32BY16_SET"
> +  "#"
> +  "TARGET_MULMAC_32BY16_SET && reload_completed"
> +  [(const_int 0)]
> +  {
> +   rtx result_hi = gen_highpart (SImode, operands[0]);
> +   rtx result_low = gen_lowpart (SImode, operands[0]);
> +
> +   emit_insn (gen_mul64_600 (operands[1], operands[2]));
> +   emit_insn (gen_mac64_600 (result_hi, operands[1], operands[2]));
> +   emit_move_insn (result_low, gen_acc2 ());
> +   DONE;
> +  }
> +  [(set_attr "type" "multi")
> +   (set_attr "length" "8")])
> +
>  
>  (define_insn "mul64_600"
> -  [(set (reg:DI 56)
> +  [(set (reg:DI MUL32x16_REG)
>  	(mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand"
>  				  "c,c,c"))
>  		 (zero_extract:DI (match_operand:SI 1 "nonmemory_operand"
> @@ -2218,14 +2272,14 @@
>  
>  ;; ??? check if this is canonical rtl
>  (define_insn "mac64_600"
> -  [(set (reg:DI 56)
> +  [(set (reg:DI MUL32x16_REG)
>  	(plus:DI
>  	  (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "c,c,c"))
>  		   (ashift:DI
>  		     (sign_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal")
>  				      (const_int 16) (const_int 16))
>  		     (const_int 16)))
> -	  (reg:DI 56)))
> +	  (reg:DI MUL32x16_REG)))
>     (set (match_operand:SI 0 "register_operand" "=w,w,w")
>  	(zero_extract:SI
>  	  (plus:DI
> @@ -2234,7 +2288,7 @@
>  		       (sign_extract:DI (match_dup 2)
>  					(const_int 16) (const_int 16))
>  			  (const_int 16)))
> -	    (reg:DI 56))
> +	    (reg:DI MUL32x16_REG))
>  	  (const_int 32) (const_int 32)))]
>    "TARGET_MULMAC_32BY16_SET"
>    "machlw%? %0, %1, %2"
> @@ -2428,20 +2482,14 @@
>      }
>    else if (TARGET_MUL64_SET)
>      {
> -      emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
> +     operands[2] = force_reg (SImode, operands[2]);
> +     emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
>        DONE;
>      }
>    else if (TARGET_MULMAC_32BY16_SET)
>      {
> -      rtx result_hi = gen_reg_rtx (SImode);
> -      rtx result_low = gen_reg_rtx (SImode);
> -
> -      result_hi = gen_highpart(SImode , operands[0]);
> -      result_low = gen_lowpart(SImode , operands[0]);
> -
> -      emit_insn (gen_umul64_600 (operands[1], operands[2]));
> -      emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2]));
> -      emit_move_insn (result_low, gen_acc2 ());
> +     operands[2] = force_reg (SImode, operands[2]);
> +     emit_insn (gen_umulsidi64 (operands[0], operands[1], operands[2]));
>        DONE;
>      }
>    else
> @@ -2454,8 +2502,32 @@
>      }
>  })
>  
> +(define_insn_and_split "umulsidi64"
> +  [(set (match_operand:DI 0 "register_operand" "=w")
> +	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c"))
> +		 (zero_extend:DI (match_operand:SI 2 "extend_operand" "ci"))))
> +   (clobber (reg:DI MUL32x16_REG))]
> +  "TARGET_MULMAC_32BY16_SET"
> +  "#"
> +  "TARGET_MULMAC_32BY16_SET && reload_completed"
> +  [(const_int 0)]
> +  {
> +   rtx result_hi;
> +   rtx result_low;
> +
> +   result_hi = gen_highpart (SImode, operands[0]);
> +   result_low = gen_lowpart (SImode, operands[0]);
> +
> +   emit_insn (gen_umul64_600 (operands[1], operands[2]));
> +   emit_insn (gen_umac64_600 (result_hi, operands[1], operands[2]));
> +   emit_move_insn (result_low, gen_acc2 ());
> +   DONE;
> +   }
> +  [(set_attr "type" "multi")
> +   (set_attr "length" "8")])
> +
>  (define_insn "umul64_600"
> -  [(set (reg:DI 56)
> +  [(set (reg:DI MUL32x16_REG)
>  	(mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand"
>  				  "c,c,c"))
>  		 (zero_extract:DI (match_operand:SI 1 "nonmemory_operand"
> @@ -2472,14 +2544,14 @@
>  
>  
>  (define_insn "umac64_600"
> -  [(set (reg:DI 56)
> +  [(set (reg:DI MUL32x16_REG)
>  	(plus:DI
>  	  (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "c,c,c"))
>  		   (ashift:DI
>  		     (zero_extract:DI (match_operand:SI 2 "nonmemory_operand" "c,L,Cal")
>  				      (const_int 16) (const_int 16))
>  		     (const_int 16)))
> -	  (reg:DI 56)))
> +	  (reg:DI MUL32x16_REG)))
>     (set (match_operand:SI 0 "register_operand" "=w,w,w")
>  	(zero_extract:SI
>  	  (plus:DI
> @@ -2488,7 +2560,7 @@
>  		       (zero_extract:DI (match_dup 2)
>  					(const_int 16) (const_int 16))
>  			  (const_int 16)))
> -	    (reg:DI 56))
> +	    (reg:DI MUL32x16_REG))
>  	  (const_int 32) (const_int 32)))]
>    "TARGET_MULMAC_32BY16_SET"
>    "machulw%? %0, %1, %2"
> @@ -2497,8 +2569,6 @@
>     (set_attr "predicable" "no,no,yes")
>     (set_attr "cond" "nocond, canuse_limm, canuse")])
>  
> -
> -
>  ;; DI <- DI(unsigned SI) * DI(unsigned SI)
>  (define_insn_and_split "umulsidi3_700"
>    [(set (match_operand:DI 0 "dest_reg_operand" "=&r")
> -- 
> 1.9.1
> 

Re: [PATCH 3/7] [ARC] Allow r30 to be used by the reg-alloc.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:30:58 +0200]:

> gcc/
> 2016-12-12  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_conditional_register_usage): Allow r30 to
> 	be used by the reg-alloc.

Looks good, thanks,

Andrew


> ---
>  gcc/config/arc/arc.c | 9 ++++++++-
>  gcc/config/arc/arc.h | 3 ++-
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index fd4bf2c..ff86f6c 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -1551,7 +1551,14 @@ arc_conditional_register_usage (void)
>        /* For ARCv2 the core register set is changed.  */
>        strcpy (rname29, "ilink");
>        strcpy (rname30, "r30");
> -      fixed_regs[30] = call_used_regs[30] = 1;
> +      call_used_regs[30] = 1;
> +      fixed_regs[30] = 0;
> +
> +      arc_regno_reg_class[30] = WRITABLE_CORE_REGS;
> +      SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], 30);
> +      SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], 30);
> +      SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], 30);
> +      SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], 30);
>     }
>  
>    if (TARGET_MUL64_SET)
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index 0a4c745..fbc1195 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -641,7 +641,8 @@ extern enum reg_class arc_regno_reg_class[];
>    ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63)	\
>     || ((unsigned) reg_renumber[REGNO] < 29)				\
>     || ((unsigned) (REGNO) == (unsigned) arc_tp_regno)			\
> -   || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)))
> +   || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59))		\
> +   || ((REGNO) == 30 && fixed_regs[REGNO] == 0))
>  
>  #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
>  
> -- 
> 1.9.1
> 

Re: [PATCH 4/7] [ARC] Change predicate movv2hi to avoid scaled addresses.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:30:59 +0200]:

> From: Claudiu Zissulescu <claziss@gmail.com>
> 
> 2016-12-17  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/simdext.md (movv2hi_insn): Change predicate to avoid
> 	scaled addresses.

Seems reasonable.

Thanks,
Andrew


> ---
>  gcc/config/arc/simdext.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
> index 5253033..6c102d3 100644
> --- a/gcc/config/arc/simdext.md
> +++ b/gcc/config/arc/simdext.md
> @@ -1356,7 +1356,7 @@
>     }")
>  
>  (define_insn_and_split "*movv2hi_insn"
> -  [(set (match_operand:V2HI 0 "nonimmediate_operand" "=r,r,r,m")
> +  [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m")
>  	(match_operand:V2HI 1 "general_operand"       "i,r,m,r"))]
>    "(register_operand (operands[0], V2HImode)
>      || register_operand (operands[1], V2HImode))"
> -- 
> 1.9.1
> 

Re: [PATCH 5/7] [ARC] Update (non)commutative_binary_comparison patterns.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:31:00 +0200]:

> gcc/
> 2016-12-20  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.md (commutative_binary_comparison): Remove 'I'
> 	constraint. It is not valid for the pattern.
> 	(noncommutative_binary_comparison): Likewise.

Looks good, thanks,
Andrew


> ---
>  gcc/config/arc/arc.md | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index c0ad86c..743a844 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -948,15 +948,15 @@
>    [(set (match_operand:CC_ZN 0 "cc_set_register" "")
>  	(match_operator:CC_ZN 5 "zn_compare_operator"
>  	  [(match_operator:SI 4 "commutative_operator"
> -	     [(match_operand:SI 1 "register_operand" "%c,c,c")
> -	      (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")])
> +	     [(match_operand:SI 1 "register_operand" "%c,c")
> +	      (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
>  	   (const_int 0)]))
> -   (clobber (match_scratch:SI 3 "=X,1,X"))]
> +   (clobber (match_scratch:SI 3 "=X,X"))]
>    ""
>    "%O4.f 0,%1,%2"
>    [(set_attr "type" "compare")
>     (set_attr "cond" "set_zn")
> -   (set_attr "length" "4,4,8")])
> +   (set_attr "length" "4,8")])
>  
>  ; for flag setting 'add' instructions like if (a+b) { ...}
>  ; the combiner needs this pattern
> @@ -1050,15 +1050,15 @@
>    [(set (match_operand:CC_ZN 0 "cc_set_register" "")
>  	(match_operator:CC_ZN 5 "zn_compare_operator"
>  	  [(match_operator:SI 4 "noncommutative_operator"
> -	     [(match_operand:SI 1 "register_operand" "c,c,c")
> -	      (match_operand:SI 2 "nonmemory_operand" "cL,I,?Cal")])
> +	     [(match_operand:SI 1 "register_operand" "c,c")
> +	      (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])
>  	   (const_int 0)]))
> -   (clobber (match_scratch:SI 3 "=X,1,X"))]
> +   (clobber (match_scratch:SI 3 "=X,X"))]
>    "TARGET_BARREL_SHIFTER || GET_CODE (operands[4]) == MINUS"
>    "%O4.f 0,%1,%2"
>    [(set_attr "type" "compare")
>     (set_attr "cond" "set_zn")
> -   (set_attr "length" "4,4,8")])
> +   (set_attr "length" "4,8")])
>  
>  (define_expand "bic_f_zn"
>    [(parallel
> -- 
> 1.9.1
> 

Re: [PATCH 7/7] [ARC] Test against frame_pointer_needed in arc_can_eliminate.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:31:02 +0200]:

> arc_can_eliminate is using arc_frmae_pointer_required() which is wrong
> as the frame_pointer_needed can be set on different conditions. Fix it
> by calling arc_frame_pointer_needed().
> 
> gcc/
> 2017-01-09  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_can_eliminate): Test against
> 	arc_frame_pointer_needed.

Looks good,

thanks,
Andrew



> ---
>  gcc/config/arc/arc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 0c4c901..aac1952 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -4733,7 +4733,7 @@ arc_final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED,
>  static bool
>  arc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
>  {
> -  return to == FRAME_POINTER_REGNUM || !arc_frame_pointer_required ();
> +  return ((to == FRAME_POINTER_REGNUM) || !arc_frame_pointer_needed ());
>  }
>  
>  /* Define the offset between two registers, one to be eliminated, and
> -- 
> 1.9.1
> 

Re: [PATCH 6/7] [ARC] Prevent moving stores to the frame before the stack adjustment.

[Andrew Burgess]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-05-19 12:31:01 +0200]:

> From: Claudiu Zissulescu <claziss@gmail.com>
> 
> If the stack pointer is needed, emit a special barrier that will prevent
> the scheduler from moving stores to the frame before the stack adjustment.
> 
> 2017-01-03  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_expand_prologue): Emit a special barrier
> 	to prevent store reordering.
> 	* config/arc/arc.md (UNSPEC_ARC_STKTIE): Define.
> 	(type): Add block type.
> 	(stack_tie): Define special instruction to be used in
> 	expand_prologue.

Given the description the code looks fine.  It would be nice to see
more of a _why_ in the commit message.  I'm guessing this is either
something related to signal handling, or debugging... I don't see why
this would be needed for functional correctness.

Thanks,
Andrew






> ---
>  gcc/config/arc/arc.c  | 10 +++++++++-
>  gcc/config/arc/arc.md | 15 ++++++++++++++-
>  2 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index ff86f6c..0c4c901 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -3030,7 +3030,15 @@ arc_expand_prologue (void)
>    frame_size_to_allocate -= first_offset;
>    /* Allocate the stack frame.  */
>    if (frame_size_to_allocate > 0)
> -    frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
> +    {
> +      frame_stack_add ((HOST_WIDE_INT) 0 - frame_size_to_allocate);
> +      /* If the frame pointer is needed, emit a special barrier that
> +	 will prevent the scheduler from moving stores to the frame
> +	 before the stack adjustment.  */
> +      if (arc_frame_pointer_needed ())
> +	emit_insn (gen_stack_tie (stack_pointer_rtx,
> +				  hard_frame_pointer_rtx));
> +    }
>  
>    /* Setup the gp register, if needed.  */
>    if (crtl->uses_pic_offset_table)
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 743a844..6cd192a 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -135,6 +135,7 @@
>    UNSPEC_ARC_VMAC2HU
>    UNSPEC_ARC_VMPY2H
>    UNSPEC_ARC_VMPY2HU
> +  UNSPEC_ARC_STKTIE
>    ])
>  
>  (define_c_enum "vunspec" [
> @@ -205,7 +206,7 @@
>     simd_vcompare, simd_vpermute, simd_vpack, simd_vpack_with_acc,
>     simd_valign, simd_valign_with_acc, simd_vcontrol,
>     simd_vspecial_3cycle, simd_vspecial_4cycle, simd_dma, mul16_em, div_rem,
> -   fpu"
> +   fpu, block"
>    (cond [(eq_attr "is_sfunc" "yes")
>  	 (cond [(match_test "!TARGET_LONG_CALLS_SET && (!TARGET_MEDIUM_CALLS || GET_CODE (PATTERN (insn)) != COND_EXEC)") (const_string "call")
>  		(match_test "flag_pic") (const_string "sfunc")]
> @@ -6547,6 +6548,18 @@
>    (set_attr "predicable" "yes,no,no,yes,no")
>    (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")])
>  
> +(define_insn "stack_tie"
> +  [(set (mem:BLK (scratch))
> +	(unspec:BLK [(match_operand:SI 0 "register_operand" "rb")
> +		     (match_operand:SI 1 "register_operand" "rb")]
> +		    UNSPEC_ARC_STKTIE))]
> +  ""
> +  ""
> +  [(set_attr "length" "0")
> +   (set_attr "iscompact" "false")
> +   (set_attr "type" "block")]
> +  )
> +
>  ;; include the arc-FPX instructions
>  (include "fpx.md")
>  
> -- 
> 1.9.1
> 

RE: [PATCH 6/7] [ARC] Prevent moving stores to the frame before the stack adjustment.

[Claudiu Zissulescu]

> Given the description the code looks fine.  It would be nice to see
> more of a _why_ in the commit message.  I'm guessing this is either
> something related to signal handling, or debugging... I don't see why
> this would be needed for functional correctness.
> 

The issue is how we generate a function prologue when we use fno-omit-frame-pointer, for example:

[snip]
	mov_s	fp,sp 	; frame pointer is set here
[snip]
	st	r1,[fp,-24]	; frame pointer is used here
[snip]
	sub_s	sp,sp,0x20	; stack pointer adjusted

So we can easily see that any interrupt between the `st` and `sub` instruction will lead to faulty code as the interrupt routine will use a faulty sp register, and, potentially, overwriting the value stored by 'st' instruction. Thus, adding a scheduler barrier will force the compiler to emit the `sub` instruction before the store one.

Thanks,
Claudiu

RE: [PATCH 6/7] [ARC] Prevent moving stores to the frame before the stack adjustment.

[Claudiu Zissulescu]

 
> Given the description the code looks fine.  It would be nice to see
> more of a _why_ in the commit message.  I'm guessing this is either
> something related to signal handling, or debugging... I don't see why
> this would be needed for functional correctness.

Committed with additional comments.

Thank you, Claudiu

RE: [PATCH 7/7] [ARC] Test against frame_pointer_needed in arc_can_eliminate.

[Claudiu Zissulescu]

 
> Looks good,
> 

Committed, thank you,
Claudiu

RE: [PATCH 5/7] [ARC] Update (non)commutative_binary_comparison patterns.

[Claudiu Zissulescu]

> Looks good, thanks,
> Andrew

Committed, thank you,
Claudiu

RE: [PATCH 4/7] [ARC] Change predicate movv2hi to avoid scaled addresses.

[Claudiu Zissulescu]

> Seems reasonable.
> 

Committed, thank you,
Claudiu

RE: [PATCH 3/7] [ARC] Allow r30 to be used by the reg-alloc.

[Claudiu Zissulescu]

> Looks good, thanks,
> 
Committed, thank you,
Claudiu

RE: [PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

[Claudiu Zissulescu]

> Looks good, thanks,

Committed, thank you,
Claudiu

RE: [PATCH 1/7] [ARC] Make mulsi for A700 pattern commutative.

[Claudiu Zissulescu]

> Looks good thanks,

Committed, thank you,
Claudiu