From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
To: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: [PATCH 1/5] xtensa: Document new -mextra-l32r-costs= Xtensa-specific option
Date: Tue, 14 Jun 2022 12:34:48 +0900 [thread overview]
Message-ID: <09db7f8f-5619-ee00-d1f5-1806d01fa068@yahoo.co.jp> (raw)
gcc/ChangeLog:
* doc/invoke.texi: Document -mextra-l32r-costs= option.
---
gcc/doc/invoke.texi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b6c0305f198..2a3c638de40 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1473,7 +1473,8 @@ See RS/6000 and PowerPC Options.
-mauto-litpools -mno-auto-litpools @gol
-mtarget-align -mno-target-align @gol
-mlongcalls -mno-longcalls @gol
--mabi=@var{abi-type}}
+-mabi=@var{abi-type} @gol
+-mextra-l32r-costs=@var{cycles}}
@emph{zSeries Options}
See S/390 and zSeries Options.
@@ -33526,6 +33527,14 @@ by 8 registers on entry so that its arguments are found in registers
pointer. Register window is rotated 8 registers back upon return.
When this version of the ABI is enabled the C preprocessor symbol
@code{__XTENSA_WINDOWED_ABI__} is defined.
+
+@item -mextra-l32r-costs=@var{n}
+@opindex mextra-l32r-costs
+Specify an extra cost of instruction RAM/ROM access for @code{L32R}
+instructions, in clock cycles. This affects, when optimizing for speed,
+whether loading a constant from literal pool using @code{L32R} or
+synthesizing the constant from a small one with a couple of arithmetic
+instructions. The default value is 0.
@end table
@node zSeries Options
--
2.20.1
next reply other threads:[~2022-06-14 3:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-14 3:34 Takayuki 'January June' Suwa [this message]
2022-06-16 0:03 ` Max Filippov
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