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From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: gcc-patches <gcc-patches@gcc.gnu.org>
Cc: richard.sandiford <richard.sandiford@arm.com>,
	 prathamesh.kulkarni <prathamesh.kulkarni@linaro.org>
Subject: PR111754
Date: Tue, 28 Nov 2023 15:56:47 +0800	[thread overview]
Message-ID: <0E364CF57C9D73AC+202311281556465482658@rivai.ai> (raw)

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Hi, there is a regression in RISC-V caused by this patch:

FAIL: gcc.dg/vect/pr111754.c -flto -ffat-lto-objects  scan-tree-dump optimized "return { 0.0, 9.0e\\+0, 0.0, 0.0 }"
FAIL: gcc.dg/vect/pr111754.c scan-tree-dump optimized "return { 0.0, 9.0e\\+0, 0.0, 0.0 }"

I have checked the dump is :
F foo (F a, F b)
{
  <bb 2> [local count: 1073741824]:
  <retval> = { 0.0, 9.0e+0, 0.0, 0.0 };
  return <retval>;

}

The dump IR seems reasonable to me.
I wonder whether we should walk around in RISC-V backend to generate the same IR as ARM SVE ?
Or we should adjust the test ?

Thanks.


juzhe.zhong@rivai.ai

             reply	other threads:[~2023-11-28  7:56 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-28  7:56 juzhe.zhong [this message]
2023-11-28  8:43 ` PR111754 Jakub Jelinek
2023-11-28  8:57   ` [PATCH] testsuite: Fix up pr111754.c test Jakub Jelinek
2023-11-28  9:12     ` Richard Biener
  -- strict thread matches above, loose matches on Subject: below --
2023-10-20 17:25 PR111754 Prathamesh Kulkarni
2023-10-24 21:28 ` PR111754 Richard Sandiford
2023-10-25  8:42   ` PR111754 Richard Sandiford
2023-10-25 10:59   ` PR111754 Prathamesh Kulkarni
2023-10-25 22:38     ` PR111754 Richard Sandiford
2023-10-26  4:13       ` PR111754 Prathamesh Kulkarni
2023-11-08 16:27         ` PR111754 Prathamesh Kulkarni
2023-11-15 15:14           ` PR111754 Prathamesh Kulkarni
2023-11-23 11:40             ` PR111754 Prathamesh Kulkarni
2023-11-23 21:43           ` PR111754 Richard Sandiford
2023-11-27 15:13             ` PR111754 Prathamesh Kulkarni
2023-11-27 16:49               ` PR111754 Richard Sandiford

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