* RE: [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x.
@ 2023-10-15 8:14 Roger Sayle
2023-10-16 11:48 ` Claudiu Zissulescu Ianculescu
2023-10-16 13:14 ` [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src " Jeff Law
0 siblings, 2 replies; 5+ messages in thread
From: Roger Sayle @ 2023-10-15 8:14 UTC (permalink / raw)
To: gcc-patches; +Cc: 'Claudiu Zissulescu'
[-- Attachment #1.1: Type: text/plain, Size: 1485 bytes --]
I've done it again. ENOPATCH.
From: Roger Sayle <roger@nextmovesoftware.com>
Sent: 15 October 2023 09:13
To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
Cc: 'Claudiu Zissulescu' <claziss@gmail.com>
Subject: [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement
1<<x.
This patch adds a pre-reload splitter to arc.md, to use the bset (set
specific bit instruction) to implement 1<<x (i.e. left shifts of one)
on ARC processors that don't have a barrel shifter.
Currently,
int foo(int x) {
return 1 << x;
}
when compiled with -O2 -mcpu=em is compiled as a loop:
foo: mov_s r2,1 ;3
and.f lp_count,r0, 0x1f
lpnz 2f
add r2,r2,r2
nop
2: # end single insn loop
j_s.d [blink]
mov_s r0,r2 ;4
with this patch we instead generate a single instruction:
foo: bset r0,0,r0
j_s [blink]
Finger-crossed this passes Claudiu's nightly testing. This patch
has been minimally tested by building a cross-compiler cc1 to
arc-linux hosted on x86_64-pc-linux-gnu with no additional failures
seen with make -k check. Ok for mainline? Thanks in advance.
2023-10-15 Roger Sayle <roger@nextmovesoftware.com
<mailto:roger@nextmovesoftware.com> >
gcc/ChangeLog
* config/arc/arc.md (*ashlsi3_1): New pre-reload splitter to
use bset dst,0,src to implement 1<<x on !TARGET_BARREL_SHIFTER.
Cheers,
Roger
--
[-- Attachment #2: patchar2.txt --]
[-- Type: text/plain, Size: 910 bytes --]
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a936a8b..22af0bf 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -3421,6 +3421,22 @@ archs4x, archs4xd"
(set_attr "predicable" "no,no,yes,no,no")
(set_attr "cond" "nocond,canuse,canuse,nocond,nocond")])
+;; Split asl dst,1,src into bset dst,0,src.
+(define_insn_and_split "*ashlsi3_1"
+ [(set (match_operand:SI 0 "dest_reg_operand")
+ (ashift:SI (const_int 1)
+ (match_operand:SI 1 "nonmemory_operand")))]
+ "!TARGET_BARREL_SHIFTER
+ && arc_pre_reload_split ()"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (ior:SI (ashift:SI (const_int 1) (match_dup 1))
+ (const_int 0)))]
+ ""
+ [(set_attr "type" "shift")
+ (set_attr "length" "8")])
+
(define_insn_and_split "*ashlsi3_nobs"
[(set (match_operand:SI 0 "dest_reg_operand")
(ashift:SI (match_operand:SI 1 "register_operand")
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x.
2023-10-15 8:14 [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x Roger Sayle
@ 2023-10-16 11:48 ` Claudiu Zissulescu Ianculescu
2023-10-16 13:14 ` [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src " Jeff Law
1 sibling, 0 replies; 5+ messages in thread
From: Claudiu Zissulescu Ianculescu @ 2023-10-16 11:48 UTC (permalink / raw)
To: Roger Sayle; +Cc: gcc-patches
Hi Roger,
Indeed, I was missing the patch file.
Approved.
Thank you for your contribution,
Claudiu
On Sun, Oct 15, 2023 at 11:14 AM Roger Sayle <roger@nextmovesoftware.com> wrote:
>
> I’ve done it again. ENOPATCH.
>
>
>
> From: Roger Sayle <roger@nextmovesoftware.com>
> Sent: 15 October 2023 09:13
> To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
> Cc: 'Claudiu Zissulescu' <claziss@gmail.com>
> Subject: [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x.
>
>
>
>
>
> This patch adds a pre-reload splitter to arc.md, to use the bset (set
>
> specific bit instruction) to implement 1<<x (i.e. left shifts of one)
>
> on ARC processors that don't have a barrel shifter.
>
>
>
> Currently,
>
>
>
> int foo(int x) {
>
> return 1 << x;
>
> }
>
>
>
> when compiled with -O2 -mcpu=em is compiled as a loop:
>
>
>
> foo: mov_s r2,1 ;3
>
> and.f lp_count,r0, 0x1f
>
> lpnz 2f
>
> add r2,r2,r2
>
> nop
>
> 2: # end single insn loop
>
> j_s.d [blink]
>
> mov_s r0,r2 ;4
>
>
>
> with this patch we instead generate a single instruction:
>
>
>
> foo: bset r0,0,r0
>
> j_s [blink]
>
>
>
>
>
> Finger-crossed this passes Claudiu's nightly testing. This patch
>
> has been minimally tested by building a cross-compiler cc1 to
>
> arc-linux hosted on x86_64-pc-linux-gnu with no additional failures
>
> seen with make -k check. Ok for mainline? Thanks in advance.
>
>
>
>
>
> 2023-10-15 Roger Sayle <roger@nextmovesoftware.com>
>
>
>
> gcc/ChangeLog
>
> * config/arc/arc.md (*ashlsi3_1): New pre-reload splitter to
>
> use bset dst,0,src to implement 1<<x on !TARGET_BARREL_SHIFTER.
>
>
>
>
>
> Cheers,
>
> Roger
>
> --
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src to implement 1<<x.
2023-10-15 8:14 [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x Roger Sayle
2023-10-16 11:48 ` Claudiu Zissulescu Ianculescu
@ 2023-10-16 13:14 ` Jeff Law
1 sibling, 0 replies; 5+ messages in thread
From: Jeff Law @ 2023-10-16 13:14 UTC (permalink / raw)
To: Roger Sayle, gcc-patches; +Cc: 'Claudiu Zissulescu'
On 10/15/23 02:14, Roger Sayle wrote:
> I’ve done it again. ENOPATCH.
>
> *From:*Roger Sayle <roger@nextmovesoftware.com>
> *Sent:* 15 October 2023 09:13
> *To:* 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
> *Cc:* 'Claudiu Zissulescu' <claziss@gmail.com>
> *Subject:* [ARC PATCH] Split asl dst,1,src into bset dst,0,src to
> implement 1<<x.
>
> This patch adds a pre-reload splitter to arc.md, to use the bset (set
>
> specific bit instruction) to implement 1<<x (i.e. left shifts of one)
>
> on ARC processors that don't have a barrel shifter.
>
> Currently,
>
> int foo(int x) {
>
> return 1 << x;
>
> }
The same basic idea works on the H8, though it's got restrictions that
make it not actually useful in practice.
In particular the H8's bset instruction only looks at the bottom 3 bits
of the count. So unless there's a suitable masking of the count or the
destination register is QImode, then it's not useful ;(
That's too bad, avoiding the shift loop for this kind of source
construct would definitely be a win.
jeff
^ permalink raw reply [flat|nested] 5+ messages in thread
* [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x.
@ 2023-10-15 8:12 Roger Sayle
2023-10-16 17:25 ` [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src " Jeff Law
0 siblings, 1 reply; 5+ messages in thread
From: Roger Sayle @ 2023-10-15 8:12 UTC (permalink / raw)
To: gcc-patches; +Cc: 'Claudiu Zissulescu'
[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]
This patch adds a pre-reload splitter to arc.md, to use the bset (set
specific bit instruction) to implement 1<<x (i.e. left shifts of one)
on ARC processors that don't have a barrel shifter.
Currently,
int foo(int x) {
return 1 << x;
}
when compiled with -O2 -mcpu=em is compiled as a loop:
foo: mov_s r2,1 ;3
and.f lp_count,r0, 0x1f
lpnz 2f
add r2,r2,r2
nop
2: # end single insn loop
j_s.d [blink]
mov_s r0,r2 ;4
with this patch we instead generate a single instruction:
foo: bset r0,0,r0
j_s [blink]
Finger-crossed this passes Claudiu's nightly testing. This patch
has been minimally tested by building a cross-compiler cc1 to
arc-linux hosted on x86_64-pc-linux-gnu with no additional failures
seen with make -k check. Ok for mainline? Thanks in advance.
2023-10-15 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/arc/arc.md (*ashlsi3_1): New pre-reload splitter to
use bset dst,0,src to implement 1<<x on !TARGET_BARREL_SHIFTER.
Cheers,
Roger
--
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src to implement 1<<x.
2023-10-15 8:12 [ARC PATCH] Split asl dst,1,src into bset dst,0,src " Roger Sayle
@ 2023-10-16 17:25 ` Jeff Law
0 siblings, 0 replies; 5+ messages in thread
From: Jeff Law @ 2023-10-16 17:25 UTC (permalink / raw)
To: Roger Sayle, gcc-patches; +Cc: 'Claudiu Zissulescu'
On 10/15/23 02:12, Roger Sayle wrote:
> This patch adds a pre-reload splitter to arc.md, to use the bset (set
>
> specific bit instruction) to implement 1<<x (i.e. left shifts of one)
>
> on ARC processors that don't have a barrel shifter.
>
> Currently,
>
> int foo(int x) {
>
> return 1 << x;
>
> }
FYI conceptually this would be helpful on the H8 port as well since it
does a loop. But unfortunately the bset instruction on the H8 masks the
bit position with 0x7, so a straightforward implementation would only
work in QImode which is pretty uninteresting.
While I could probably cobble together something on the H8 for HI/SI by
detecting when there's a suitable mask in the IL, but I doubt that
happens much in practice.
jeff
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-10-16 17:26 UTC | newest]
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2023-10-15 8:14 [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement 1<<x Roger Sayle
2023-10-16 11:48 ` Claudiu Zissulescu Ianculescu
2023-10-16 13:14 ` [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src " Jeff Law
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