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Tue, 09 Jan 2024 09:59:30 -0800 (PST) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id du10-20020a056638604a00b0046e3314cefdsm778166jab.3.2024.01.09.09.59.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jan 2024 09:59:30 -0800 (PST) Message-ID: <0b3ac135-7ccf-4aa7-86ac-970e6b3213fe@gmail.com> Date: Tue, 9 Jan 2024 10:59:28 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension Content-Language: en-US To: Jin Ma , gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, christoph.muellner@vrull.eu, jinma.contrib@gmail.com References: <20231107030415.1105-1-jinma@linux.alibaba.com> <20231117073325.1959-1-jinma@linux.alibaba.com> From: Jeff Law In-Reply-To: <20231117073325.1959-1-jinma@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/17/23 00:33, Jin Ma wrote: > The XTheadInt ISA extension provides acceleration interruption > instructions as defined in T-Head-specific: > * th.ipush > * th.ipop > > Ref: > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (th_int_get_mask): New prototype. > (th_int_get_save_adjustment): Likewise. > (th_int_adjust_cfi_prologue): Likewise. > * config/riscv/riscv.cc (TH_INT_INTERRUPT): New macro. > (riscv_expand_prologue): Add the processing of XTheadInt. > (riscv_expand_epilogue): Likewise. > * config/riscv/riscv.md: New unspec. > * config/riscv/thead.cc (BITSET_P): New macro. > * config/riscv/thead.md (th_int_push): New pattern. > (th_int_pop): New pattern. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadint-push-pop.c: New test. Thanks for the ping earlier today. I've looked at this patch repeatedly over the last few weeks, but never enough to give it a full review. > diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md > index 2babfafb23c..4d6e16c0edc 100644 > --- a/gcc/config/riscv/thead.md > +++ b/gcc/config/riscv/thead.md > +(define_insn "th_int_pop" > + [(unspec_volatile [(const_int 0)] UNSPECV_XTHEADINT_POP) > + (clobber (reg:SI RETURN_ADDR_REGNUM)) > + (clobber (reg:SI T0_REGNUM)) > + (clobber (reg:SI T1_REGNUM)) > + (clobber (reg:SI T2_REGNUM)) > + (clobber (reg:SI A0_REGNUM)) > + (clobber (reg:SI A1_REGNUM)) > + (clobber (reg:SI A2_REGNUM)) > + (clobber (reg:SI A3_REGNUM)) > + (clobber (reg:SI A4_REGNUM)) > + (clobber (reg:SI A5_REGNUM)) > + (clobber (reg:SI A6_REGNUM)) > + (clobber (reg:SI A7_REGNUM)) > + (clobber (reg:SI T3_REGNUM)) > + (clobber (reg:SI T4_REGNUM)) > + (clobber (reg:SI T5_REGNUM)) > + (clobber (reg:SI T6_REGNUM)) > + (return)] > + "TARGET_XTHEADINT && !TARGET_64BIT" > + "th.ipop" > + [(set_attr "type" "ret") > + (set_attr "mode" "SI")]) I probably would have gone with a load type since its the loads that are most likely to interact existing code in the pipeline. But I doubt it really matters in practice. OK for the trunk. Thanks for your patience. jeff