[PATCH 1/2][Aarch64] Improve FP to int conversions

[PATCH 1/2][Aarch64] Improve FP to int conversions

[Michael Collison]

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This patch improves additional cases of FP to integer conversions.

Example 1:

unsigned long
f7 (double x)
{
  return (unsigned) y;
}


At -O2

Trunk generates:

f7:
	fcvtzu	w0, d0
	uxtw	x0, w0
	ret

With the patch we can merge the zero-extend and reduce the sequence to one instruction at -O2

f7:
	fcvtzu	x0, d0
	ret
	
Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk?

2018-05-15  Michael Collison  <michael.collison@arm.com>

	* config/aarch64/aarch64.md:
	(*fix_to_zero_extenddfdi2): New pattern.
	* gcc.target/aarch64/fix_extend1.c: New testcase.

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From 69f5f84710a709ae1db6d09b9326a6c804011057 Mon Sep 17 00:00:00 2001
From: Michael Collison <michael.collison@arm.com>
Date: Fri, 11 May 2018 06:22:49 +0100
Subject: [PATCH 1/2] Patch 1 to improve fp to int conversions


diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 32a0e1f..b37b56e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -5113,6 +5113,16 @@
   [(set_attr "type" "f_cvtf2i")]
 )
 
+(define_insn "*fix_to_zero_extend<mode>di2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	 (unsigned_fix:SI
+	  (match_operand:GPF 1 "register_operand" "w"))))]
+  "TARGET_FLOAT"
+  "fcvtzu\t%w0, %<s>1"
+  [(set_attr "type" "f_cvtf2i")]
+)
+
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
diff --git a/gcc/testsuite/gcc.target/aarch64/fix_extend1.c b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c
new file mode 100644
index 0000000..3a251d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned long
+f7 (double x)
+{
+  return (unsigned) x;
+}
+
+unsigned long
+f7_2 (float x)
+{
+  return (unsigned) x;
+}
+
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */
-- 
1.9.1

Re: [PATCH 1/2][Aarch64] Improve FP to int conversions

[Richard Sandiford]

Michael Collison <Michael.Collison@arm.com> writes:
> This patch improves additional cases of FP to integer conversions.
>
> Example 1:
>
> unsigned long
> f7 (double x)
> {
>   return (unsigned) y;
> }
>
>
> At -O2
>
> Trunk generates:
>
> f7:
> 	fcvtzu	w0, d0
> 	uxtw	x0, w0
> 	ret
>
> With the patch we can merge the zero-extend and reduce the sequence to one instruction at -O2
>
> f7:
> 	fcvtzu	x0, d0
> 	ret

Thanks for doing this, patch looks good to me FWIW.  I think the
patch actually uses "fcvtzu w0, d0", which unlike "fcvtzu x0, d0"
preserves the rtl semantics exactly.

> +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, d\[0-9\]+" } } */
> +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */

Just wanted to plug curly-brace quoting, which avoids the extra backslashes:

/* { dg-final { scan-assembler {fcvtzu\tw[0-9]+, d[0-9]+} } } */
/* { dg-final { scan-assembler {fcvtzu\tw[0-9]+, s[0-9]+} } } */

Either's fine though -- don't respin for that. :-)

Richard

Re: [PATCH 1/2][Aarch64] Improve FP to int conversions

[Richard Earnshaw (lists)]

On 18/05/18 21:34, Michael Collison wrote:
> This patch improves additional cases of FP to integer conversions.
> 
> Example 1:
> 
> unsigned long
> f7 (double x)
> {
>   return (unsigned) y;
> }
> 
> 
> At -O2
> 
> Trunk generates:
> 
> f7:
> 	fcvtzu	w0, d0
> 	uxtw	x0, w0
> 	ret
> 
> With the patch we can merge the zero-extend and reduce the sequence to one instruction at -O2
> 
> f7:
> 	fcvtzu	x0, d0
> 	ret
> 	
> Bootstrapped and regression tested on aarch64-linux-gnu. Okay for trunk?
> 
> 2018-05-15  Michael Collison  <michael.collison@arm.com>
> 
> 	* config/aarch64/aarch64.md:
> 	(*fix_to_zero_extenddfdi2): New pattern.
> 	* gcc.target/aarch64/fix_extend1.c: New testcase.
> 

OK, either with, or without, Richard S's testsuite change.

R.
> 
> gnutools-6527-pt1.patch
> 
> 
> From 69f5f84710a709ae1db6d09b9326a6c804011057 Mon Sep 17 00:00:00 2001
> From: Michael Collison <michael.collison@arm.com>
> Date: Fri, 11 May 2018 06:22:49 +0100
> Subject: [PATCH 1/2] Patch 1 to improve fp to int conversions
> 
> 
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 32a0e1f..b37b56e 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -5113,6 +5113,16 @@
>    [(set_attr "type" "f_cvtf2i")]
>  )
>  
> +(define_insn "*fix_to_zero_extend<mode>di2"
> +  [(set (match_operand:DI 0 "register_operand" "=r")
> +	(zero_extend:DI
> +	 (unsigned_fix:SI
> +	  (match_operand:GPF 1 "register_operand" "w"))))]
> +  "TARGET_FLOAT"
> +  "fcvtzu\t%w0, %<s>1"
> +  [(set_attr "type" "f_cvtf2i")]
> +)
> +
>  (define_insn "<optab><fcvt_target><GPF:mode>2"
>    [(set (match_operand:GPF 0 "register_operand" "=w,w")
>          (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
> diff --git a/gcc/testsuite/gcc.target/aarch64/fix_extend1.c b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c
> new file mode 100644
> index 0000000..3a251d0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/fix_extend1.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +unsigned long
> +f7 (double x)
> +{
> +  return (unsigned) x;
> +}
> +
> +unsigned long
> +f7_2 (float x)
> +{
> +  return (unsigned) x;
> +}
> +
> +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, d\[0-9\]+" } } */
> +/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */
>