RE: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions emitted at -O3

[xiezhiheng <xiezhiheng@huawei.com>]

[-- Attachment #1: Type: text/plain, Size: 2612 bytes --]

> -----Original Message-----
> From: Richard Sandiford [mailto:richard.sandiford@arm.com]
> Sent: Friday, August 21, 2020 5:02 PM
> To: xiezhiheng <xiezhiheng@huawei.com>
> Cc: Richard Biener <richard.guenther@gmail.com>; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions
> emitted at -O3

Cut...
 
> Looks like the saturating intrinsics might need a bit more thought.
> Would you mind submitting the patch with just the other parts?
> Those were uncontroversial and it would be a shame to hold them
> up over this.

Okay, I reorganized the existing patch and finished the first half of the intrinsics
except saturating intrinsics and load intrinsics.

Bootstrapped and tested on aarch64 Linux platform.

For load intrinsics, I have one problem when I set FLAG_READ_MEMORY for them,
some test cases like
gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
  #include <arm_neon.h>

  /* { dg-do compile } */
  /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */

  poly8x8x2_t
  f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v)
  {
    poly8x8x2_t res;
    /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
    res = vld2_lane_p8 (p, v, 8);
    /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
    res = vld2_lane_p8 (p, v, -1);
    return res;
  }
would fail in regression.  Because the first statement
  res = vld2_lane_p8 (p, v, 8);
would be eliminated as dead code in gimple phase but the error message is
generated in expand pass.  So I am going to replace the second statement
  res = vld2_lane_p8 (p, v, -1);
with
  res = vld2_lane_p8 (p, res, -1);
or do you have any other suggestions?

And for test case gcc.target/aarch64/arg-type-diagnostics-1.c, I return the result
to prevent the statement
  result = vrsra_n_s32 (arg1, arg2, a);
from being eliminated by treated as dead code.

Thanks,
Xie Zhiheng


diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7a71b4367d4..217344d7d1f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-25  Zhiheng Xie  <xiezhiheng@huawei.com>
+
+	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAGS
+	for intrinsic functions.
+

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b9562e67883..e10bcc9b28a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-25  Zhiheng Xie  <xiezhiheng@huawei.com>
+
+	* gcc.target/aarch64/arg-type-diagnostics-1.c: Return result
+	to prevent statement from being eliminated.
+

[-- Attachment #2: pr94442-v1.patch --]
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From 7769142a0855d38510869262a9e413dc48766086 Mon Sep 17 00:00:00 2001
From: xiezhiheng <xiezhiheng@huawei.com>
Date: Mon, 24 Aug 2020 21:35:51 -0400
Subject: [PATCH] AArch64: Add FLAGS for intrinsic functions [PR94442]

2020-08-25  Zhiheng Xie  <xiezhiheng@huawei.com>

gcc/ChangeLog:

	* config/aarch64/aarch64-simd-builtins.def: Add proper FLAGS
	for intrinsic functions.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/arg-type-diagnostics-1.c: Return result
	to prevent statement from being eliminated.
---
 gcc/config/aarch64/aarch64-simd-builtins.def  | 560 +++++++++---------
 .../aarch64/arg-type-diagnostics-1.c          |   3 +-
 2 files changed, 284 insertions(+), 279 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index e8650121cd6..c37c6d561ba 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -37,19 +37,23 @@
    macro holding the RTL pattern for the intrinsic.  This mapping is:
    0 - CODE_FOR_aarch64_<name><mode>
    1-9 - CODE_FOR_<name><mode><1-9>
-   10 - CODE_FOR_<name><mode>.  */
-
-  BUILTIN_VDC (COMBINE, combine, 0, ALL)
-  VAR1 (COMBINEP, combine, 0, ALL, di)
-  BUILTIN_VB (BINOP, pmul, 0, ALL)
-  BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, ALL)
-  BUILTIN_VHSDF_DF (UNOP, sqrt, 2, ALL)
-  BUILTIN_VD_BHSI (BINOP, addp, 0, ALL)
-  VAR1 (UNOP, addp, 0, ALL, di)
-  BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, ALL)
-  BUILTIN_VDQ_BHSI (UNOP, clz, 2, ALL)
-  BUILTIN_VS (UNOP, ctz, 2, ALL)
-  BUILTIN_VB (UNOP, popcount, 2, ALL)
+   10 - CODE_FOR_<name><mode>.
+
+   Parameter 4 is the 'flag' of the intrinsic.  This is used to
+   help describe the attributes (for example, pure) for the intrinsic
+   function.  */
+
+  BUILTIN_VDC (COMBINE, combine, 0, AUTO_FP)
+  VAR1 (COMBINEP, combine, 0, AUTO_FP, di)
+  BUILTIN_VB (BINOP, pmul, 0, NONE)
+  BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, FP)
+  BUILTIN_VHSDF_DF (UNOP, sqrt, 2, NONE)
+  BUILTIN_VD_BHSI (BINOP, addp, 0, NONE)
+  VAR1 (UNOP, addp, 0, NONE, di)
+  BUILTIN_VDQ_BHSI (UNOP, clrsb, 2, NONE)
+  BUILTIN_VDQ_BHSI (UNOP, clz, 2, NONE)
+  BUILTIN_VS (UNOP, ctz, 2, NONE)
+  BUILTIN_VB (UNOP, popcount, 2, NONE)
 
   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
   BUILTIN_VSDQ_I (BINOP, sqshl, 0, ALL)
@@ -66,94 +70,94 @@
   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0, ALL)
 
   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
-  BUILTIN_VDC (GETREG, get_dregoi, 0, ALL)
-  BUILTIN_VDC (GETREG, get_dregci, 0, ALL)
-  BUILTIN_VDC (GETREG, get_dregxi, 0, ALL)
-  VAR1 (GETREGP, get_dregoi, 0, ALL, di)
-  VAR1 (GETREGP, get_dregci, 0, ALL, di)
-  VAR1 (GETREGP, get_dregxi, 0, ALL, di)
+  BUILTIN_VDC (GETREG, get_dregoi, 0, AUTO_FP)
+  BUILTIN_VDC (GETREG, get_dregci, 0, AUTO_FP)
+  BUILTIN_VDC (GETREG, get_dregxi, 0, AUTO_FP)
+  VAR1 (GETREGP, get_dregoi, 0, AUTO_FP, di)
+  VAR1 (GETREGP, get_dregci, 0, AUTO_FP, di)
+  VAR1 (GETREGP, get_dregxi, 0, AUTO_FP, di)
   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (GETREG, get_qregoi, 0, ALL)
-  BUILTIN_VQ (GETREG, get_qregci, 0, ALL)
-  BUILTIN_VQ (GETREG, get_qregxi, 0, ALL)
-  VAR1 (GETREGP, get_qregoi, 0, ALL, v2di)
-  VAR1 (GETREGP, get_qregci, 0, ALL, v2di)
-  VAR1 (GETREGP, get_qregxi, 0, ALL, v2di)
+  BUILTIN_VQ (GETREG, get_qregoi, 0, AUTO_FP)
+  BUILTIN_VQ (GETREG, get_qregci, 0, AUTO_FP)
+  BUILTIN_VQ (GETREG, get_qregxi, 0, AUTO_FP)
+  VAR1 (GETREGP, get_qregoi, 0, AUTO_FP, v2di)
+  VAR1 (GETREGP, get_qregci, 0, AUTO_FP, v2di)
+  VAR1 (GETREGP, get_qregxi, 0, AUTO_FP, v2di)
   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
-  BUILTIN_VQ (SETREG, set_qregoi, 0, ALL)
-  BUILTIN_VQ (SETREG, set_qregci, 0, ALL)
-  BUILTIN_VQ (SETREG, set_qregxi, 0, ALL)
-  VAR1 (SETREGP, set_qregoi, 0, ALL, v2di)
-  VAR1 (SETREGP, set_qregci, 0, ALL, v2di)
-  VAR1 (SETREGP, set_qregxi, 0, ALL, v2di)
+  BUILTIN_VQ (SETREG, set_qregoi, 0, AUTO_FP)
+  BUILTIN_VQ (SETREG, set_qregci, 0, AUTO_FP)
+  BUILTIN_VQ (SETREG, set_qregxi, 0, AUTO_FP)
+  VAR1 (SETREGP, set_qregoi, 0, AUTO_FP, v2di)
+  VAR1 (SETREGP, set_qregci, 0, AUTO_FP, v2di)
+  VAR1 (SETREGP, set_qregxi, 0, AUTO_FP, v2di)
   /* Implemented by aarch64_ld1x2<VQ:mode>. */
-  BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, ALL)
+  BUILTIN_VQ (LOADSTRUCT, ld1x2, 0, READ_MEMORY)
   /* Implemented by aarch64_ld1x2<VDC:mode>. */
-  BUILTIN_VDC (LOADSTRUCT, ld1x2, 0, ALL)
+  BUILTIN_VDC (LOADSTRUCT, ld1x2, 0, READ_MEMORY)
   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
-  BUILTIN_VDC (LOADSTRUCT, ld2, 0, ALL)
-  BUILTIN_VDC (LOADSTRUCT, ld3, 0, ALL)
-  BUILTIN_VDC (LOADSTRUCT, ld4, 0, ALL)
+  BUILTIN_VDC (LOADSTRUCT, ld2, 0, READ_MEMORY)
+  BUILTIN_VDC (LOADSTRUCT, ld3, 0, READ_MEMORY)
+  BUILTIN_VDC (LOADSTRUCT, ld4, 0, READ_MEMORY)
   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
-  BUILTIN_VQ (LOADSTRUCT, ld2, 0, ALL)
-  BUILTIN_VQ (LOADSTRUCT, ld3, 0, ALL)
-  BUILTIN_VQ (LOADSTRUCT, ld4, 0, ALL)
+  BUILTIN_VQ (LOADSTRUCT, ld2, 0, READ_MEMORY)
+  BUILTIN_VQ (LOADSTRUCT, ld3, 0, READ_MEMORY)
+  BUILTIN_VQ (LOADSTRUCT, ld4, 0, READ_MEMORY)
   /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>.  */
-  BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0, ALL)
-  BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0, ALL)
-  BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0, ALL)
+  BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0, READ_MEMORY)
+  BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0, READ_MEMORY)
+  BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0, READ_MEMORY)
   /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>.  */
-  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0, ALL)
-  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0, ALL)
-  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0, ALL)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0, READ_MEMORY)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0, READ_MEMORY)
+  BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0, READ_MEMORY)
   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
-  BUILTIN_VDC (STORESTRUCT, st2, 0, ALL)
-  BUILTIN_VDC (STORESTRUCT, st3, 0, ALL)
-  BUILTIN_VDC (STORESTRUCT, st4, 0, ALL)
+  BUILTIN_VDC (STORESTRUCT, st2, 0, WRITE_MEMORY)
+  BUILTIN_VDC (STORESTRUCT, st3, 0, WRITE_MEMORY)
+  BUILTIN_VDC (STORESTRUCT, st4, 0, WRITE_MEMORY)
   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
-  BUILTIN_VQ (STORESTRUCT, st2, 0, ALL)
-  BUILTIN_VQ (STORESTRUCT, st3, 0, ALL)
-  BUILTIN_VQ (STORESTRUCT, st4, 0, ALL)
-
-  BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0, ALL)
-  BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0, ALL)
-  BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0, ALL)
-
-  BUILTIN_VQW (BINOP, saddl2, 0, ALL)
-  BUILTIN_VQW (BINOP, uaddl2, 0, ALL)
-  BUILTIN_VQW (BINOP, ssubl2, 0, ALL)
-  BUILTIN_VQW (BINOP, usubl2, 0, ALL)
-  BUILTIN_VQW (BINOP, saddw2, 0, ALL)
-  BUILTIN_VQW (BINOP, uaddw2, 0, ALL)
-  BUILTIN_VQW (BINOP, ssubw2, 0, ALL)
-  BUILTIN_VQW (BINOP, usubw2, 0, ALL)
+  BUILTIN_VQ (STORESTRUCT, st2, 0, WRITE_MEMORY)
+  BUILTIN_VQ (STORESTRUCT, st3, 0, WRITE_MEMORY)
+  BUILTIN_VQ (STORESTRUCT, st4, 0, WRITE_MEMORY)
+
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0, WRITE_MEMORY)
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0, WRITE_MEMORY)
+  BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0, WRITE_MEMORY)
+
+  BUILTIN_VQW (BINOP, saddl2, 0, NONE)
+  BUILTIN_VQW (BINOP, uaddl2, 0, NONE)
+  BUILTIN_VQW (BINOP, ssubl2, 0, NONE)
+  BUILTIN_VQW (BINOP, usubl2, 0, NONE)
+  BUILTIN_VQW (BINOP, saddw2, 0, NONE)
+  BUILTIN_VQW (BINOP, uaddw2, 0, NONE)
+  BUILTIN_VQW (BINOP, ssubw2, 0, NONE)
+  BUILTIN_VQW (BINOP, usubw2, 0, NONE)
   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
-  BUILTIN_VD_BHSI (BINOP, saddl, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, uaddl, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, ssubl, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, usubl, 0, ALL)
+  BUILTIN_VD_BHSI (BINOP, saddl, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, uaddl, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, ssubl, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, usubl, 0, NONE)
   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
-  BUILTIN_VD_BHSI (BINOP, saddw, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, uaddw, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, ssubw, 0, ALL)
-  BUILTIN_VD_BHSI (BINOP, usubw, 0, ALL)
+  BUILTIN_VD_BHSI (BINOP, saddw, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, uaddw, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, ssubw, 0, NONE)
+  BUILTIN_VD_BHSI (BINOP, usubw, 0, NONE)
   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
-  BUILTIN_VDQ_BHSI (BINOP, shadd, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, shsub, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, uhadd, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, uhsub, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, urhadd, 0, ALL)
+  BUILTIN_VDQ_BHSI (BINOP, shadd, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, shsub, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, uhadd, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, uhsub, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, urhadd, 0, NONE)
   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
-  BUILTIN_VQN (BINOP, addhn, 0, ALL)
-  BUILTIN_VQN (BINOP, subhn, 0, ALL)
-  BUILTIN_VQN (BINOP, raddhn, 0, ALL)
-  BUILTIN_VQN (BINOP, rsubhn, 0, ALL)
+  BUILTIN_VQN (BINOP, addhn, 0, NONE)
+  BUILTIN_VQN (BINOP, subhn, 0, NONE)
+  BUILTIN_VQN (BINOP, raddhn, 0, NONE)
+  BUILTIN_VQN (BINOP, rsubhn, 0, NONE)
   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
-  BUILTIN_VQN (TERNOP, addhn2, 0, ALL)
-  BUILTIN_VQN (TERNOP, subhn2, 0, ALL)
-  BUILTIN_VQN (TERNOP, raddhn2, 0, ALL)
-  BUILTIN_VQN (TERNOP, rsubhn2, 0, ALL)
+  BUILTIN_VQN (TERNOP, addhn2, 0, NONE)
+  BUILTIN_VQN (TERNOP, subhn2, 0, NONE)
+  BUILTIN_VQN (TERNOP, raddhn2, 0, NONE)
+  BUILTIN_VQN (TERNOP, rsubhn2, 0, NONE)
 
   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0, ALL)
   /* Implemented by aarch64_<sur>qmovn<mode>.  */
@@ -185,20 +189,20 @@
   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0, ALL)
   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0, ALL)
 
-  BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0, ALL)
-  BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0, ALL)
+  BUILTIN_VD_BHSI (BINOP, intrinsic_vec_smult_lo_, 0, NONE)
+  BUILTIN_VD_BHSI (BINOPU, intrinsic_vec_umult_lo_, 0, NONE)
 
-  BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10, ALL)
-  BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10, ALL)
+  BUILTIN_VQW (BINOP, vec_widen_smult_hi_, 10, NONE)
+  BUILTIN_VQW (BINOPU, vec_widen_umult_hi_, 10, NONE)
 
-  BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, ALL)
-  BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, ALL)
-  BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, ALL)
-  BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, ALL)
-  BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, ALL)
-  BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, ALL)
-  BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, ALL)
-  BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, ALL)
+  BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, NONE)
+  BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, NONE)
+  BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, NONE)
+  BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_laneq_, 0, NONE)
+  BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_lane_, 0, NONE)
+  BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_lane_, 0, NONE)
+  BUILTIN_VD_HSI (TERNOPU_LANE, vec_umult_laneq_, 0, NONE)
+  BUILTIN_VD_HSI (QUADOPU_LANE, vec_umlal_laneq_, 0, NONE)
 
   BUILTIN_VSD_HSI (BINOP, sqdmull, 0, ALL)
   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0, ALL)
@@ -217,63 +221,63 @@
   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0, ALL)
   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0, ALL)
 
-  BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, ALL)
+  BUILTIN_VSDQ_I_DI (BINOP, ashl, 3, NONE)
   /* Implemented by aarch64_<sur>shl<mode>.  */
-  BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, ALL)
-  BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, ALL)
-  BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, ALL)
-  BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, ALL)
+  BUILTIN_VSDQ_I_DI (BINOP, sshl, 0, NONE)
+  BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0, NONE)
+  BUILTIN_VSDQ_I_DI (BINOP, srshl, 0, NONE)
+  BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, NONE)
 
   /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>.  */
-  BUILTIN_VB (TERNOP, sdot, 0, ALL)
-  BUILTIN_VB (TERNOPU, udot, 0, ALL)
-  BUILTIN_VB (TERNOP_SSUS, usdot, 0, ALL)
-  BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, ALL)
-  BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, ALL)
-  BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, ALL)
-  BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, ALL)
-  BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, ALL)
-  BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, ALL)
-  BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, ALL)
-  BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, ALL)
+  BUILTIN_VB (TERNOP, sdot, 0, NONE)
+  BUILTIN_VB (TERNOPU, udot, 0, NONE)
+  BUILTIN_VB (TERNOP_SSUS, usdot, 0, NONE)
+  BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, NONE)
+  BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, NONE)
+  BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0, NONE)
+  BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0, NONE)
+  BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_lane, 0, NONE)
+  BUILTIN_VB (QUADOPSSUS_LANE_QUADTUP, usdot_laneq, 0, NONE)
+  BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_lane, 0, NONE)
+  BUILTIN_VB (QUADOPSSSU_LANE_QUADTUP, sudot_laneq, 0, NONE)
 
   /* Implemented by aarch64_fcadd<rot><mode>.   */
-  BUILTIN_VHSDF (BINOP, fcadd90, 0, ALL)
-  BUILTIN_VHSDF (BINOP, fcadd270, 0, ALL)
+  BUILTIN_VHSDF (BINOP, fcadd90, 0, FP)
+  BUILTIN_VHSDF (BINOP, fcadd270, 0, FP)
 
   /* Implemented by aarch64_fcmla{_lane}{q}<rot><mode>.   */
-  BUILTIN_VHSDF (TERNOP, fcmla0, 0, ALL)
-  BUILTIN_VHSDF (TERNOP, fcmla90, 0, ALL)
-  BUILTIN_VHSDF (TERNOP, fcmla180, 0, ALL)
-  BUILTIN_VHSDF (TERNOP, fcmla270, 0, ALL)
-  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, ALL)
-  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, ALL)
-  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0, ALL)
-  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0, ALL)
-
-  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0, ALL)
-  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0, ALL)
-  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0, ALL)
-  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0, ALL)
-
-  BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, ALL)
-  VAR1 (SHIFTIMM, ashr_simd, 0, ALL, di)
-  BUILTIN_VDQ_I (SHIFTIMM, lshr, 3, ALL)
-  VAR1 (USHIFTIMM, lshr_simd, 0, ALL, di)
+  BUILTIN_VHSDF (TERNOP, fcmla0, 0, FP)
+  BUILTIN_VHSDF (TERNOP, fcmla90, 0, FP)
+  BUILTIN_VHSDF (TERNOP, fcmla180, 0, FP)
+  BUILTIN_VHSDF (TERNOP, fcmla270, 0, FP)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, FP)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, FP)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane180, 0, FP)
+  BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane270, 0, FP)
+
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane0, 0, FP)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane90, 0, FP)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane180, 0, FP)
+  BUILTIN_VQ_HSF (QUADOP_LANE_PAIR, fcmlaq_lane270, 0, FP)
+
+  BUILTIN_VDQ_I (SHIFTIMM, ashr, 3, NONE)
+  VAR1 (SHIFTIMM, ashr_simd, 0, NONE, di)
+  BUILTIN_VDQ_I (SHIFTIMM, lshr, 3, NONE)
+  VAR1 (USHIFTIMM, lshr_simd, 0, NONE, di)
   /* Implemented by aarch64_<sur>shr_n<mode>.  */
-  BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, ALL)
+  BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0, NONE)
   /* Implemented by aarch64_<sur>sra_n<mode>.  */
-  BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, ALL)
+  BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0, NONE)
   /* Implemented by aarch64_<sur>shll_n<mode>.  */
-  BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, ALL)
-  BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, ALL)
+  BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0, NONE)
+  BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0, NONE)
   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
-  BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, ALL)
-  BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, ALL)
+  BUILTIN_VQW (SHIFTIMM, sshll2_n, 0, NONE)
+  BUILTIN_VQW (SHIFTIMM, ushll2_n, 0, NONE)
   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0, ALL)
   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0, ALL)
@@ -282,166 +286,166 @@
   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0, ALL)
   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0, ALL)
   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
-  BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, ALL)
-  BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, ALL)
-  VAR2 (SHIFTINSERTP, ssli_n, 0, ALL, di, v2di)
-  BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, ALL)
+  BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0, NONE)
+  BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0, NONE)
+  VAR2 (SHIFTINSERTP, ssli_n, 0, NONE, di, v2di)
+  BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0, NONE)
   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0, ALL)
   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0, ALL)
   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0, ALL)
 
   /* Implemented by aarch64_reduc_plus_<mode>.  */
-  BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, ALL)
+  BUILTIN_VALL (UNOP, reduc_plus_scal_, 10, NONE)
 
   /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar).  */
-  BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10, ALL)
-  BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10, ALL)
-  BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10, ALL)
-  BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10, ALL)
-  BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10, ALL)
-  BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10, ALL)
+  BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10, NONE)
+  BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10, NONE)
+  BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10, NONE)
+  BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10, NONE)
+  BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10, NONE)
+  BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10, NONE)
 
   /* Implemented by <maxmin_uns><mode>3.
      smax variants map to fmaxnm,
      smax_nan variants map to fmax.  */
-  BUILTIN_VDQ_BHSI (BINOP, smax, 3, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, smin, 3, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, umax, 3, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, umin, 3, ALL)
-  BUILTIN_VHSDF_DF (BINOP, smax_nan, 3, ALL)
-  BUILTIN_VHSDF_DF (BINOP, smin_nan, 3, ALL)
+  BUILTIN_VDQ_BHSI (BINOP, smax, 3, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, smin, 3, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, umax, 3, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, umin, 3, NONE)
+  BUILTIN_VHSDF_DF (BINOP, smax_nan, 3, NONE)
+  BUILTIN_VHSDF_DF (BINOP, smin_nan, 3, NONE)
 
   /* Implemented by <maxmin_uns><mode>3.  */
-  BUILTIN_VHSDF_HSDF (BINOP, fmax, 3, ALL)
-  BUILTIN_VHSDF_HSDF (BINOP, fmin, 3, ALL)
+  BUILTIN_VHSDF_HSDF (BINOP, fmax, 3, FP)
+  BUILTIN_VHSDF_HSDF (BINOP, fmin, 3, FP)
 
   /* Implemented by aarch64_<maxmin_uns>p<mode>.  */
-  BUILTIN_VDQ_BHSI (BINOP, smaxp, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, sminp, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, umaxp, 0, ALL)
-  BUILTIN_VDQ_BHSI (BINOP, uminp, 0, ALL)
-  BUILTIN_VHSDF (BINOP, smaxp, 0, ALL)
-  BUILTIN_VHSDF (BINOP, sminp, 0, ALL)
-  BUILTIN_VHSDF (BINOP, smax_nanp, 0, ALL)
-  BUILTIN_VHSDF (BINOP, smin_nanp, 0, ALL)
+  BUILTIN_VDQ_BHSI (BINOP, smaxp, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, sminp, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, umaxp, 0, NONE)
+  BUILTIN_VDQ_BHSI (BINOP, uminp, 0, NONE)
+  BUILTIN_VHSDF (BINOP, smaxp, 0, NONE)
+  BUILTIN_VHSDF (BINOP, sminp, 0, NONE)
+  BUILTIN_VHSDF (BINOP, smax_nanp, 0, NONE)
+  BUILTIN_VHSDF (BINOP, smin_nanp, 0, NONE)
 
   /* Implemented by <frint_pattern><mode>2.  */
-  BUILTIN_VHSDF (UNOP, btrunc, 2, ALL)
-  BUILTIN_VHSDF (UNOP, ceil, 2, ALL)
-  BUILTIN_VHSDF (UNOP, floor, 2, ALL)
-  BUILTIN_VHSDF (UNOP, nearbyint, 2, ALL)
-  BUILTIN_VHSDF (UNOP, rint, 2, ALL)
-  BUILTIN_VHSDF (UNOP, round, 2, ALL)
-  BUILTIN_VHSDF_DF (UNOP, frintn, 2, ALL)
-
-  VAR1 (UNOP, btrunc, 2, ALL, hf)
-  VAR1 (UNOP, ceil, 2, ALL, hf)
-  VAR1 (UNOP, floor, 2, ALL, hf)
-  VAR1 (UNOP, frintn, 2, ALL, hf)
-  VAR1 (UNOP, nearbyint, 2, ALL, hf)
-  VAR1 (UNOP, rint, 2, ALL, hf)
-  VAR1 (UNOP, round, 2, ALL, hf)
+  BUILTIN_VHSDF (UNOP, btrunc, 2, FP)
+  BUILTIN_VHSDF (UNOP, ceil, 2, FP)
+  BUILTIN_VHSDF (UNOP, floor, 2, FP)
+  BUILTIN_VHSDF (UNOP, nearbyint, 2, FP)
+  BUILTIN_VHSDF (UNOP, rint, 2, FP)
+  BUILTIN_VHSDF (UNOP, round, 2, FP)
+  BUILTIN_VHSDF_DF (UNOP, frintn, 2, FP)
+
+  VAR1 (UNOP, btrunc, 2, FP, hf)
+  VAR1 (UNOP, ceil, 2, FP, hf)
+  VAR1 (UNOP, floor, 2, FP, hf)
+  VAR1 (UNOP, frintn, 2, FP, hf)
+  VAR1 (UNOP, nearbyint, 2, FP, hf)
+  VAR1 (UNOP, rint, 2, FP, hf)
+  VAR1 (UNOP, round, 2, FP, hf)
 
   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
-  VAR1 (UNOP, lbtruncv4hf, 2, ALL, v4hi)
-  VAR1 (UNOP, lbtruncv8hf, 2, ALL, v8hi)
-  VAR1 (UNOP, lbtruncv2sf, 2, ALL, v2si)
-  VAR1 (UNOP, lbtruncv4sf, 2, ALL, v4si)
-  VAR1 (UNOP, lbtruncv2df, 2, ALL, v2di)
-
-  VAR1 (UNOPUS, lbtruncuv4hf, 2, ALL, v4hi)
-  VAR1 (UNOPUS, lbtruncuv8hf, 2, ALL, v8hi)
-  VAR1 (UNOPUS, lbtruncuv2sf, 2, ALL, v2si)
-  VAR1 (UNOPUS, lbtruncuv4sf, 2, ALL, v4si)
-  VAR1 (UNOPUS, lbtruncuv2df, 2, ALL, v2di)
-
-  VAR1 (UNOP, lroundv4hf, 2, ALL, v4hi)
-  VAR1 (UNOP, lroundv8hf, 2, ALL, v8hi)
-  VAR1 (UNOP, lroundv2sf, 2, ALL, v2si)
-  VAR1 (UNOP, lroundv4sf, 2, ALL, v4si)
-  VAR1 (UNOP, lroundv2df, 2, ALL, v2di)
+  VAR1 (UNOP, lbtruncv4hf, 2, FP, v4hi)
+  VAR1 (UNOP, lbtruncv8hf, 2, FP, v8hi)
+  VAR1 (UNOP, lbtruncv2sf, 2, FP, v2si)
+  VAR1 (UNOP, lbtruncv4sf, 2, FP, v4si)
+  VAR1 (UNOP, lbtruncv2df, 2, FP, v2di)
+
+  VAR1 (UNOPUS, lbtruncuv4hf, 2, FP, v4hi)
+  VAR1 (UNOPUS, lbtruncuv8hf, 2, FP, v8hi)
+  VAR1 (UNOPUS, lbtruncuv2sf, 2, FP, v2si)
+  VAR1 (UNOPUS, lbtruncuv4sf, 2, FP, v4si)
+  VAR1 (UNOPUS, lbtruncuv2df, 2, FP, v2di)
+
+  VAR1 (UNOP, lroundv4hf, 2, FP, v4hi)
+  VAR1 (UNOP, lroundv8hf, 2, FP, v8hi)
+  VAR1 (UNOP, lroundv2sf, 2, FP, v2si)
+  VAR1 (UNOP, lroundv4sf, 2, FP, v4si)
+  VAR1 (UNOP, lroundv2df, 2, FP, v2di)
   /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2.  */
-  BUILTIN_GPI_I16 (UNOP, lroundhf, 2, ALL)
-  VAR1 (UNOP, lroundsf, 2, ALL, si)
-  VAR1 (UNOP, lrounddf, 2, ALL, di)
-
-  VAR1 (UNOPUS, lrounduv4hf, 2, ALL, v4hi)
-  VAR1 (UNOPUS, lrounduv8hf, 2, ALL, v8hi)
-  VAR1 (UNOPUS, lrounduv2sf, 2, ALL, v2si)
-  VAR1 (UNOPUS, lrounduv4sf, 2, ALL, v4si)
-  VAR1 (UNOPUS, lrounduv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2, ALL)
-  VAR1 (UNOPUS, lroundusf, 2, ALL, si)
-  VAR1 (UNOPUS, lroundudf, 2, ALL, di)
-
-  VAR1 (UNOP, lceilv4hf, 2, ALL, v4hi)
-  VAR1 (UNOP, lceilv8hf, 2, ALL, v8hi)
-  VAR1 (UNOP, lceilv2sf, 2, ALL, v2si)
-  VAR1 (UNOP, lceilv4sf, 2, ALL, v4si)
-  VAR1 (UNOP, lceilv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOP, lceilhf, 2, ALL)
-
-  VAR1 (UNOPUS, lceiluv4hf, 2, ALL, v4hi)
-  VAR1 (UNOPUS, lceiluv8hf, 2, ALL, v8hi)
-  VAR1 (UNOPUS, lceiluv2sf, 2, ALL, v2si)
-  VAR1 (UNOPUS, lceiluv4sf, 2, ALL, v4si)
-  VAR1 (UNOPUS, lceiluv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2, ALL)
-  VAR1 (UNOPUS, lceilusf, 2, ALL, si)
-  VAR1 (UNOPUS, lceiludf, 2, ALL, di)
-
-  VAR1 (UNOP, lfloorv4hf, 2, ALL, v4hi)
-  VAR1 (UNOP, lfloorv8hf, 2, ALL, v8hi)
-  VAR1 (UNOP, lfloorv2sf, 2, ALL, v2si)
-  VAR1 (UNOP, lfloorv4sf, 2, ALL, v4si)
-  VAR1 (UNOP, lfloorv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOP, lfloorhf, 2, ALL)
-
-  VAR1 (UNOPUS, lflooruv4hf, 2, ALL, v4hi)
-  VAR1 (UNOPUS, lflooruv8hf, 2, ALL, v8hi)
-  VAR1 (UNOPUS, lflooruv2sf, 2, ALL, v2si)
-  VAR1 (UNOPUS, lflooruv4sf, 2, ALL, v4si)
-  VAR1 (UNOPUS, lflooruv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2, ALL)
-  VAR1 (UNOPUS, lfloorusf, 2, ALL, si)
-  VAR1 (UNOPUS, lfloorudf, 2, ALL, di)
-
-  VAR1 (UNOP, lfrintnv4hf, 2, ALL, v4hi)
-  VAR1 (UNOP, lfrintnv8hf, 2, ALL, v8hi)
-  VAR1 (UNOP, lfrintnv2sf, 2, ALL, v2si)
-  VAR1 (UNOP, lfrintnv4sf, 2, ALL, v4si)
-  VAR1 (UNOP, lfrintnv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2, ALL)
-  VAR1 (UNOP, lfrintnsf, 2, ALL, si)
-  VAR1 (UNOP, lfrintndf, 2, ALL, di)
-
-  VAR1 (UNOPUS, lfrintnuv4hf, 2, ALL, v4hi)
-  VAR1 (UNOPUS, lfrintnuv8hf, 2, ALL, v8hi)
-  VAR1 (UNOPUS, lfrintnuv2sf, 2, ALL, v2si)
-  VAR1 (UNOPUS, lfrintnuv4sf, 2, ALL, v4si)
-  VAR1 (UNOPUS, lfrintnuv2df, 2, ALL, v2di)
-  BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2, ALL)
-  VAR1 (UNOPUS, lfrintnusf, 2, ALL, si)
-  VAR1 (UNOPUS, lfrintnudf, 2, ALL, di)
+  BUILTIN_GPI_I16 (UNOP, lroundhf, 2, FP)
+  VAR1 (UNOP, lroundsf, 2, FP, si)
+  VAR1 (UNOP, lrounddf, 2, FP, di)
+
+  VAR1 (UNOPUS, lrounduv4hf, 2, FP, v4hi)
+  VAR1 (UNOPUS, lrounduv8hf, 2, FP, v8hi)
+  VAR1 (UNOPUS, lrounduv2sf, 2, FP, v2si)
+  VAR1 (UNOPUS, lrounduv4sf, 2, FP, v4si)
+  VAR1 (UNOPUS, lrounduv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2, FP)
+  VAR1 (UNOPUS, lroundusf, 2, FP, si)
+  VAR1 (UNOPUS, lroundudf, 2, FP, di)
+
+  VAR1 (UNOP, lceilv4hf, 2, FP, v4hi)
+  VAR1 (UNOP, lceilv8hf, 2, FP, v8hi)
+  VAR1 (UNOP, lceilv2sf, 2, FP, v2si)
+  VAR1 (UNOP, lceilv4sf, 2, FP, v4si)
+  VAR1 (UNOP, lceilv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOP, lceilhf, 2, FP)
+
+  VAR1 (UNOPUS, lceiluv4hf, 2, FP, v4hi)
+  VAR1 (UNOPUS, lceiluv8hf, 2, FP, v8hi)
+  VAR1 (UNOPUS, lceiluv2sf, 2, FP, v2si)
+  VAR1 (UNOPUS, lceiluv4sf, 2, FP, v4si)
+  VAR1 (UNOPUS, lceiluv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2, FP)
+  VAR1 (UNOPUS, lceilusf, 2, FP, si)
+  VAR1 (UNOPUS, lceiludf, 2, FP, di)
+
+  VAR1 (UNOP, lfloorv4hf, 2, FP, v4hi)
+  VAR1 (UNOP, lfloorv8hf, 2, FP, v8hi)
+  VAR1 (UNOP, lfloorv2sf, 2, FP, v2si)
+  VAR1 (UNOP, lfloorv4sf, 2, FP, v4si)
+  VAR1 (UNOP, lfloorv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOP, lfloorhf, 2, FP)
+
+  VAR1 (UNOPUS, lflooruv4hf, 2, FP, v4hi)
+  VAR1 (UNOPUS, lflooruv8hf, 2, FP, v8hi)
+  VAR1 (UNOPUS, lflooruv2sf, 2, FP, v2si)
+  VAR1 (UNOPUS, lflooruv4sf, 2, FP, v4si)
+  VAR1 (UNOPUS, lflooruv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2, FP)
+  VAR1 (UNOPUS, lfloorusf, 2, FP, si)
+  VAR1 (UNOPUS, lfloorudf, 2, FP, di)
+
+  VAR1 (UNOP, lfrintnv4hf, 2, FP, v4hi)
+  VAR1 (UNOP, lfrintnv8hf, 2, FP, v8hi)
+  VAR1 (UNOP, lfrintnv2sf, 2, FP, v2si)
+  VAR1 (UNOP, lfrintnv4sf, 2, FP, v4si)
+  VAR1 (UNOP, lfrintnv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2, FP)
+  VAR1 (UNOP, lfrintnsf, 2, FP, si)
+  VAR1 (UNOP, lfrintndf, 2, FP, di)
+
+  VAR1 (UNOPUS, lfrintnuv4hf, 2, FP, v4hi)
+  VAR1 (UNOPUS, lfrintnuv8hf, 2, FP, v8hi)
+  VAR1 (UNOPUS, lfrintnuv2sf, 2, FP, v2si)
+  VAR1 (UNOPUS, lfrintnuv4sf, 2, FP, v4si)
+  VAR1 (UNOPUS, lfrintnuv2df, 2, FP, v2di)
+  BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2, FP)
+  VAR1 (UNOPUS, lfrintnusf, 2, FP, si)
+  VAR1 (UNOPUS, lfrintnudf, 2, FP, di)
 
   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
-  VAR1 (UNOP, floatv4hi, 2, ALL, v4hf)
-  VAR1 (UNOP, floatv8hi, 2, ALL, v8hf)
-  VAR1 (UNOP, floatv2si, 2, ALL, v2sf)
-  VAR1 (UNOP, floatv4si, 2, ALL, v4sf)
-  VAR1 (UNOP, floatv2di, 2, ALL, v2df)
+  VAR1 (UNOP, floatv4hi, 2, FP, v4hf)
+  VAR1 (UNOP, floatv8hi, 2, FP, v8hf)
+  VAR1 (UNOP, floatv2si, 2, FP, v2sf)
+  VAR1 (UNOP, floatv4si, 2, FP, v4sf)
+  VAR1 (UNOP, floatv2di, 2, FP, v2df)
 
-  VAR1 (UNOP, floatunsv4hi, 2, ALL, v4hf)
-  VAR1 (UNOP, floatunsv8hi, 2, ALL, v8hf)
-  VAR1 (UNOP, floatunsv2si, 2, ALL, v2sf)
-  VAR1 (UNOP, floatunsv4si, 2, ALL, v4sf)
-  VAR1 (UNOP, floatunsv2di, 2, ALL, v2df)
+  VAR1 (UNOP, floatunsv4hi, 2, FP, v4hf)
+  VAR1 (UNOP, floatunsv8hi, 2, FP, v8hf)
+  VAR1 (UNOP, floatunsv2si, 2, FP, v2sf)
+  VAR1 (UNOP, floatunsv4si, 2, FP, v4sf)
+  VAR1 (UNOP, floatunsv2di, 2, FP, v2df)
 
-  VAR5 (UNOPU, bswap, 2, ALL, v4hi, v8hi, v2si, v4si, v2di)
+  VAR5 (UNOPU, bswap, 2, NONE, v4hi, v8hi, v2si, v4si, v2di)
 
-  BUILTIN_VB (UNOP, rbit, 0, ALL)
+  BUILTIN_VB (UNOP, rbit, 0, NONE)
 
   /* Implemented by
      aarch64_<PERMUTE:perm_insn><mode>.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c b/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
index a7b7cd3bd8d..ef70f75e75e 100644
--- a/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
@@ -3,7 +3,7 @@
 
 #include "arm_neon.h"
 
-void foo (int a)
+int32x2_t foo (int a)
 {
   int32x2_t arg1;
   int32x2_t arg2;
@@ -15,4 +15,5 @@ void foo (int a)
      we have to tell dg-error to ignore the line number.  */
   result = vrsra_n_s32 (arg1, arg2, a);
   /* { dg-error "must be a constant immediate" "" { target *-*-* } 0 } */
+  return result;
 }
-- 
2.19.1