From: Julian Brown <julian@codesourcery.com>
To: <gcc-patches@gcc.gnu.org>
Cc: <fortran@gcc.gnu.org>, Tobias Burnus <tobias@codesourcery.com>,
Jakub Jelinek <jakub@redhat.com>,
Thomas Schwinge <thomas@codesourcery.com>,
Andrew Stubbs <ams@codesourcery.com>
Subject: [PATCH 3/5] amdgcn: Add clrsbsi2/clrsbdi2 implementation
Date: Fri, 18 Jun 2021 07:19:32 -0700 [thread overview]
Message-ID: <0ec87e2fb22898e2578c4deacfce958b92c6d94f.1624025450.git.julian@codesourcery.com> (raw)
In-Reply-To: <cover.1624025450.git.julian@codesourcery.com>
This patch adds an open-coded implementation of the clrsb<mode>2
(count leading redundant sign bit) standard names using the GCN flbit_i*
instructions for SImode and DImode. Those don't count exactly as we need,
so we need a couple of other instructions to fix up the result afterwards.
These patterns are lost from libgcc if we build it for DImode/TImode
rather than SImode/DImode, a change we make in a later patch in this
series.
I can probably self-approve this, but I'll give Andrew Stubbs a chance
to comment.
Thanks,
Julian
2021-06-18 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn.md (UNSPEC_FLBIT_INT): New unspec constant.
(s_mnemonic): Add clrsb.
(gcn_flbit<mode>_int): Add insn pattern for SImode/DImode.
(clrsb<mode>2): Add expander for SImode/DImode.
---
gcc/config/gcn/gcn.md | 40 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 70655ca4b8b..0fa7f86702e 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -81,7 +81,8 @@
UNSPEC_MOV_FROM_LANE63
UNSPEC_GATHER
UNSPEC_SCATTER
- UNSPEC_RCP])
+ UNSPEC_RCP
+ UNSPEC_FLBIT_INT])
;; }}}
;; {{{ Attributes
@@ -338,7 +339,8 @@
[(not "not%b")
(popcount "bcnt1_i32%b")
(clz "flbit_i32%b")
- (ctz "ff1_i32%b")])
+ (ctz "ff1_i32%b")
+ (clrsb "flbit_i32%i")])
(define_code_attr revmnemonic
[(minus "subrev%i")
@@ -1509,6 +1511,40 @@
[(set_attr "type" "sop1")
(set_attr "length" "4,8")])
+(define_insn "gcn_flbit<mode>_int"
+ [(set (match_operand:SI 0 "register_operand" "=Sg,Sg")
+ (unspec:SI [(match_operand:SIDI 1 "gcn_alu_operand" "SgA, B")]
+ UNSPEC_FLBIT_INT))]
+ ""
+ {
+ if (<MODE>mode == SImode)
+ return "s_flbit_i32\t%0, %1";
+ else
+ return "s_flbit_i32_i64\t%0, %1";
+ }
+ [(set_attr "type" "sop1")
+ (set_attr "length" "4,8")])
+
+(define_expand "clrsb<mode>2"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (clrsb:SI (match_operand:SIDI 1 "gcn_alu_operand" "")))]
+ ""
+ {
+ rtx tmp = gen_reg_rtx (SImode);
+ /* FLBIT_I* counts sign or zero bits at the most-significant end of the
+ input register (and returns -1 for 0/-1 inputs). We want the number of
+ *redundant* bits (i.e. that value minus one), and an answer of 31/63 for
+ 0/-1 inputs. We can do that in three instructions... */
+ emit_insn (gen_gcn_flbit<mode>_int (tmp, operands[1]));
+ emit_insn (gen_uminsi3 (tmp, tmp,
+ gen_int_mode (GET_MODE_BITSIZE (<MODE>mode),
+ SImode)));
+ /* If we put this last, it can potentially be folded into a subsequent
+ arithmetic operation. */
+ emit_insn (gen_subsi3 (operands[0], tmp, const1_rtx));
+ DONE;
+ })
+
;; }}}
;; {{{ ALU: generic 32-bit binop
--
2.29.2
next prev parent reply other threads:[~2021-06-18 14:20 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 14:19 [PATCH 0/5] amdgcn: Improve TImode support Julian Brown
2021-06-18 14:19 ` [PATCH 1/5] amdgcn: Use unsigned types for udivsi3/umodsi3 libgcc helper args/return Julian Brown
2021-06-18 15:15 ` Andrew Stubbs
2021-06-18 14:19 ` [PATCH 2/5] amdgcn: Add [us]mulsi3_highpart SGPR alternatives & [us]mulsid3/muldi3 expanders Julian Brown
2021-06-18 14:55 ` Andrew Stubbs
2021-06-29 15:10 ` Julian Brown
2021-06-18 14:19 ` Julian Brown [this message]
2021-06-18 15:01 ` [PATCH 3/5] amdgcn: Add clrsbsi2/clrsbdi2 implementation Andrew Stubbs
2021-06-18 14:19 ` [PATCH 4/5] amdgcn: Enable support for TImode for AMD GCN Julian Brown
2021-06-18 15:08 ` Andrew Stubbs
2021-06-18 14:20 ` [PATCH 5/5] Fortran: Re-enable 128-bit integers " Julian Brown
2021-06-21 11:15 ` Tobias Burnus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0ec87e2fb22898e2578c4deacfce958b92c6d94f.1624025450.git.julian@codesourcery.com \
--to=julian@codesourcery.com \
--cc=ams@codesourcery.com \
--cc=fortran@gcc.gnu.org \
--cc=gcc-patches@gcc.gnu.org \
--cc=jakub@redhat.com \
--cc=thomas@codesourcery.com \
--cc=tobias@codesourcery.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).