From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from esa2.mentor.iphmx.com (esa2.mentor.iphmx.com [68.232.141.98]) by sourceware.org (Postfix) with ESMTPS id 451B83AA9830; Fri, 18 Jun 2021 14:20:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 451B83AA9830 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: vhQmxYfzHAyOUNWu+nZJJFILcJnWCZA0K0SP6kCJMH5WsnbeNKi0/E2GaTAA0s9u6N4mJq9GbM gibE9UyzSXD4c5ep56tx8A7FFAy0V4uaxI4R6FvBsOE8bjdd2qoXkpWj0p876Wl3P5svWp8+IO j+0xWs0vA7Yxh7+0sjZ9EPqP43BxoYKPswlq+qyJP1HnBxiB/LdPNsoIMgoZUONHCoD+W+8Ua+ 9jSMtxm0o0pRF6La5r/6IfkWASpowaxA5primBvnM/MFVFddrjwuu+gkRMiNSmfcMRExpeZ85K 7TY= X-IronPort-AV: E=Sophos;i="5.83,284,1616486400"; d="scan'208";a="62563389" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa2.mentor.iphmx.com with ESMTP; 18 Jun 2021 06:20:00 -0800 IronPort-SDR: dpj5QVTe7t5+bRiG1Fn/AFoYQrSkHMw/pc9uhad7wivgqaeZ9emKBJwbQ7pEJLxU+Etkippsoz teBdfPE+zmwyAnF9WbgCBXESElVFYZdh9VepaEjdESqo9DXrtnW3k9mVqumiQqzve04+As9s3D V6kF/A2uVic1zrJNp6H2J1DgzNmCcJ+kEh/uvuZoSz40Q//TqHsxeZhbiC8ojy7ZBnmUU65xgb P6YqHws39F2HtdJElunceGDwXddIdu8qhvgWZDB1QFPcl5T1Rq4xlRZQQ6HfpHTuQ0pvXkpHop Zp4= From: Julian Brown To: CC: , Tobias Burnus , Jakub Jelinek , Thomas Schwinge , Andrew Stubbs Subject: [PATCH 3/5] amdgcn: Add clrsbsi2/clrsbdi2 implementation Date: Fri, 18 Jun 2021 07:19:32 -0700 Message-ID: <0ec87e2fb22898e2578c4deacfce958b92c6d94f.1624025450.git.julian@codesourcery.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-07.mgc.mentorg.com (139.181.222.7) To SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Jun 2021 14:20:01 -0000 This patch adds an open-coded implementation of the clrsb2 (count leading redundant sign bit) standard names using the GCN flbit_i* instructions for SImode and DImode. Those don't count exactly as we need, so we need a couple of other instructions to fix up the result afterwards. These patterns are lost from libgcc if we build it for DImode/TImode rather than SImode/DImode, a change we make in a later patch in this series. I can probably self-approve this, but I'll give Andrew Stubbs a chance to comment. Thanks, Julian 2021-06-18 Julian Brown gcc/ * config/gcn/gcn.md (UNSPEC_FLBIT_INT): New unspec constant. (s_mnemonic): Add clrsb. (gcn_flbit_int): Add insn pattern for SImode/DImode. (clrsb2): Add expander for SImode/DImode. --- gcc/config/gcn/gcn.md | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 70655ca4b8b..0fa7f86702e 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -81,7 +81,8 @@ UNSPEC_MOV_FROM_LANE63 UNSPEC_GATHER UNSPEC_SCATTER - UNSPEC_RCP]) + UNSPEC_RCP + UNSPEC_FLBIT_INT]) ;; }}} ;; {{{ Attributes @@ -338,7 +339,8 @@ [(not "not%b") (popcount "bcnt1_i32%b") (clz "flbit_i32%b") - (ctz "ff1_i32%b")]) + (ctz "ff1_i32%b") + (clrsb "flbit_i32%i")]) (define_code_attr revmnemonic [(minus "subrev%i") @@ -1509,6 +1511,40 @@ [(set_attr "type" "sop1") (set_attr "length" "4,8")]) +(define_insn "gcn_flbit_int" + [(set (match_operand:SI 0 "register_operand" "=Sg,Sg") + (unspec:SI [(match_operand:SIDI 1 "gcn_alu_operand" "SgA, B")] + UNSPEC_FLBIT_INT))] + "" + { + if (mode == SImode) + return "s_flbit_i32\t%0, %1"; + else + return "s_flbit_i32_i64\t%0, %1"; + } + [(set_attr "type" "sop1") + (set_attr "length" "4,8")]) + +(define_expand "clrsb2" + [(set (match_operand:SI 0 "register_operand" "") + (clrsb:SI (match_operand:SIDI 1 "gcn_alu_operand" "")))] + "" + { + rtx tmp = gen_reg_rtx (SImode); + /* FLBIT_I* counts sign or zero bits at the most-significant end of the + input register (and returns -1 for 0/-1 inputs). We want the number of + *redundant* bits (i.e. that value minus one), and an answer of 31/63 for + 0/-1 inputs. We can do that in three instructions... */ + emit_insn (gen_gcn_flbit_int (tmp, operands[1])); + emit_insn (gen_uminsi3 (tmp, tmp, + gen_int_mode (GET_MODE_BITSIZE (mode), + SImode))); + /* If we put this last, it can potentially be folded into a subsequent + arithmetic operation. */ + emit_insn (gen_subsi3 (operands[0], tmp, const1_rtx)); + DONE; + }) + ;; }}} ;; {{{ ALU: generic 32-bit binop -- 2.29.2