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([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id f9-20020aa782c9000000b00640f588b36dsm3397413pfn.8.2023.05.06.10.01.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 06 May 2023 10:01:46 -0700 (PDT) Message-ID: <0fe2501f-9a0f-e502-233e-59764078583b@gmail.com> Date: Sat, 6 May 2023 11:01:45 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v6 1/9] RISC-V: autovec: Add new predicates and function prototypes Content-Language: en-US To: Michael Collison , gcc-patches@gcc.gnu.org References: <20230505154607.1155567-1-collison@rivosinc.com> <20230505154607.1155567-2-collison@rivosinc.com> From: Jeff Law In-Reply-To: <20230505154607.1155567-2-collison@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 5/5/23 09:45, Michael Collison wrote: > 2023-04-24 Michael Collison > Juzhe Zhong > > * config/riscv/riscv-protos.h > (riscv_vector_preferred_simd_mode): New. > (riscv_vector_mask_mode_p): Ditto. > (riscv_vector_get_mask_mode): Ditto. > (emit_vlmax_vsetvl): Ditto. > (get_mask_policy_no_pred): Ditto. > (get_tail_policy_no_pred): Ditto. > (vlmul_field_enum): Ditto. > * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): > Remove static scope. > * config/riscv/riscv-opts.h (riscv_vector_lmul_enum): New enum. > --- > gcc/config/riscv/riscv-opts.h | 10 ++++++++++ > gcc/config/riscv/riscv-protos.h | 9 +++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 4207db240ea..00c4ab222ae 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -67,6 +67,7 @@ enum stack_protector_guard { > SSP_GLOBAL /* global canary */ > }; > > + > /* RISC-V auto-vectorization preference. */ > enum riscv_autovec_preference_enum { > NO_AUTOVEC, Extranous change. Removed. > @@ -82,6 +83,15 @@ enum riscv_autovec_lmul_enum { > RVV_M8 = 8 > }; > > +/* vectorization factor. */ > +enum riscv_vector_lmul_enum > +{ > + RVV_LMUL1 = 1, > + RVV_LMUL2 = 2, > + RVV_LMUL4 = 4, > + RVV_LMUL8 = 8 > +}; > + > #define MASK_ZICSR (1 << 0) > #define MASK_ZIFENCEI (1 << 1) > I ack'd this hunk earlier, but Kito asked for it to be removed. Given I don't see any uses of LMUL in the series, I'm just going to remove this for now. We can always add it back at the point where we need it. > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index 33eb574aadc..fb39b856735 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -243,4 +243,13 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); > #endif > > extern bool riscv_use_divmod_expander (void); > +/* Routines implemented in riscv-v.cc. */ > + > +namespace riscv_vector { > +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode); This prototype is on the trunk now. > +extern bool riscv_vector_mask_mode_p (machine_mode); > +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); > +extern rtx get_mask_policy_no_pred (); > +extern rtx get_tail_policy_no_pred (); I'll go ahead and commit these. I think that's all that's left from this patch. Going forward, the right time to add the prototypes is in the same patch that adds the function. Jeff