Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law <jeffreyalaw@gmail.com>]

On 9/11/23 21:17, Lehua Ding wrote:
> Hi Jeff,
> 
> On 2023/9/12 11:00, Jeff Law wrote:
>> I'd rather be consistent and make it policy that every insn has a type.
> 
> Since the type set here will not be used by sched pass (these insn 
> pattern will not exit at shced pass since use define_insn_and_split with 
> condition `TARGET_VECTOR && can_create_pseudo_p ()`), I think it is easy 
> to cause misunderstanding and some problems are not easy to find (e.g. 
> accidentally went through the sched pass should be assert error).
But that condition is _not_ generally sufficient to prevent these insns 
from existing during sched1.  ie, a pass between split1 and sched1 could 
create these patterns and successfully match them.  That in turn would 
trigger the assertion.

can_create_pseudo_p is true up through the register allocator.  As a 
result a condition like TARGET_VECTOR && can_create_pseudo_p() is _not_ 
sufficient to ensure the pattern does not exist during sched1.  While no 
pass likely creates these kinds of insns right now in that window 
between split1 and sched1, there's no guarantee that will always be true.

The simple rule is easy to follow.  Every insn should have a type.  That 
also gives us a degree of future-proof, even if someone adds additional 
passes/capabilities between split1 and sched1.


jeff