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From: Jeff Law <jeffreyalaw@gmail.com>
To: Christoph Muellner <christoph.muellner@vrull.eu>,
	gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: Re: [PATCH] riscv: Synthesize all 11-bit-rotate constants with rori
Date: Tue, 5 Sep 2023 15:57:47 -0600	[thread overview]
Message-ID: <116ee849-d822-4467-af87-9f74b5a1a211@gmail.com> (raw)
In-Reply-To: <20230905211559.2871358-1-christoph.muellner@vrull.eu>



On 9/5/23 15:15, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Some constants can be built up using LI+RORI instructions.
> The current implementation requires one of the upper 32-bits
> to be a zero bit, which is not neccesary.
> Let's drop this requirement in order to be able to synthesize
> a constant like 0xffffffff00ffffffL.
> 
> The tests for LI+RORI are made more strict to detect regression
> in the calculation of the LI constant and the rotation amount.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_build_integer_1): Don't
> 	require one zero bit in the upper 32 bits for LI+RORI synthesis.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/xtheadbb-li-rotr.c: New tests.
> 	* gcc.target/riscv/zbb-li-rotr.c: Likewise.
OK
jeff

  reply	other threads:[~2023-09-05 21:57 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-05 21:15 Christoph Muellner
2023-09-05 21:57 ` Jeff Law [this message]
2023-09-05 21:59   ` Philipp Tomsich

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