From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id BB2883858D28 for ; Tue, 5 Sep 2023 21:57:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BB2883858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-573e67cc6eeso652460a12.2 for ; Tue, 05 Sep 2023 14:57:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1693951075; x=1694555875; darn=gcc.gnu.org; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=Oe6nbn9wMDYS5SZFNvUVsb2e0FeWW2FYqm7bnM3QWds=; b=Nv4QfcrmQ1vDMVLsRanNwb9w2I/pk59XT4k+D+fS8afmyqD6q0abTQfJ8H5BskK/Oc wsYh/kDhQrS/Gr/AICHhKW+AbTSkI/jWyQjE4rqOaDeHLOulfBWaaSracYLtvKhAOs0j kREfFJl2G+xFo2kg/wQsxh2lmpq08PqKliy/sR7DBBnvwg/JOt5hxuCe98ggFkcTyWhA 8mJHXmTZyUZcK5yoOXN+G7C8Peinr1SFCclPa2u2ekX+pPLBo1wpPh/fbK/KyE+Ip3R5 TQD0J4G8RVMBkf0bBNX6NYiaakRBrpvDUA+JmsU7gTryEgup4/CL6uPH1RtcLt6eUFob Ru9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693951075; x=1694555875; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Oe6nbn9wMDYS5SZFNvUVsb2e0FeWW2FYqm7bnM3QWds=; b=ANm0jpSwvw899z4xWdDs+AWAyYUjnazbJV4uF1PGrCffuUXeH2qhaRrilKoqvrd2gm iFzXy6thJMrMwse/ymdq33I2uFpp7jpzqsl19QBgMfLiWCGmP9I2auujJZficyyF2ZyE TUeZiNSuS2+t0RS8DcvFQMwN0jFNFiGh9bcd+y6mpLq69CZEdBIK+bWlwz/fV2qr3+ea KozU/myQPqXiRLQlK5KFdQFV1nZfFnLKwC/hkZyubdmNb8SF70FZW0gxQ42V1nVHnOln tpMIcxeZBX1kIRuogvywg07sg2/RyMHq6hQOH/dlHi0acGw2aZYYaCDE5nU7t50c98vd iYUQ== X-Gm-Message-State: AOJu0Yy11evRh/hTQp+5qYytEZD1Fxfg6utUWIm+IQesOWlg9ZI++Bxl CELido5Qj0EL5KzQywIeIeRYOtJJFPo6bg== X-Google-Smtp-Source: AGHT+IFe/m1J2oOMAXZ4cw2LWZ9RYefEAUSdkdWaMuITKMfxUwybondTtMPjMalrT0sSBUSw6EgNmw== X-Received: by 2002:a05:6300:8002:b0:140:8537:85c1 with SMTP id an2-20020a056300800200b00140853785c1mr11132186pzc.28.1693951074597; Tue, 05 Sep 2023 14:57:54 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id r8-20020a63b108000000b0056da0ae25cdsm10055037pgf.80.2023.09.05.14.57.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Sep 2023 14:57:54 -0700 (PDT) Message-ID: <116ee849-d822-4467-af87-9f74b5a1a211@gmail.com> Date: Tue, 5 Sep 2023 15:57:47 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] riscv: Synthesize all 11-bit-rotate constants with rori Content-Language: en-US To: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich References: <20230905211559.2871358-1-christoph.muellner@vrull.eu> From: Jeff Law In-Reply-To: <20230905211559.2871358-1-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_MANYTO,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 9/5/23 15:15, Christoph Muellner wrote: > From: Christoph Müllner > > Some constants can be built up using LI+RORI instructions. > The current implementation requires one of the upper 32-bits > to be a zero bit, which is not neccesary. > Let's drop this requirement in order to be able to synthesize > a constant like 0xffffffff00ffffffL. > > The tests for LI+RORI are made more strict to detect regression > in the calculation of the LI constant and the rotation amount. > > Signed-off-by: Christoph Müllner > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_build_integer_1): Don't > require one zero bit in the upper 32 bits for LI+RORI synthesis. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadbb-li-rotr.c: New tests. > * gcc.target/riscv/zbb-li-rotr.c: Likewise. OK jeff