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([2601:681:8d00:265::f0a]) by smtp.gmail.com with ESMTPSA id l2-20020a170902d34200b0019a773419a6sm1392359plk.170.2023.05.31.07.00.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 31 May 2023 07:00:04 -0700 (PDT) Message-ID: <116ffb47-e199-8829-b049-508ae0e6f811@gmail.com> Date: Wed, 31 May 2023 08:00:03 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH 1/2] Implementation of new RISCV optimizations pass: fold-mem-offsets. Content-Language: en-US To: Manolis Tsamis Cc: Richard Biener , gcc-patches@gcc.gnu.org References: <20230525123550.1072506-1-manolis.tsamis@vrull.eu> <20230525123550.1072506-2-manolis.tsamis@vrull.eu> From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 5/31/23 06:19, Manolis Tsamis wrote: > On Tue, May 30, 2023 at 2:30 AM Jeff Law wrote: >> >> >> >> On 5/25/23 08:02, Manolis Tsamis wrote: >>> On Thu, May 25, 2023 at 4:53 PM Richard Biener via Gcc-patches >>> wrote: >>>> >>>> On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches >>>> wrote: >>>>> >>>>> >>>>> >>>>> On 5/25/23 07:01, Richard Biener via Gcc-patches wrote: >>>>>> On Thu, May 25, 2023 at 2:36 PM Manolis Tsamis wrote: >>>>>>> >>>>>>> Implementation of the new RISC-V optimization pass for memory offset >>>>>>> calculations, documentation and testcases. >>>>>> >>>>>> Why do fwprop or combine not what you want to do? >>>>> I think a lot of them end up coming from register elimination. >>>> >>>> Why isn't this a problem for other targets then? Or maybe it is and this >>>> shouldn't be a machine specific pass? Maybe postreload-gcse should >>>> perform strength reduction (I can't think of any other post reload pass >>>> that would do something even remotely related). >>>> >>>> Richard. >>>> >>> >>> It should be a problem for other targets as well (especially RISC-style ISAs). >>> >>> It can be easily seen by comparing the generated code for the >>> testcases: Example for testcase-2 on AArch64: >>> https://godbolt.org/z/GMT1K7Ebr >>> Although the patterns in the test cases are the ones that are simple >>> as the complex ones manifest in complex programs, the case still >>> holds. >>> The code for this pass is quite generic and could work for most/all >>> targets if that would be interesting. >> Interestly enough, fold-mem-offsets seems to interact strangely with the >> load/store pair support on aarch64. Note show store2a uses 2 stp >> instructions on the trunk, but 4 str instructions with fold-mem-offsets. >> Yet in load1r we're able to generate a load-quad rather than two load >> pairs. Weird. >> > > I'm confused, where is this comparison from? > The fold-mem-offsets pass is only run on RISCV and doesn't (shouldn't) > affect AArch64. > > I only see the 2x stp / 4x str in the godbolt link, but that is gcc vs > clang, no fold-mem-offsets involved here. My bad! I should have looked at the headings more closely. I thought you'd set up a with/without fold-mem-offsets comparison. jeff