* [ARM] Why VFP spill slots not stack aligned?
@ 2009-09-19 4:56 Doug Kwan (關振德)
2009-10-14 14:33 ` Richard Earnshaw
0 siblings, 1 reply; 2+ messages in thread
From: Doug Kwan (關振德) @ 2009-09-19 4:56 UTC (permalink / raw)
To: gcc-patches
I saw a problem in which a function pushed a VFP register to an
non-64-bit-aligned address:
00000000 <cvt>:
0: b5f0 push {r4, r5, r6, r7, lr}
2: ed2d 8b02 vstmdb sp!, {d8}
6: b087 sub sp, #28
8: ec41 0b18 vmov d8, r0, r1
The above code was generated by gcc-4.4.0. I looked at the code in
arm.c and there is no code to ensure that the VFP registers are
spilled to 64-bit aligned addresses. Is that a bug?
-Doug
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [ARM] Why VFP spill slots not stack aligned?
2009-09-19 4:56 [ARM] Why VFP spill slots not stack aligned? Doug Kwan (關振德)
@ 2009-10-14 14:33 ` Richard Earnshaw
0 siblings, 0 replies; 2+ messages in thread
From: Richard Earnshaw @ 2009-10-14 14:33 UTC (permalink / raw)
To: Doug Kwan (關振德); +Cc: gcc-patches
On Fri, 2009-09-18 at 17:29 -0700, Doug Kwan (關振德) wrote:
> I saw a problem in which a function pushed a VFP register to an
> non-64-bit-aligned address:
>
> 00000000 <cvt>:
> 0: b5f0 push {r4, r5, r6, r7, lr}
>
> 2: ed2d 8b02 vstmdb sp!, {d8}
> 6: b087 sub sp, #28
> 8: ec41 0b18 vmov d8, r0, r1
>
> The above code was generated by gcc-4.4.0. I looked at the code in
> arm.c and there is no code to ensure that the VFP registers are
> spilled to 64-bit aligned addresses. Is that a bug?
No.
Potentially sub-optimal in terms of performance on some implementations,
but perfectly acceptable architecturally.
R.
^ permalink raw reply [flat|nested] 2+ messages in thread
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