Re: ARM ldm/stm peepholes

[Richard Earnshaw <rearnsha@arm.com>]

On Fri, 2010-04-23 at 09:13 +0100, Ramana Radhakrishnan wrote:
> Hi Bernd,
> 
> On Tue, 2010-04-20 at 13:41 +0200, Bernd Schmidt wrote:
> 
> > The patch may need more tuning to decide when to use these instructions;
> > I'll need suggestions as I don't think I have enough information
> > available to make these decisions.  For now, this uses the same
> > heuristics as previously, but it may trigger in slightly more
> > situations.  I'm open to suggestions.
> 
> Apologies for the delayed response, been away from my desk this week and
> will be away for more today.
> 
> It would be useful to be able to control ldm /stm generation on a
> per-core basis i.e. on some cores it might be useful to have ldm's and
> stm's as a size optimization rather than as a performance optimization.
> For instance the A8 and A9 have a good ldm and stm setup but there might
> be circumstances where this might not be the right thing to do.
> 

This shouldn't be done on an explicit 'per-core' basis, but on a cost of
alternatives basis.  That is, there should be a cost function that
returns the cost of an ldm with N registers; this can then be compared
with the cost of (N+1)/2 ldrd instructions (if valid) or N ldr
instructions and the cheapest alternative selected.  The new costing
framework that I committed last week should easily support adding such
functions.  It may be necessary to separate out the costs of LDM and STM
as they could, in theory be different.


R.