* [PATCH, ARM] Fix ICE (PR target/45805).
@ 2010-09-29 17:21 Tejas Belagod
2010-10-05 9:31 ` Richard Earnshaw
0 siblings, 1 reply; 2+ messages in thread
From: Tejas Belagod @ 2010-09-29 17:21 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 698 bytes --]
Hi,
This patch fixes bug PR target/45805. A missing constraint specifier in
patterns for vmovl and vmovn was causing the compiler to ICE by
matching memory operands instead of the intended register operands. A
'w' in the constraint specifier fixes the ICE. Also the instruction
templates for vmovl, vmovn and vmull have been fixed by adding intended
register specifiers.
OK?
--
Tejas Belagod
ARM.
gcc/
2010-09-29 Tejas Belagod <tejas.belagod@arm.com>
* config/arm/neon.md (neon_unpack<US>_<mode>): Add 'w' to
constraint, add register specifier in instruction template.
(neon_vec_pack_trunc_<mode>): Likewise.
(neon_vec_<US>mult_<mode>): Add register specifier to
instruction template.
[-- Attachment #2: 45805.txt --]
[-- Type: text/x-patch, Size: 1260 bytes --]
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 3bb74a2..1e88981 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5314,9 +5314,9 @@
;; Vectorize for non-neon-quad case
(define_insn "neon_unpack<US>_<mode>"
[(set (match_operand:<V_widen> 0 "register_operand" "=w")
- (SE:<V_widen> (match_operand:VDI 1 "register_operand" "")))]
+ (SE:<V_widen> (match_operand:VDI 1 "register_operand" "w")))]
"TARGET_NEON"
- "vmovl.<US><V_sz_elem> %q0, %1"
+ "vmovl.<US><V_sz_elem> %q0, %P1"
[(set_attr "neon_type" "neon_shift_1")]
)
@@ -5353,7 +5353,7 @@
(SE:<V_widen>
(match_operand:VDI 2 "register_operand" "w"))))]
"TARGET_NEON"
- "vmull.<US><V_sz_elem> %q0, %1, %2"
+ "vmull.<US><V_sz_elem> %q0, %P1, %P2"
[(set_attr "neon_type" "neon_shift_1")]
)
@@ -5402,9 +5402,9 @@
;; For the non-quad case.
(define_insn "neon_vec_pack_trunc_<mode>"
[(set (match_operand:<V_narrow> 0 "register_operand" "=w")
- (truncate:<V_narrow> (match_operand:VN 1 "register_operand" "")))]
+ (truncate:<V_narrow> (match_operand:VN 1 "register_operand" "w")))]
"TARGET_NEON"
- "vmovn.i<V_sz_elem>\t%0, %q1"
+ "vmovn.i<V_sz_elem>\t%P0, %q1"
[(set_attr "neon_type" "neon_shift_1")]
)
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH, ARM] Fix ICE (PR target/45805).
2010-09-29 17:21 [PATCH, ARM] Fix ICE (PR target/45805) Tejas Belagod
@ 2010-10-05 9:31 ` Richard Earnshaw
0 siblings, 0 replies; 2+ messages in thread
From: Richard Earnshaw @ 2010-10-05 9:31 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On Wed, 2010-09-29 at 10:47 +0100, Tejas Belagod wrote:
> Hi,
>
> This patch fixes bug PR target/45805. A missing constraint specifier in
> patterns for vmovl and vmovn was causing the compiler to ICE by
> matching memory operands instead of the intended register operands. A
> 'w' in the constraint specifier fixes the ICE. Also the instruction
> templates for vmovl, vmovn and vmull have been fixed by adding intended
> register specifiers.
>
> OK?
>
> --
> Tejas Belagod
> ARM.
>
> gcc/
>
> 2010-09-29 Tejas Belagod <tejas.belagod@arm.com>
>
> * config/arm/neon.md (neon_unpack<US>_<mode>): Add 'w' to
> constraint, add register specifier in instruction template.
> (neon_vec_pack_trunc_<mode>): Likewise.
> (neon_vec_<US>mult_<mode>): Add register specifier to
> instruction template.
OK
R.
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2010-10-05 9:31 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-09-29 17:21 [PATCH, ARM] Fix ICE (PR target/45805) Tejas Belagod
2010-10-05 9:31 ` Richard Earnshaw
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).