From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22096 invoked by alias); 19 Apr 2011 12:28:36 -0000 Received: (qmail 22078 invoked by uid 22791); 19 Apr 2011 12:28:35 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (94.185.240.25) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Tue, 19 Apr 2011 12:28:20 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 19 Apr 2011 13:28:17 +0100 Received: from [10.1.67.34] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Tue, 19 Apr 2011 13:28:15 +0100 Subject: Re: [Patch,AVR]: FIX ICE in optabs due to bad rotate expander. From: Richard Earnshaw To: Denis Chertykov Cc: Georg-Johann Lay , gcc-patches@gcc.gnu.org, Anatoly Sokolov , Eric Weddington In-Reply-To: References: <4DA6CB8E.1040707@gjlay.de> <4DA72CC6.5030001@gjlay.de> <4DA880F6.4070109@gjlay.de> <4DAC14F0.5070304@gjlay.de> <4DAD521B.9020501@gjlay.de> <4DAD61D9.6020209@gjlay.de> Date: Tue, 19 Apr 2011 13:15:00 -0000 Message-Id: <1303216094.17819.50.camel@e102346-lin.cambridge.arm.com> Mime-Version: 1.0 X-MC-Unique: 111041913281700701 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-04/txt/msg01523.txt.bz2 On Tue, 2011-04-19 at 15:17 +0400, Denis Chertykov wrote: > 2011/4/19 Georg-Johann Lay : > > Denis Chertykov schrieb: > >> 2011/4/19 Georg-Johann Lay : > >>> How can add, sub etc. be split? This would need an explicit > >>> representation of carry. > >> > >> Yes. > >> > >> Look at http://gcc.gnu.org/ml/gcc/2005-03/msg00871.html > > > > Just skimmed the conversation. I thought about making AVR ISA's > > effects on SREG explicit several times, but I always got stuck at some > > point. > > > > - It's not only about scheduling (which does not happen for avr) but > > also about moving instructions across jumps. > > > > - Many transformations would happen before reload, but at these stages > > the effect on SREG is not yet known in many cases. There is > > sophisticated instruction output for many patterns, and their impact > > on SREG/CC is not known before reload. > > > > - Making CC explicit would render many single_set insns to PARALLELs > > making the optimizers' live much harder or impossible. Imagine > > instructions that could be combined. Explicit CC would clutter up > > insns and combine won't try to transform the bulky patterns. > > > > - Backend would be much more complicated, harder to maintain and > > understand. Almost any insn would have to be changed. >=20 > Generally, I'm agree with you, the AVR port uses CC0 because of that. Thumb-1 support in the ARM compiler has similar flag-setting properties (ie most instructions set the condition codes). It doesn't use CC0. It works because it doesn't model the condition code register at all, but treats compare/branch sequences as indivisible operations. R.