* [PATCH 2/7] s390: Only use lhs zero_extract in word_mode
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (4 preceding siblings ...)
2012-08-10 2:32 ` [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-11-06 13:01 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 7/7] s390: Generate rnsbg Richard Henderson
` (2 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
This means that anything targeting extimm or z10 must therefore
imply zarch, which implies word_mode == DImode.
Then, now that *insv_z10 is no longer dependent on mode, let gas
do some arithmetic, rather than doing it in C and generating new rtl.
---
gcc/config/s390/s390.md | 45 ++++++++++++++++-----------------------------
1 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 76ec9c4..2677fb2 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3364,27 +3364,15 @@
FAIL;
})
-(define_insn "*insv<mode>_z10"
- [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
- (match_operand 1 "const_int_operand" "I")
- (match_operand 2 "const_int_operand" "I"))
- (match_operand:GPR 3 "nonimmediate_operand" "d"))
+(define_insn "*insv_z10"
+ [(set (zero_extract:DI
+ (match_operand:DI 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (match_operand:DI 3 "nonimmediate_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
- && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
- GET_MODE_BITSIZE (<MODE>mode)"
-{
- int start = INTVAL (operands[2]);
- int size = INTVAL (operands[1]);
- int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
-
- operands[2] = GEN_INT (offset + start); /* start bit position */
- operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
- operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
- start - size); /* left shift count */
-
- return "risbg\t%0,%3,%b2,%b1,%b4";
-}
+ "TARGET_Z10"
+ "risbg\t%0,%3,%2,%2+%1-1,64-%2-%1"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
@@ -3483,15 +3471,14 @@
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_E1")])
-; Update the right-most 32 bit of a DI, or the whole of a SI.
-(define_insn "*insv_l<mode>_reg_extimm"
- [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
- (const_int 32)
- (match_operand 1 "const_int_operand" "n"))
- (match_operand:P 2 "const_int_operand" "n"))]
- "TARGET_EXTIMM
- && BITS_PER_WORD - INTVAL (operands[1]) == 32"
- "iilf\t%0,%o2"
+; Update the right-most 32 bit of a DI.
+(define_insn "*insv_l_di_reg_extimm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 32)
+ (const_int 32))
+ (match_operand:DI 1 "const_int_operand" "n"))]
+ "TARGET_EXTIMM"
+ "iilf\t%0,%o1"
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_A1")])
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/7] s390: Implement extzv for z10
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-12-14 13:53 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg Richard Henderson
` (7 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
---
gcc/config/s390/predicates.md | 4 +++
gcc/config/s390/s390-protos.h | 1 +
gcc/config/s390/s390.c | 16 ++++++++++++
gcc/config/s390/s390.md | 55 +++++++++++++++++++++++++++++++++++------
4 files changed, 68 insertions(+), 8 deletions(-)
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index 333457d..e4632b9 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -101,6 +101,10 @@
return true;
})
+(define_predicate "nonzero_shift_count_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
+
;; Return true if OP a valid operand for the LARL instruction.
(define_predicate "larl_operand"
diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 79673d6..97c378f 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -110,5 +110,6 @@ extern bool s390_legitimate_address_without_index_p (rtx);
extern bool s390_decompose_shift_count (rtx, rtx *, HOST_WIDE_INT *);
extern int s390_branch_condition_mask (rtx);
extern int s390_compare_and_branch_condition_mask (rtx);
+extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);
#endif /* RTX_CODE */
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 4e22100..52138d7 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1308,6 +1308,22 @@ s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
return true;
}
+/* Check whether a rotate of ROTL followed by an AND of CONTIG is equivalent
+ to a shift followed by the AND. In particular, CONTIG should not overlap
+ the (rotated) bit 0/bit 63 gap. */
+
+bool
+s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
+{
+ int pos, len;
+ bool ok;
+
+ ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
+ gcc_assert (ok);
+
+ return (rotl <= pos || rotl >= pos + len + (64 - bitsize));
+}
+
/* Check whether we can (and want to) split a double-word
move in mode MODE from SRC to DST into two single-word
moves, moving the subword FIRST_SUBWORD first. */
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index b6e1535..ae004ac 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3298,15 +3298,25 @@
[(set_attr "op_type" "RS,RSY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+(define_insn "extzv"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (zero_extract:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ "risbg\t%0,%1,63-%3-%2,128+63,63-%3-%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn_and_split "*extzv<mode>"
+(define_insn_and_split "*pre_z10_extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
- (match_operand 2 "const_int_operand" "n")
+ (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
- "INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
+ "!TARGET_Z10"
"#"
"&& reload_completed"
[(parallel
@@ -3324,14 +3334,13 @@
operands[3] = GEN_INT (mask);
})
-(define_insn_and_split "*extv<mode>"
+(define_insn_and_split "*pre_z10_extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
- (match_operand 2 "const_int_operand" "n")
+ (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
- "INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
+ "!TARGET_Z10"
"#"
"&& reload_completed"
[(parallel
@@ -6034,6 +6043,36 @@
(clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
+;; These two are what combine generates for (ashift (zero_extract)).
+(define_insn "*extzv_<mode>_srl"
+ [(set (match_operand:DSI 0 "register_operand" "=d")
+ (and:DSI (lshiftrt:DSI
+ (match_operand:DSI 1 "register_operand" "d")
+ (match_operand:DSI 2 "nonzero_shift_count_operand" ""))
+ (match_operand:DSI 3 "contiguous_bitmask_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ /* Note that even for the SImode pattern, the rotate is always DImode. */
+ && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[2]),
+ INTVAL (operands[3]))"
+ "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*extzv_<mode>_sll"
+ [(set (match_operand:DSI 0 "register_operand" "=d")
+ (and:DSI (ashift:DSI
+ (match_operand:DSI 1 "register_operand" "d")
+ (match_operand:DSI 2 "nonzero_shift_count_operand" ""))
+ (match_operand:DSI 3 "contiguous_bitmask_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
+ INTVAL (operands[3]))"
+ "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
;
; andsi3 instruction pattern(s).
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
2012-08-10 2:32 ` [PATCH 5/7] s390: Implement extzv for z10 Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-12-14 13:58 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 3/7] s390: Use risbgz for AND Richard Henderson
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
---
gcc/config/s390/s390.md | 63 +++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 56 insertions(+), 7 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index ae004ac..d733062 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -384,6 +384,9 @@
;; the same template.
(define_code_iterator SHIFT [ashift lshiftrt])
+;; This iterator allow r[ox]sbg to be defined with the same template
+(define_code_iterator IXOR [ior xor])
+
;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_iterator ATOMIC_Z196 [and ior xor plus])
@@ -3402,15 +3405,61 @@
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
-; and op1 with a mask being 1 for the selected bits and 0 for the rest
-(define_insn "*insv<mode>_or_z10_noshift"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
- (match_operand:GPR 3 "nonimmediate_operand" "0")))
+(define_insn "*r<noxa>sbg_<mode>_noshift"
+ [(set (match_operand:DSI 0 "nonimmediate_operand" "=d")
+ (IXOR:DSI
+ (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "d")
+ (match_operand:DSI 2 "contiguous_bitmask_operand" ""))
+ (match_operand:DSI 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+ [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_di_rotl"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ (IXOR:DI
+ (and:DI
+ (rotate:DI
+ (match_operand:DI 1 "nonimmediate_operand" "d")
+ (match_operand:DI 3 "const_int_operand" ""))
+ (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+ (match_operand:DI 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
- "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+ "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
+ [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_<mode>_srl"
+ [(set (match_operand:DSI 0 "nonimmediate_operand" "=d")
+ (IXOR:DSI
+ (and:DSI
+ (lshiftrt:DSI
+ (match_operand:DSI 1 "nonimmediate_operand" "d")
+ (match_operand:DSI 3 "nonzero_shift_count_operand" ""))
+ (match_operand:DSI 2 "contiguous_bitmask_operand" ""))
+ (match_operand:DSI 4 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
+ INTVAL (operands[2]))"
+ "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
+ [(set_attr "op_type" "RIE")])
+
+(define_insn "*r<noxa>sbg_<mode>_sll"
+ [(set (match_operand:DSI 0 "nonimmediate_operand" "=d")
+ (IXOR:DSI
+ (and:DSI
+ (ashift:DSI
+ (match_operand:DSI 1 "nonimmediate_operand" "d")
+ (match_operand:DSI 3 "nonzero_shift_count_operand" ""))
+ (match_operand:DSI 2 "contiguous_bitmask_operand" ""))
+ (match_operand:DSI 4 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
+ INTVAL (operands[2]))"
+ "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (3 preceding siblings ...)
2012-08-10 2:32 ` [PATCH 4/7] s390: Add mode attribute for mode bitsize Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-11-06 12:52 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 2/7] s390: Only use lhs zero_extract in word_mode Richard Henderson
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
---
gcc/config/s390/constraints.md | 11 ++++-
gcc/config/s390/predicates.md | 6 +++
gcc/config/s390/s390.c | 92 +++++++++++++++++++++++++++-------------
gcc/config/s390/s390.md | 48 +++++----------------
4 files changed, 90 insertions(+), 67 deletions(-)
diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md
index 8564b66..9d416ad 100644
--- a/gcc/config/s390/constraints.md
+++ b/gcc/config/s390/constraints.md
@@ -45,6 +45,8 @@
;; H,Q: mode of the part
;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F - all bits set)
+;; --
+;; xx[DS]q satisfies s390_contiguous_bitmask_p for DImode or SImode
;;
;; The constraint matches if the specified part of a constant
;; has a value different from its other parts. If the letter x
@@ -330,8 +332,15 @@
(and (match_code "const_int")
(match_test "s390_N_constraint_str (\"xQH0\", ival)")))
+(define_constraint "NxxDq"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_contiguous_bitmask_p (ival, 64, NULL, NULL)")))
-
+(define_constraint "NxxSq"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_contiguous_bitmask_p (ival, 32, NULL, NULL)")))
;;
;; Double-letter constraints starting with O follow.
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index 9d619fb..333457d 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -154,6 +154,12 @@
return false;
})
+(define_predicate "contiguous_bitmask_operand"
+ (match_code "const_int")
+{
+ return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
+})
+
;; operators --------------------------------------------------------------
;; Return nonzero if OP is a valid comparison operator
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index d67c0eb..4e22100 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -5286,28 +5286,35 @@ print_operand_address (FILE *file, rtx addr)
'C': print opcode suffix for branch condition.
'D': print opcode suffix for inverse branch condition.
'E': print opcode suffix for branch on index instruction.
- 'J': print tls_load/tls_gdcall/tls_ldcall suffix
'G': print the size of the operand in bytes.
+ 'J': print tls_load/tls_gdcall/tls_ldcall suffix
+ 'M': print the second word of a TImode operand.
+ 'N': print the second word of a DImode operand.
'O': print only the displacement of a memory reference.
'R': print only the base register of a memory reference.
'S': print S-type memory reference (base+displacement).
- 'N': print the second word of a DImode operand.
- 'M': print the second word of a TImode operand.
'Y': print shift count operand.
'b': print integer X as if it's an unsigned byte.
'c': print integer X as if it's an signed byte.
- 'x': print integer X as if it's an unsigned halfword.
+ 'e': "end" of DImode contiguous bitmask X.
+ 'f': "end" of SImode contiguous bitmask X.
'h': print integer X as if it's a signed halfword.
'i': print the first nonzero HImode part of X.
'j': print the first HImode part unequal to -1 of X.
'k': print the first nonzero SImode part of X.
'm': print the first SImode part unequal to -1 of X.
- 'o': print integer X as if it's an unsigned 32bit word. */
+ 'o': print integer X as if it's an unsigned 32bit word.
+ 's': "start" of DImode contiguous bitmask X.
+ 't': "start" of SImode contiguous bitmask X.
+ 'x': print integer X as if it's an unsigned halfword.
+*/
void
print_operand (FILE *file, rtx x, int code)
{
+ HOST_WIDE_INT ival;
+
switch (code)
{
case 'C':
@@ -5486,30 +5493,57 @@ print_operand (FILE *file, rtx x, int code)
break;
case CONST_INT:
- if (code == 'b')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
- else if (code == 'c')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
- else if (code == 'x')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
- else if (code == 'h')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
- else if (code == 'i')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- s390_extract_part (x, HImode, 0));
- else if (code == 'j')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- s390_extract_part (x, HImode, -1));
- else if (code == 'k')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- s390_extract_part (x, SImode, 0));
- else if (code == 'm')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- s390_extract_part (x, SImode, -1));
- else if (code == 'o')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
- else
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
+ ival = INTVAL (x);
+ switch (code)
+ {
+ case 0:
+ break;
+ case 'b':
+ ival &= 0xff;
+ break;
+ case 'c':
+ ival = ((ival & 0xff) ^ 0x80) - 0x80;
+ break;
+ case 'x':
+ ival &= 0xffff;
+ break;
+ case 'h':
+ ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
+ break;
+ case 'i':
+ ival = s390_extract_part (x, HImode, 0);
+ break;
+ case 'j':
+ ival = s390_extract_part (x, HImode, -1);
+ break;
+ case 'k':
+ ival = s390_extract_part (x, SImode, 0);
+ break;
+ case 'm':
+ ival = s390_extract_part (x, SImode, -1);
+ break;
+ case 'o':
+ ival &= 0xffffffff;
+ break;
+ case 'e': case 'f':
+ case 's': case 't':
+ {
+ int pos, len;
+ bool ok;
+
+ len = (code == 's' || code == 'e' ? 64 : 32);
+ ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
+ gcc_assert (ok);
+ if (code == 's' || code == 't')
+ ival = 64 - pos - len;
+ else
+ ival = 64 - 1 - pos;
+ }
+ break;
+ default:
+ output_operand_lossage ("invalid constant for output modifier '%c'", code);
+ }
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
break;
case CONST_DOUBLE:
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index b3d096c..76ec9c4 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -518,6 +518,10 @@
;; Maximum unsigned integer that fits in MODE.
(define_mode_attr max_uint [(HI "65535") (QI "255")])
+;; Start and end field computations for RISBG et al.
+(define_mode_attr bfstart [(DI "s") (SI "t")])
+(define_mode_attr bfend [(DI "e") (SI "f")])
+
;;
;;- Compare instructions.
;;
@@ -3389,28 +3393,12 @@
(define_insn "*insv<mode>_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
- (match_operand 2 "const_int_operand" "n"))
+ (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
- (match_operand 4 "const_int_operand" "n"))))
+ (match_operand:GPR 4 "const_int_operand" ""))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
- && s390_contiguous_bitmask_p (INTVAL (operands[2]),
- GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
- && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
-
-{
- int start;
- int size;
-
- s390_contiguous_bitmask_p (INTVAL (operands[2]),
- GET_MODE_BITSIZE (<MODE>mode), &start, &size);
-
- operands[5] = GEN_INT (64 - start - size); /* start bit position */
- operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
- operands[7] = const0_rtx; /* left shift count */
-
- return "risbg\t%0,%1,%b5,%b6,%b7";
-}
+ "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
@@ -3418,25 +3406,11 @@
(define_insn "*insv<mode>_or_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
- (match_operand 2 "const_int_operand" "n"))
+ (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
(match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
- && s390_contiguous_bitmask_p (INTVAL (operands[2]),
- GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
-{
- int start;
- int size;
-
- s390_contiguous_bitmask_p (INTVAL (operands[2]),
- GET_MODE_BITSIZE (<MODE>mode), &start, &size);
-
- operands[4] = GEN_INT (64 - start - size); /* start bit position */
- operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
- operands[6] = const0_rtx; /* left shift count */
-
- return "rosbg\t%0,%1,%b4,%b5,%b6";
-}
+ "TARGET_Z10"
+ "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/7] s390: Use risbgz for AND.
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
2012-08-10 2:32 ` [PATCH 5/7] s390: Implement extzv for z10 Richard Henderson
2012-08-10 2:32 ` [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-11-06 14:29 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 4/7] s390: Add mode attribute for mode bitsize Richard Henderson
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
---
gcc/config/s390/s390.md | 107 +++++++++++++++++++++++++++--------------------
1 files changed, 62 insertions(+), 45 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 2677fb2..6474023 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -5946,44 +5946,50 @@
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
- (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d")
+ (compare
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
+ (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
(and:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
+ "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
- ng\t%0,%2"
- [(set_attr "op_type" "RRE,RRF,RXY")
- (set_attr "cpu_facility" "*,z196,*")
- (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
+ ng\t%0,%2
+ risbg\t%0,%1,%s2,128+%e2,0"
+ [(set_attr "op_type" "RRE,RRF,RXY,RIE")
+ (set_attr "cpu_facility" "*,z196,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
- (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
+ (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d, d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
+ (clobber (match_scratch:DI 0 "=d,d, d, d"))]
+ "TARGET_ZARCH
+ && s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
- ng\t%0,%2"
- [(set_attr "op_type" "RRE,RRF,RXY")
- (set_attr "cpu_facility" "*,z196,*")
- (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
+ ng\t%0,%2
+ risbg\t%0,%1,%s2,128+%e2,0"
+ [(set_attr "op_type" "RRE,RRF,RXY,RIE")
+ (set_attr "cpu_facility" "*,z196,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
- (and:DI (match_operand:DI 1 "nonimmediate_operand"
- "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
- (match_operand:DI 2 "general_operand"
- "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
+ "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
+ (and:DI
+ (match_operand:DI 1 "nonimmediate_operand"
+ "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
+ (match_operand:DI 2 "general_operand"
+ "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
@@ -5998,10 +6004,11 @@
ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2
+ risbg\t%0,%1,%s2,128+%e2,0
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
@@ -6013,6 +6020,7 @@
z10_super_E1,
*,
z10_super_E1,
+ z10_super_E1,
*,
*")])
@@ -6033,10 +6041,12 @@
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
+ (compare
+ (and:SI
+ (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
@@ -6044,17 +6054,21 @@
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
- ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
+ ny\t%0,%2
+ risbg\t%0,%1,%t2,128+%f2,0"
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
+ (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
+ (compare
+ (and:SI
+ (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
+ (const_int 0)))
+ (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
@@ -6063,19 +6077,20 @@
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
- ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ ny\t%0,%2
+ risbg\t%0,%1,%t2,128+%f2,0"
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
+ (set_attr "cpu_facility" "*,*,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
- z10_super_E1,z10_super_E1")])
+ z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d,d, d, d, d,d,d,d,d, AQ,Q")
+ "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
- "%d,o, 0, 0, 0,0,d,0,0, 0,0")
+ "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
(match_operand:SI 2 "general_operand"
- " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
+ " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
@@ -6088,10 +6103,11 @@
nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
+ risbg\t%0,%1,%t2,128+%f2,0
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
@@ -6101,6 +6117,7 @@
*,
z10_super_E1,
z10_super_E1,
+ z10_super_E1,
*,
*")])
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 7/7] s390: Generate rnsbg
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (5 preceding siblings ...)
2012-08-10 2:32 ` [PATCH 2/7] s390: Only use lhs zero_extract in word_mode Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-12-14 14:02 ` Andreas Krebbel
2012-08-13 17:07 ` [PATCH 0/7] s390 improvements with r[ioxn]sbg Ulrich Weigand
2012-10-09 8:43 ` Andreas Krebbel
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
---
gcc/config/s390/s390.md | 55 +++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index d733062..182e7b1 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3462,6 +3462,61 @@
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
+;; These two are generated by combine for s.bf &= val.
+;; ??? For bitfields smaller than 32-bits, we wind up with SImode
+;; shifts and ands, which results in some truly awful patterns
+;; including subregs of operations. Rather unnecessisarily, IMO.
+;; Instead of
+;;
+;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
+;; (const_int 24 [0x18])
+;; (const_int 0 [0]))
+;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
+;; (const_int 40 [0x28])) 4)
+;; (reg:SI 4 %r4 [ y+4 ])) 0))
+;;
+;; we should instead generate
+;;
+;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
+;; (const_int 24 [0x18])
+;; (const_int 0 [0]))
+;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
+;; (const_int 40 [0x28]))
+;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
+;;
+;; by noticing that we can push down the outer paradoxical subreg
+;; into the operation.
+
+(define_insn "*insv_rnsbg_noshift"
+ [(set (zero_extract:DI
+ (match_operand:DI 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (and:DI
+ (match_dup 0)
+ (match_operand:DI 3 "nonimmediate_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
+ "rnsbg\t%0,%3,%2,63,0"
+ [(set_attr "op_type" "RIE")])
+
+(define_insn "*insv_rnsbg_srl"
+ [(set (zero_extract:DI
+ (match_operand:DI 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (and:DI
+ (lshiftrt:DI
+ (match_dup 0)
+ (match_operand 3 "const_int_operand" ""))
+ (match_operand:DI 4 "nonimmediate_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
+ "rnsbg\t%0,%4,%2,%2+%1-1,64-%2,%1"
+ [(set_attr "op_type" "RIE")])
+
(define_insn "*insv<mode>_mem_reg"
[(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/7] s390 improvements with r[ioxn]sbg
@ 2012-08-10 2:32 Richard Henderson
2012-08-10 2:32 ` [PATCH 5/7] s390: Implement extzv for z10 Richard Henderson
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
Only "tested" visually, by examining assembly diffs of the
runtime libraries between successive patches. All told it
would appear to be some remarkable code size improvements.
Please test.
r~
Richard Henderson (7):
s390: Constraints, predicates, and op letters for contiguous bitmasks
s390: Only use lhs zero_extract in word_mode
s390: Use risbgz for AND.
s390: Add mode attribute for mode bitsize
s390: Implement extzv for z10
s390: Generate rxsbg, and shifted forms of rosbg
s390: Generate rnsbg
gcc/config/s390/constraints.md | 11 +-
gcc/config/s390/predicates.md | 10 +
gcc/config/s390/s390-protos.h | 1 +
gcc/config/s390/s390.c | 108 ++++++++---
gcc/config/s390/s390.md | 385 ++++++++++++++++++++++++++--------------
5 files changed, 353 insertions(+), 162 deletions(-)
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/7] s390: Add mode attribute for mode bitsize
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (2 preceding siblings ...)
2012-08-10 2:32 ` [PATCH 3/7] s390: Use risbgz for AND Richard Henderson
@ 2012-08-10 2:32 ` Richard Henderson
2012-12-14 13:48 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks Richard Henderson
` (4 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Richard Henderson @ 2012-08-10 2:32 UTC (permalink / raw)
To: uweigand; +Cc: gcc-patches
Constant fold, and less typing than, GET_MODE_BITSIZE with
another mode substitution.
---
gcc/config/s390/s390.md | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 6474023..b6e1535 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -522,6 +522,9 @@
(define_mode_attr bfstart [(DI "s") (SI "t")])
(define_mode_attr bfend [(DI "e") (SI "f")])
+;; In place of GET_MODE_BITSIZE (<MODE>mode)
+(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
+
;;
;;- Compare instructions.
;;
@@ -3317,7 +3320,7 @@
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
- operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
+ operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask);
})
@@ -3344,7 +3347,7 @@
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
- operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
+ operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask);
})
@@ -3532,8 +3535,7 @@
}
else if (!TARGET_EXTIMM)
{
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
- GET_MODE_BITSIZE (<HQI:MODE>mode));
+ rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
@@ -3635,8 +3637,7 @@
{
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GET_MODE_SIZE (QImode));
- operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
- - GET_MODE_BITSIZE (QImode));
+ operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
})
;
@@ -3747,8 +3748,7 @@
}
else if (!TARGET_EXTIMM)
{
- rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
- GET_MODE_BITSIZE(<MODE>mode));
+ rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
@@ -3765,7 +3765,7 @@
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1],
- GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
+ GEN_INT ((1 << <HQI:bitsize>) - 1)));
DONE;
}
})
@@ -3958,8 +3958,8 @@
REAL_VALUE_TYPE cmp, sub;
operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
- real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
- real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
+ real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
+ real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
@@ -4676,7 +4676,7 @@
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
|| CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
- && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
+ && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (<bitsize> - 1))"
"@
a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2
--
1.7.7.6
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/7] s390 improvements with r[ioxn]sbg
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (6 preceding siblings ...)
2012-08-10 2:32 ` [PATCH 7/7] s390: Generate rnsbg Richard Henderson
@ 2012-08-13 17:07 ` Ulrich Weigand
2012-08-13 17:24 ` Richard Henderson
2012-10-09 8:43 ` Andreas Krebbel
8 siblings, 1 reply; 18+ messages in thread
From: Ulrich Weigand @ 2012-08-13 17:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches
Richard Henderson wrote:
> Only "tested" visually, by examining assembly diffs of the
> runtime libraries between successive patches. All told it
> would appear to be some remarkable code size improvements.
Thanks for having a look at this!
> Please test.
Unfortunately GCC crashes during bootstrap, probably because on
of the issues below.
A couple of comments to the patches:
> s390: Constraints, predicates, and op letters for contiguous bitmasks
> s390: Only use lhs zero_extract in word_mode
> s390: Use risbgz for AND.
> s390: Add mode attribute for mode bitsize
These look all good to me.
> s390: Implement extzv for z10
> +/* Check whether a rotate of ROTL followed by an AND of CONTIG is equivalent
> + to a shift followed by the AND. In particular, CONTIG should not overlap
> + the (rotated) bit 0/bit 63 gap. */
> +
> +bool
> +s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
> +{
> + int pos, len;
> + bool ok;
> +
> + ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
> + gcc_assert (ok);
> +
> + return (rotl <= pos || rotl >= pos + len + (64 - bitsize));
> +}
I don't quite see how this can work correctly for both left and right shifts.
E.g. for bitsize == 64, rotl == 1, contig == 1, a left shift by 1 followed
by the AND is always zero, and certainly not equal to the rotate. But the
routine would return true. (Note that the same routine would be called for
a *right* shift by 63, in which case the "true" result is actually correct.)
> +(define_insn "extzv"
> + [(set (match_operand:DI 0 "register_operand" "=d")
> + (zero_extract:DI
> + (match_operand:DI 1 "register_operand" "d")
> + (match_operand 2 "const_int_operand" "")
> + (match_operand 3 "const_int_operand" "")))
> + (clobber (reg:CC CC_REGNUM))]
> + "TARGET_Z10"
> + "risbg\t%0,%1,63-%3-%2,128+63,63-%3-%2"
This doesn't look right for bits-big-endian order. Shouldn't we have a
rotate count of %3+%2, and a start bit position of 64-%2 ?
> -(define_insn_and_split "*extv<mode>"
> +(define_insn_and_split "*pre_z10_extv<mode>"
> [(set (match_operand:GPR 0 "register_operand" "=d")
> (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
> - (match_operand 2 "const_int_operand" "n")
> + (match_operand 2 "nonzero_shift_count_operand" "")
> (const_int 0)))
> (clobber (reg:CC CC_REGNUM))]
> - "INTVAL (operands[2]) > 0
> - && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
> + "!TARGET_Z10"
> "#"
> "&& reload_completed"
Why disable this for pre-z10?
> +(define_insn "*extzv_<mode>_srl"
> + [(set (match_operand:DSI 0 "register_operand" "=d")
> + (and:DSI (lshiftrt:DSI
> + (match_operand:DSI 1 "register_operand" "d")
> + (match_operand:DSI 2 "nonzero_shift_count_operand" ""))
> + (match_operand:DSI 3 "contiguous_bitmask_operand" "")))
> + (clobber (reg:CC CC_REGNUM))]
> + "TARGET_Z10
While those are equivalent (given that TARGET_Z10 implies TARGET_ZARCH),
it would seem more in line with many other patterns to use GPR instead of DSI.
> s390: Generate rxsbg, and shifted forms of rosbg
This looks OK.
> s390: Generate rnsbg
> +(define_insn "*insv_rnsbg_srl"
> + [(set (zero_extract:DI
> + (match_operand:DI 0 "nonimmediate_operand" "+d")
> + (match_operand 1 "const_int_operand" "")
> + (match_operand 2 "const_int_operand" ""))
> + (and:DI
> + (lshiftrt:DI
> + (match_dup 0)
> + (match_operand 3 "const_int_operand" ""))
> + (match_operand:DI 4 "nonimmediate_operand" "d")))
> + (clobber (reg:CC CC_REGNUM))]
> + "TARGET_Z10
> + && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
> + "rnsbg\t%0,%4,%2,%2+%1-1,64-%2,%1"
I guess the last "," is supposed to be a "-". (Then we might
as well use %3 instead of 64-%2-%1.)
Bye,
Ulrich
--
Dr. Ulrich Weigand
GNU Toolchain for Linux on System z and Cell BE
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/7] s390 improvements with r[ioxn]sbg
2012-08-13 17:07 ` [PATCH 0/7] s390 improvements with r[ioxn]sbg Ulrich Weigand
@ 2012-08-13 17:24 ` Richard Henderson
0 siblings, 0 replies; 18+ messages in thread
From: Richard Henderson @ 2012-08-13 17:24 UTC (permalink / raw)
To: Ulrich Weigand; +Cc: gcc-patches
On 08/13/2012 10:07 AM, Ulrich Weigand wrote:
>> +/* Check whether a rotate of ROTL followed by an AND of CONTIG is equivalent
>> + to a shift followed by the AND. In particular, CONTIG should not overlap
>> + the (rotated) bit 0/bit 63 gap. */
>> +
>> +bool
>> +s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
>> +{
>> + int pos, len;
>> + bool ok;
>> +
>> + ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
>> + gcc_assert (ok);
>> +
>> + return (rotl <= pos || rotl >= pos + len + (64 - bitsize));
>> +}
>
> I don't quite see how this can work correctly for both left and right shifts.
> E.g. for bitsize == 64, rotl == 1, contig == 1, a left shift by 1 followed
> by the AND is always zero, and certainly not equal to the rotate. But the
> routine would return true. (Note that the same routine would be called for
> a *right* shift by 63, in which case the "true" result is actually correct.)
Absolutely correct; I hadn't considered that.
>> +(define_insn "extzv"
>> + [(set (match_operand:DI 0 "register_operand" "=d")
>> + (zero_extract:DI
>> + (match_operand:DI 1 "register_operand" "d")
>> + (match_operand 2 "const_int_operand" "")
>> + (match_operand 3 "const_int_operand" "")))
>> + (clobber (reg:CC CC_REGNUM))]
>> + "TARGET_Z10"
>> + "risbg\t%0,%1,63-%3-%2,128+63,63-%3-%2"
>
> This doesn't look right for bits-big-endian order. Shouldn't we have a
> rotate count of %3+%2, and a start bit position of 64-%2 ?
Yes.
>> -(define_insn_and_split "*extv<mode>"
>> +(define_insn_and_split "*pre_z10_extv<mode>"
>> [(set (match_operand:GPR 0 "register_operand" "=d")
>> (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
>> - (match_operand 2 "const_int_operand" "n")
>> + (match_operand 2 "nonzero_shift_count_operand" "")
>> (const_int 0)))
>> (clobber (reg:CC CC_REGNUM))]
>> - "INTVAL (operands[2]) > 0
>> - && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
>> + "!TARGET_Z10"
>> "#"
>> "&& reload_completed"
>
> Why disable this for pre-z10?
I blatantly assumed that L+RISBGZ was better than ICM+SRL. I probably
shouldn't have also disabled the sign_extract version as well.
> While those are equivalent (given that TARGET_Z10 implies TARGET_ZARCH),
> it would seem more in line with many other patterns to use GPR instead of DSI.
Ok.
>> + && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
>> + "rnsbg\t%0,%4,%2,%2+%1-1,64-%2,%1"
>
> I guess the last "," is supposed to be a "-". (Then we might
> as well use %3 instead of 64-%2-%1.)
Good catch.
r~
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/7] s390 improvements with r[ioxn]sbg
2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
` (7 preceding siblings ...)
2012-08-13 17:07 ` [PATCH 0/7] s390 improvements with r[ioxn]sbg Ulrich Weigand
@ 2012-10-09 8:43 ` Andreas Krebbel
8 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-10-09 8:43 UTC (permalink / raw)
To: Richard Henderson; +Cc: uweigand, gcc-patches
On 10/08/12 04:31, Richard Henderson wrote:
> Only "tested" visually, by examining assembly diffs of the
> runtime libraries between successive patches. All told it
> would appear to be some remarkable code size improvements.
>
> Please test.
Thanks a lot for looking into this! I'll test the patches and try to fix the remaining issues.
Bye,
-Andreas-
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks
2012-08-10 2:32 ` [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks Richard Henderson
@ 2012-11-06 12:52 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-11-06 12:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches, uweigand
Hi,
thanks for your patch. I've refreshed it to the latest revision and
have added patterns for risbgn (risbg without clobbering CC) which has
been added with zEC12.
I've tested the patch on s390x with -march=z196. I think it is safe
for EC12 as well. However I'll run some tests there later on.
Feel free to apply.
Bye,
-Andreas-
gcc/config/s390/constraints.md | 11 ++!!
gcc/config/s390/predicates.md | 6 ++
gcc/config/s390/s390.c | 92 ++-!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
gcc/config/s390/s390.md | 74 +-!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
4 files changed, 21 insertions(+), 5 deletions(-), 157 modifications(!)
Index: gcc/config/s390/constraints.md
===================================================================
*** gcc/config/s390/constraints.md.orig
--- gcc/config/s390/constraints.md
***************
*** 45,50 ****
--- 45,52 ----
;; H,Q: mode of the part
;; D,S,H: mode of the containing operand
;; 0,F: value of the other parts (F - all bits set)
+ ;; --
+ ;; xx[DS]q satisfies s390_contiguous_bitmask_p for DImode or SImode
;;
;; The constraint matches if the specified part of a constant
;; has a value different from its other parts. If the letter x
***************
*** 330,337 ****
(and (match_code "const_int")
(match_test "s390_N_constraint_str (\"xQH0\", ival)")))
!
;;
;; Double-letter constraints starting with O follow.
--- 332,346 ----
(and (match_code "const_int")
(match_test "s390_N_constraint_str (\"xQH0\", ival)")))
+ (define_constraint "NxxDq"
+ "@internal"
+ (and (match_code "const_int")
+ (match_test "s390_contiguous_bitmask_p (ival, 64, NULL, NULL)")))
! (define_constraint "NxxSq"
! "@internal"
! (and (match_code "const_int")
! (match_test "s390_contiguous_bitmask_p (ival, 32, NULL, NULL)")))
;;
;; Double-letter constraints starting with O follow.
Index: gcc/config/s390/predicates.md
===================================================================
*** gcc/config/s390/predicates.md.orig
--- gcc/config/s390/predicates.md
***************
*** 154,159 ****
--- 154,165 ----
return false;
})
+ (define_predicate "contiguous_bitmask_operand"
+ (match_code "const_int")
+ {
+ return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
+ })
+
;; operators --------------------------------------------------------------
;; Return nonzero if OP is a valid comparison operator
Index: gcc/config/s390/s390.c
===================================================================
*** gcc/config/s390/s390.c.orig
--- gcc/config/s390/s390.c
*************** print_operand_address (FILE *file, rtx a
*** 5361,5388 ****
'C': print opcode suffix for branch condition.
'D': print opcode suffix for inverse branch condition.
'E': print opcode suffix for branch on index instruction.
- 'J': print tls_load/tls_gdcall/tls_ldcall suffix
'G': print the size of the operand in bytes.
'O': print only the displacement of a memory reference.
'R': print only the base register of a memory reference.
'S': print S-type memory reference (base+displacement).
- 'N': print the second word of a DImode operand.
- 'M': print the second word of a TImode operand.
'Y': print shift count operand.
'b': print integer X as if it's an unsigned byte.
'c': print integer X as if it's an signed byte.
! 'x': print integer X as if it's an unsigned halfword.
'h': print integer X as if it's a signed halfword.
'i': print the first nonzero HImode part of X.
'j': print the first HImode part unequal to -1 of X.
'k': print the first nonzero SImode part of X.
'm': print the first SImode part unequal to -1 of X.
! 'o': print integer X as if it's an unsigned 32bit word. */
void
print_operand (FILE *file, rtx x, int code)
{
switch (code)
{
case 'C':
--- 5361,5395 ----
'C': print opcode suffix for branch condition.
'D': print opcode suffix for inverse branch condition.
'E': print opcode suffix for branch on index instruction.
'G': print the size of the operand in bytes.
+ 'J': print tls_load/tls_gdcall/tls_ldcall suffix
+ 'M': print the second word of a TImode operand.
+ 'N': print the second word of a DImode operand.
'O': print only the displacement of a memory reference.
'R': print only the base register of a memory reference.
'S': print S-type memory reference (base+displacement).
'Y': print shift count operand.
'b': print integer X as if it's an unsigned byte.
'c': print integer X as if it's an signed byte.
! 'e': "end" of DImode contiguous bitmask X.
! 'f': "end" of SImode contiguous bitmask X.
'h': print integer X as if it's a signed halfword.
'i': print the first nonzero HImode part of X.
'j': print the first HImode part unequal to -1 of X.
'k': print the first nonzero SImode part of X.
'm': print the first SImode part unequal to -1 of X.
! 'o': print integer X as if it's an unsigned 32bit word.
! 's': "start" of DImode contiguous bitmask X.
! 't': "start" of SImode contiguous bitmask X.
! 'x': print integer X as if it's an unsigned halfword.
! */
void
print_operand (FILE *file, rtx x, int code)
{
+ HOST_WIDE_INT ival;
+
switch (code)
{
case 'C':
*************** print_operand (FILE *file, rtx x, int co
*** 5561,5590 ****
break;
case CONST_INT:
! if (code == 'b')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
! else if (code == 'c')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
! else if (code == 'x')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
! else if (code == 'h')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
! else if (code == 'i')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC,
! s390_extract_part (x, HImode, 0));
! else if (code == 'j')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC,
! s390_extract_part (x, HImode, -1));
! else if (code == 'k')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC,
! s390_extract_part (x, SImode, 0));
! else if (code == 'm')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC,
! s390_extract_part (x, SImode, -1));
! else if (code == 'o')
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
! else
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
break;
case CONST_DOUBLE:
--- 5568,5624 ----
break;
case CONST_INT:
! ival = INTVAL (x);
! switch (code)
! {
! case 0:
! break;
! case 'b':
! ival &= 0xff;
! break;
! case 'c':
! ival = ((ival & 0xff) ^ 0x80) - 0x80;
! break;
! case 'x':
! ival &= 0xffff;
! break;
! case 'h':
! ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
! break;
! case 'i':
! ival = s390_extract_part (x, HImode, 0);
! break;
! case 'j':
! ival = s390_extract_part (x, HImode, -1);
! break;
! case 'k':
! ival = s390_extract_part (x, SImode, 0);
! break;
! case 'm':
! ival = s390_extract_part (x, SImode, -1);
! break;
! case 'o':
! ival &= 0xffffffff;
! break;
! case 'e': case 'f':
! case 's': case 't':
! {
! int pos, len;
! bool ok;
!
! len = (code == 's' || code == 'e' ? 64 : 32);
! ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
! gcc_assert (ok);
! if (code == 's' || code == 't')
! ival = 64 - pos - len;
! else
! ival = 64 - 1 - pos;
! }
! break;
! default:
! output_operand_lossage ("invalid constant for output modifier '%c'", code);
! }
! fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
break;
case CONST_DOUBLE:
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 527,532 ****
--- 527,536 ----
;; Maximum unsigned integer that fits in MODE.
(define_mode_attr max_uint [(HI "65535") (QI "255")])
+ ;; Start and end field computations for RISBG et al.
+ (define_mode_attr bfstart [(DI "s") (SI "t")])
+ (define_mode_attr bfend [(DI "e") (SI "f")])
+
;;
;;- Compare instructions.
;;
***************
*** 3420,3475 ****
(define_insn "*insv<mode>_zEC12_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand 2 "const_int_operand" "n"))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
! (match_operand 4 "const_int_operand" "n"))))]
! "TARGET_ZEC12
! && s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
! && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
!
! {
! int start;
! int size;
!
! s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), &start, &size);
!
! operands[5] = GEN_INT (64 - start - size); /* start bit position */
! operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
! operands[7] = const0_rtx; /* left shift count */
!
! return "risbgn\t%0,%1,%b5,%b6,%b7";
! }
[(set_attr "op_type" "RIE")])
- ; and op1 with a mask being 1 for the selected bits and 0 for the rest
- ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
(define_insn "*insv<mode>_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand 2 "const_int_operand" "n"))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
! (match_operand 4 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
! && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
!
! {
! int start;
! int size;
!
! s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), &start, &size);
!
! operands[5] = GEN_INT (64 - start - size); /* start bit position */
! operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
! operands[7] = const0_rtx; /* left shift count */
!
! return "risbg\t%0,%1,%b5,%b6,%b7";
! }
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
--- 3424,3445 ----
(define_insn "*insv<mode>_zEC12_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
! (match_operand:GPR 4 "const_int_operand" ""))))]
! "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
! "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
(and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
! (match_operand:GPR 4 "const_int_operand" ""))))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
! "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
***************
*** 3477,3501 ****
(define_insn "*insv<mode>_or_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand 2 "const_int_operand" "n"))
(match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
! {
! int start;
! int size;
!
! s390_contiguous_bitmask_p (INTVAL (operands[2]),
! GET_MODE_BITSIZE (<MODE>mode), &start, &size);
!
! operands[4] = GEN_INT (64 - start - size); /* start bit position */
! operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
! operands[6] = const0_rtx; /* left shift count */
!
! return "rosbg\t%0,%1,%b4,%b5,%b6";
! }
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
--- 3447,3457 ----
(define_insn "*insv<mode>_or_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
(match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10"
! "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/7] s390: Only use lhs zero_extract in word_mode
2012-08-10 2:32 ` [PATCH 2/7] s390: Only use lhs zero_extract in word_mode Richard Henderson
@ 2012-11-06 13:01 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-11-06 13:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches, uweigand
Hi,
I had to remove the insv pattern changes from that patch. I
understand that you simplified the patterns since the generic RTL
expander only generates word mode zero extracts. However, we still
need the SImode variant for atomic operations so we cannot remove it.
The insv_z10 definition can still be simplified after adding the
bitsize mode attribute with one of your later patches so that change
will be moved to a later patch.
No regressions with that patch on s390x with -march=z196.
Feel free to apply.
Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 17 !!!!!!!!!!!!!!!!!
1 file changed, 17 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 3525,3539 ****
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_E1")])
! ; Update the right-most 32 bit of a DI, or the whole of a SI.
! (define_insn "*insv_l<mode>_reg_extimm"
! [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
! (const_int 32)
! (match_operand 1 "const_int_operand" "n"))
! (match_operand:P 2 "const_int_operand" "n"))]
! "TARGET_EXTIMM
! && BITS_PER_WORD - INTVAL (operands[1]) == 32"
! "iilf\t%0,%o2"
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_A1")])
--- 3525,3538 ----
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_E1")])
! ; Update the right-most 32 bit of a DI.
! (define_insn "*insv_l_di_reg_extimm"
! [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
! (const_int 32)
! (const_int 32))
! (match_operand:DI 1 "const_int_operand" "n"))]
! "TARGET_EXTIMM"
! "iilf\t%0,%o1"
[(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_A1")])
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/7] s390: Use risbgz for AND.
2012-08-10 2:32 ` [PATCH 3/7] s390: Use risbgz for AND Richard Henderson
@ 2012-11-06 14:29 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-11-06 14:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches, uweigand
I didn't do any changes to that one. So it is only a refresh to latest
GCC head.
Bootstrapped on s390x with -march=z196. No regressions.
Feel free to apply.
Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 109 +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 4 insertions(+), 105 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 6000,6043 ****
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
! (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
! (match_operand:DI 2 "general_operand" " d,d,RT"))
! (const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d, d")
(and:DI (match_dup 1) (match_dup 2)))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2"
! [(set_attr "op_type" "RRE,RRF,RXY")
! (set_attr "cpu_facility" "*,z196,*")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
! (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
! (match_operand:DI 2 "general_operand" " d,d,RT"))
! (const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d, d"))]
! "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2"
! [(set_attr "op_type" "RRE,RRF,RXY")
! (set_attr "cpu_facility" "*,z196,*")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
! (and:DI (match_operand:DI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
! (match_operand:DI 2 "general_operand"
! "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
--- 6000,6049 ----
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
! (compare
! (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
! (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
! (const_int 0)))
! (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
(and:DI (match_dup 1) (match_dup 2)))]
! "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2
! risbg\t%0,%1,%s2,128+%e2,0"
! [(set_attr "op_type" "RRE,RRF,RXY,RIE")
! (set_attr "cpu_facility" "*,z196,*,z10")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
! (compare
! (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
! (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
! (const_int 0)))
! (clobber (match_scratch:DI 0 "=d,d, d, d"))]
! "TARGET_ZARCH
! && s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
ngrk\t%0,%1,%2
! ng\t%0,%2
! risbg\t%0,%1,%s2,128+%e2,0"
! [(set_attr "op_type" "RRE,RRF,RXY,RIE")
! (set_attr "cpu_facility" "*,z196,*,z10")
! (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
! "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
! (and:DI
! (match_operand:DI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
! (match_operand:DI 2 "general_operand"
! "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
***************
*** 6052,6061 ****
ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
--- 6058,6068 ----
ngr\t%0,%2
ngrk\t%0,%1,%2
ng\t%0,%2
+ risbg\t%0,%1,%s2,128+%e2,0
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
***************
*** 6067,6072 ****
--- 6074,6080 ----
z10_super_E1,
*,
z10_super_E1,
+ z10_super_E1,
*,
*")])
***************
*** 6087,6096 ****
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
--- 6095,6106 ----
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
! (compare
! (and:SI
! (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
! (const_int 0)))
! (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
***************
*** 6098,6114 ****
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
! (set_attr "cpu_facility" "*,*,z196,*,*")
! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
! (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
! (const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
--- 6108,6128 ----
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2
! risbg\t%0,%1,%t2,128+%f2,0"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
! (set_attr "cpu_facility" "*,*,z196,*,*,z10")
! (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
! (compare
! (and:SI
! (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d")
! (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq"))
! (const_int 0)))
! (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
***************
*** 6117,6135 ****
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
! (set_attr "cpu_facility" "*,*,z196,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d, d, d, d,d,d,d,d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand"
! " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
--- 6131,6150 ----
nr\t%0,%2
nrk\t%0,%1,%2
n\t%0,%2
! ny\t%0,%2
! risbg\t%0,%1,%t2,128+%f2,0"
! [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
! (set_attr "cpu_facility" "*,*,z196,*,*,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
! z10_super_E1,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
! "=d,d, d, d, d,d,d,d,d, d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
! "%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
(match_operand:SI 2 "general_operand"
! " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
***************
*** 6142,6151 ****
nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
--- 6157,6167 ----
nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
+ risbg\t%0,%1,%t2,128+%f2,0
#
#"
! [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
! (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
***************
*** 6155,6160 ****
--- 6171,6177 ----
*,
z10_super_E1,
z10_super_E1,
+ z10_super_E1,
*,
*")])
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/7] s390: Add mode attribute for mode bitsize
2012-08-10 2:32 ` [PATCH 4/7] s390: Add mode attribute for mode bitsize Richard Henderson
@ 2012-12-14 13:48 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-12-14 13:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches
On Thu, Aug 09, 2012 at 07:31:58PM -0700, Richard Henderson wrote:
> Constant fold, and less typing than, GET_MODE_BITSIZE with
> another mode substitution.
I did just a minor change in order to avoid a warning in the last hunk.
Tested on s390 and s390x with different arch flags.
Please apply to mainline. Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 72 ++++!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 7 insertions(+), 65 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 531,536 ****
--- 531,539 ----
(define_mode_attr bfstart [(DI "s") (SI "t")])
(define_mode_attr bfend [(DI "e") (SI "f")])
+ ;; In place of GET_MODE_BITSIZE (<MODE>mode)
+ (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
+
;;
;;- Compare instructions.
;;
***************
*** 3326,3332 ****
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
! operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
operands[3] = GEN_INT (mask);
})
--- 3329,3335 ----
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
! operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask);
})
***************
*** 3353,3359 ****
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
! operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
operands[3] = GEN_INT (mask);
})
--- 3356,3362 ----
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
! operands[2] = GEN_INT (<GPR:bitsize> - bitsize);
operands[3] = GEN_INT (mask);
})
***************
*** 3373,3421 ****
FAIL;
})
(define_insn "*insv<mode>_zEC12"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
! (match_operand 1 "const_int_operand" "I")
! (match_operand 2 "const_int_operand" "I"))
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
"TARGET_ZEC12
! && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
! GET_MODE_BITSIZE (<MODE>mode)"
! {
! int start = INTVAL (operands[2]);
! int size = INTVAL (operands[1]);
! int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
!
! operands[2] = GEN_INT (offset + start); /* start bit position */
! operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
! operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
! start - size); /* left shift count */
!
! return "risbgn\t%0,%3,%b2,%b1,%b4";
! }
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_z10"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
! (match_operand 1 "const_int_operand" "I")
! (match_operand 2 "const_int_operand" "I"))
(match_operand:GPR 3 "nonimmediate_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
! && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
! GET_MODE_BITSIZE (<MODE>mode)"
! {
! int start = INTVAL (operands[2]);
! int size = INTVAL (operands[1]);
! int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
!
! operands[2] = GEN_INT (offset + start); /* start bit position */
! operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
! operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
! start - size); /* left shift count */
!
! return "risbg\t%0,%3,%b2,%b1,%b4";
! }
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
--- 3376,3404 ----
FAIL;
})
+
+ ; The normal RTL expansion will never generate a zero_extract where
+ ; the location operand isn't word mode. However, we do this in the
+ ; back-end when generating atomic operations. See s390_two_part_insv.
(define_insn "*insv<mode>_zEC12"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
! (match_operand 1 "const_int_operand" "I") ; size
! (match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
"TARGET_ZEC12
! && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
! "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_z10"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
! (match_operand 1 "const_int_operand" "I") ; size
! (match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
! && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
! "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
***************
*** 3585,3592 ****
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
! GET_MODE_BITSIZE (<HQI:MODE>mode));
operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
--- 3568,3574 ----
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>);
operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
***************
*** 3688,3695 ****
{
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GET_MODE_SIZE (QImode));
! operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
! - GET_MODE_BITSIZE (QImode));
})
;
--- 3670,3676 ----
{
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], GET_MODE_SIZE (QImode));
! operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT);
})
;
***************
*** 3800,3807 ****
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
! GET_MODE_BITSIZE(<MODE>mode));
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
--- 3781,3787 ----
}
else if (!TARGET_EXTIMM)
{
! rtx bitcount = GEN_INT (64 - <HQI:bitsize>);
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
***************
*** 3818,3824 ****
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1],
! GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
DONE;
}
})
--- 3798,3804 ----
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_andsi3 (operands[0], operands[1],
! GEN_INT ((1 << <HQI:bitsize>) - 1)));
DONE;
}
})
***************
*** 4011,4018 ****
REAL_VALUE_TYPE cmp, sub;
operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
! real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
! real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
--- 3991,3998 ----
REAL_VALUE_TYPE cmp, sub;
operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
! real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
! real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
***************
*** 4727,4735 ****
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
! || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
! || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
! && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
"@
a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2
--- 4707,4715 ----
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
! || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
! /* Avoid INT32_MIN on 32 bit. */
! && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))"
"@
a<g>hi\t%0,%h2
a<g>hik\t%0,%1,%h2
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/7] s390: Implement extzv for z10
2012-08-10 2:32 ` [PATCH 5/7] s390: Implement extzv for z10 Richard Henderson
@ 2012-12-14 13:53 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-12-14 13:53 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches
I've changed the s390_extzv_shift_ok function and have added extzv
patterns for zEC12. I also tried to implement an extzvsi expander but
ran into some issues which need to be fixed first.
Tested on s390 and s390x with z196 and zEC12.
Please apply to mainline. Thanks!
Bye,
-Andreas-
gcc/config/s390/predicates.md | 4 +
gcc/config/s390/s390-protos.h | 1
gcc/config/s390/s390.c | 18 ++++++++
gcc/config/s390/s390.md | 94 +++++++++++++++++++++++++!!!!!!!!!!!!!!!!!
4 files changed, 81 insertions(+), 36 modifications(!)
Index: gcc/config/s390/predicates.md
===================================================================
*** gcc/config/s390/predicates.md.orig
--- gcc/config/s390/predicates.md
***************
*** 101,106 ****
--- 101,110 ----
return true;
})
+ (define_predicate "nonzero_shift_count_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
+
;; Return true if OP a valid operand for the LARL instruction.
(define_predicate "larl_operand"
Index: gcc/config/s390/s390-protos.h
===================================================================
*** gcc/config/s390/s390-protos.h.orig
--- gcc/config/s390/s390-protos.h
*************** extern bool s390_legitimate_address_with
*** 109,113 ****
--- 109,114 ----
extern bool s390_decompose_shift_count (rtx, rtx *, HOST_WIDE_INT *);
extern int s390_branch_condition_mask (rtx);
extern int s390_compare_and_branch_condition_mask (rtx);
+ extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT);
#endif /* RTX_CODE */
Index: gcc/config/s390/s390.c
===================================================================
*** gcc/config/s390/s390.c.orig
--- gcc/config/s390/s390.c
*************** s390_contiguous_bitmask_p (unsigned HOST
*** 1347,1352 ****
--- 1347,1370 ----
return true;
}
+ /* Check whether a rotate of ROTL followed by an AND of CONTIG is
+ equivalent to a shift followed by the AND. In particular, CONTIG
+ should not overlap the (rotated) bit 0/bit 63 gap. Negative values
+ for ROTL indicate a rotate to the right. */
+
+ bool
+ s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
+ {
+ int pos, len;
+ bool ok;
+
+ ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
+ gcc_assert (ok);
+
+ return ((rotl >= 0 && rotl <= pos)
+ || (rotl < 0 && -rotl <= bitsize - len - pos));
+ }
+
/* Check whether we can (and want to) split a double-word
move in mode MODE from SRC to DST into two single-word
moves, moving the subword FIRST_SUBWORD first. */
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 3307,3321 ****
[(set_attr "op_type" "RS,RSY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
! (define_insn_and_split "*extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
! (match_operand 2 "const_int_operand" "n")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
! "INTVAL (operands[2]) > 0
! && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
"#"
"&& reload_completed"
[(parallel
--- 3307,3370 ----
[(set_attr "op_type" "RS,RSY")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ ;
+ ; extv instruction patterns
+ ;
+
+ ; FIXME: This expander needs to be converted from DI to GPR as well
+ ; after resolving some issues with it.
+
+ (define_expand "extzv"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (zero_extract:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "") ; size
+ (match_operand 3 "const_int_operand" ""))) ; start
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z10"
+ {
+ /* Starting with zEC12 there is risbgn not clobbering CC. */
+ if (TARGET_ZEC12)
+ {
+ emit_move_insn (operands[0],
+ gen_rtx_ZERO_EXTRACT (DImode,
+ operands[1],
+ operands[2],
+ operands[3]));
+ DONE;
+ }
+ })
! (define_insn "*extzv<mode>_zEC12"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (zero_extract:GPR
! (match_operand:GPR 1 "register_operand" "d")
! (match_operand 2 "const_int_operand" "") ; size
! (match_operand 3 "const_int_operand" "")))] ; start]
! "TARGET_ZEC12"
! "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*extzv<mode>_z10"
! [(set (match_operand:GPR 0 "register_operand" "=d")
! (zero_extract:GPR
! (match_operand:GPR 1 "register_operand" "d")
! (match_operand 2 "const_int_operand" "") ; size
! (match_operand 3 "const_int_operand" ""))) ; start
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10"
! "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
! [(set_attr "op_type" "RIE")
! (set_attr "z10prop" "z10_super_E1")])
!
! (define_insn_and_split "*pre_z10_extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
! (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
! "!TARGET_Z10"
"#"
"&& reload_completed"
[(parallel
***************
*** 3333,3346 ****
operands[3] = GEN_INT (mask);
})
! (define_insn_and_split "*extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
! (match_operand 2 "const_int_operand" "n")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
! "INTVAL (operands[2]) > 0
! && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
"#"
"&& reload_completed"
[(parallel
--- 3382,3394 ----
operands[3] = GEN_INT (mask);
})
! (define_insn_and_split "*pre_z10_extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
! (match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
! ""
"#"
"&& reload_completed"
[(parallel
***************
*** 6067,6072 ****
--- 6115,6150 ----
(clobber (reg:CC CC_REGNUM))])]
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
+ ;; These two are what combine generates for (ashift (zero_extract)).
+ (define_insn "*extzv_<mode>_srl"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR (lshiftrt:GPR
+ (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ /* Note that even for the SImode pattern, the rotate is always DImode. */
+ && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
+ INTVAL (operands[3]))"
+ "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+ (define_insn "*extzv_<mode>_sll"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR (ashift:GPR
+ (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
+ INTVAL (operands[3]))"
+ "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
;
; andsi3 instruction pattern(s).
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg
2012-08-10 2:32 ` [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg Richard Henderson
@ 2012-12-14 13:58 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-12-14 13:58 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches
I only changed DSI to GPR. This is semantically the same but more
common in the backend.
Tested on s390 and s390x with z196 and zEC12.
Please apply to mainline. Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 61 ++!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1 file changed, 3 insertions(+), 58 modifications(!)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 393,398 ****
--- 393,401 ----
;; the same template.
(define_code_iterator SHIFT [ashift lshiftrt])
+ ;; This iterator allow r[ox]sbg to be defined with the same template
+ (define_code_iterator IXOR [ior xor])
+
;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult])
(define_code_iterator ATOMIC_Z196 [and ior xor plus])
***************
*** 3474,3488 ****
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
! ; and op1 with a mask being 1 for the selected bits and 0 for the rest
! (define_insn "*insv<mode>_or_z10_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
! "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
--- 3477,3537 ----
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
! (define_insn "*r<noxa>sbg_<mode>_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_di_rotl"
! [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
! (IXOR:DI
! (and:DI
! (rotate:DI
! (match_operand:DI 1 "nonimmediate_operand" "d")
! (match_operand:DI 3 "const_int_operand" ""))
! (match_operand:DI 2 "contiguous_bitmask_operand" ""))
! (match_operand:DI 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_<mode>_srl"
! [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR
! (lshiftrt:GPR
! (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
! INTVAL (operands[2]))"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
! [(set_attr "op_type" "RIE")])
!
! (define_insn "*r<noxa>sbg_<mode>_sll"
! [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
! (IXOR:GPR
! (and:GPR
! (ashift:GPR
! (match_operand:GPR 1 "nonimmediate_operand" "d")
! (match_operand:GPR 3 "nonzero_shift_count_operand" ""))
! (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
! (match_operand:GPR 4 "nonimmediate_operand" "0")))
! (clobber (reg:CC CC_REGNUM))]
! "TARGET_Z10
! && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]),
! INTVAL (operands[2]))"
! "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 7/7] s390: Generate rnsbg
2012-08-10 2:32 ` [PATCH 7/7] s390: Generate rnsbg Richard Henderson
@ 2012-12-14 14:02 ` Andreas Krebbel
0 siblings, 0 replies; 18+ messages in thread
From: Andreas Krebbel @ 2012-12-14 14:02 UTC (permalink / raw)
To: Richard Henderson; +Cc: gcc-patches
I did the change suggested by Uli in the *insv_rnsbg_srl pattern.
Tested on s390 and s390x with z196 and zEC12.
Please apply to mainline. Thanks!
Bye,
-Andreas-
gcc/config/s390/s390.md | 55 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 3534,3539 ****
--- 3534,3594 ----
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
+ ;; These two are generated by combine for s.bf &= val.
+ ;; ??? For bitfields smaller than 32-bits, we wind up with SImode
+ ;; shifts and ands, which results in some truly awful patterns
+ ;; including subregs of operations. Rather unnecessisarily, IMO.
+ ;; Instead of
+ ;;
+ ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
+ ;; (const_int 24 [0x18])
+ ;; (const_int 0 [0]))
+ ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ])
+ ;; (const_int 40 [0x28])) 4)
+ ;; (reg:SI 4 %r4 [ y+4 ])) 0))
+ ;;
+ ;; we should instead generate
+ ;;
+ ;; (set (zero_extract:DI (reg/v:DI 50 [ s ])
+ ;; (const_int 24 [0x18])
+ ;; (const_int 0 [0]))
+ ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ])
+ ;; (const_int 40 [0x28]))
+ ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0)))
+ ;;
+ ;; by noticing that we can push down the outer paradoxical subreg
+ ;; into the operation.
+
+ (define_insn "*insv_rnsbg_noshift"
+ [(set (zero_extract:DI
+ (match_operand:DI 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (and:DI
+ (match_dup 0)
+ (match_operand:DI 3 "nonimmediate_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
+ "rnsbg\t%0,%3,%2,63,0"
+ [(set_attr "op_type" "RIE")])
+
+ (define_insn "*insv_rnsbg_srl"
+ [(set (zero_extract:DI
+ (match_operand:DI 0 "nonimmediate_operand" "+d")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (and:DI
+ (lshiftrt:DI
+ (match_dup 0)
+ (match_operand 3 "const_int_operand" ""))
+ (match_operand:DI 4 "nonimmediate_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10
+ && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
+ "rnsbg\t%0,%4,%2,%2+%1-1,%3"
+ [(set_attr "op_type" "RIE")])
+
(define_insn "*insv<mode>_mem_reg"
[(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
^ permalink raw reply [flat|nested] 18+ messages in thread
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2012-08-10 2:32 [PATCH 0/7] s390 improvements with r[ioxn]sbg Richard Henderson
2012-08-10 2:32 ` [PATCH 5/7] s390: Implement extzv for z10 Richard Henderson
2012-12-14 13:53 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 6/7] s390: Generate rxsbg, and shifted forms of rosbg Richard Henderson
2012-12-14 13:58 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 3/7] s390: Use risbgz for AND Richard Henderson
2012-11-06 14:29 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 4/7] s390: Add mode attribute for mode bitsize Richard Henderson
2012-12-14 13:48 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 1/7] s390: Constraints, predicates, and op letters for contiguous bitmasks Richard Henderson
2012-11-06 12:52 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 2/7] s390: Only use lhs zero_extract in word_mode Richard Henderson
2012-11-06 13:01 ` Andreas Krebbel
2012-08-10 2:32 ` [PATCH 7/7] s390: Generate rnsbg Richard Henderson
2012-12-14 14:02 ` Andreas Krebbel
2012-08-13 17:07 ` [PATCH 0/7] s390 improvements with r[ioxn]sbg Ulrich Weigand
2012-08-13 17:24 ` Richard Henderson
2012-10-09 8:43 ` Andreas Krebbel
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