From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by sourceware.org (Postfix) with ESMTPS id 869673857702 for ; Wed, 6 Sep 2023 14:01:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 869673857702 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-68c0d4cc3a4so2638736b3a.1 for ; Wed, 06 Sep 2023 07:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694008866; x=1694613666; darn=gcc.gnu.org; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=AfZh3HDVuVkvL3JrEu15oN+GpVokKO34fZSitp+O/6A=; b=ohkkreA9grBBnSoZ9uduPyiFNlsIR6tratzA8mbUJr8ufgfcXG8ltbwUmO6+XHUxmu +AgPNw2awZG8J9qYPkxTdksPP65FRnVBvFxvYDcpOXmlasVc7/Rb6NMaNu54hw6LfDBX g+AC7U8KQbE1NSR0lRbr7zJ1kJzJw6EhnVbXWNQkG9kBbChQ4X/2aqGpegcYHpW55kG9 BHRTN4O+/sMrkeA9Z4TRjdZBl8M+gGYDzidUJzHN/iii3unTSW++8IItFg5DonmTZTi3 m1RC8Ge8wRoDYjJZhWQTcwUqvOTgnYy4koj+AdWtsiuY5Hvi7EjIrsN7KBGt+HTjCz/n R+Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694008866; x=1694613666; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AfZh3HDVuVkvL3JrEu15oN+GpVokKO34fZSitp+O/6A=; b=Dv6UhKkrykJijQOExxV9KOmUqPMg721QvOUaiQMJ6V9KFK78g8xR6J0uIB5uzHgQus YPmVKuN3INbO3K02den6mSiMvUun78oIUkE1nl/2rO9ETA5D170X85rfY8Xke6YSEAio L9ax3rFg9kzKsnRpVvLm45QcLsNxOIXio1tdcIPuA5fwWlrNAPDJ0Fiiqw0TYM4hv0WQ iRPpkQHW4NRWRLa1m1zrDeI3IPpw3taGIhtdi5myQS6QkDG0DbqtQtILYM42sp5p6nyU xWcVgS/wZXxKuCbM7ct1H1I+B4hiC5wdhOBUXcTRqVLNVg985/gCNoASChODI7oyzbxd QTbQ== X-Gm-Message-State: AOJu0YyvVqzHVd0o/5aFsHa1Kuoqz9gSudAhjcMtDTc7YfWrf7ho176C NnOu94thRp7jxKNNQUddTDw= X-Google-Smtp-Source: AGHT+IHN/JYkpYbwLyZzifQSk2wjrf5gjibso7R+ZiJgpoCITk9QdEw7kiKdQPi+SypSOrphjbJ2nA== X-Received: by 2002:a05:6a00:4186:b0:68e:388f:c962 with SMTP id ca6-20020a056a00418600b0068e388fc962mr297968pfb.27.1694008866271; Wed, 06 Sep 2023 07:01:06 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id b23-20020aa78117000000b0065a1b05193asm10845482pfi.185.2023.09.06.07.01.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Sep 2023 07:01:05 -0700 (PDT) Message-ID: <1349083b-1483-4f5d-82e7-178fb3154322@gmail.com> Date: Wed, 6 Sep 2023 08:00:59 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] Content-Language: en-US To: Juzhe-Zhong , gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, rdapp.gcc@gmail.com References: <20230906094759.4040203-1-juzhe.zhong@rivai.ai> From: Jeff Law In-Reply-To: <20230906094759.4040203-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 9/6/23 03:47, Juzhe-Zhong wrote: > This patch fix incorrect mode tieable between DI and V2SI which cause ICE > in RA. > > PR target/111296 > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug. > > gcc/testsuite/ChangeLog: > > * g++.target/riscv/rvv/base/pr111296.C: New test. > > --- > gcc/config/riscv/riscv.cc | 7 +++++++ > .../g++.target/riscv/rvv/base/pr111296.C | 18 ++++++++++++++++++ > 2 files changed, 25 insertions(+) > create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 228515acc1f..2c0c4c2f3ae 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -7648,6 +7648,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) > static bool > riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) > { > + /* We don't allow different REG_CLASS modes tieable since it > + will cause ICE in register allocation (RA). > + E.g. V2SI and DI are not tieable. */ > + if (riscv_v_ext_mode_p (mode1) && !riscv_v_ext_mode_p (mode2)) > + return false; > + else if (riscv_v_ext_mode_p (mode2) && !riscv_v_ext_mode_p (mode1)) > + return false; Isn't this just if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2)) OK with that change. jeff