[PATCH 2/2] Support __ATOMIC_HLE_RELEASE for __atomic_clear/store_n

[Andi Kleen <andi@firstfloor.org>]

From: Andi Kleen <ak@linux.intel.com>

__atomic_clear and __atomic_store_n didn't have code to generate
the TSX HLE RELEASE prefix. Add this plus test cases.

Right now it would need another target hook to check for someone
passing __ATOMIC_HLE_ACQUIRE to store/clear. I just ignore this
for now.

Passes bootstrap/test on x86_64.

Ok for release branch / trunk ?

gcc/:
2013-01-11  Andi Kleen  <ak@linux.intel.com>

	PR target/55948
	* builtins.c (expand_builtin_atomic_clear): Add comment.
	* config/i386/sync.md (UNSPEC_MOVA_RELEASE): Add.
	(atomic_store_hle_release<mode>): Add
        (atomic_store<mode>): Check for HLE RELEASE.

gcc/testsuite/:
2013-01-11  Andi Kleen  <ak@linux.intel.com>

	PR target/55948
	* gcc.target/i386/hle-clear-rel.c: New file
	* testsuite/gcc.target/i386/hle-store-rel.c: New file.
---
 gcc/builtins.c                                |    2 ++
 gcc/config/i386/sync.md                       |   16 ++++++++++++++++
 gcc/testsuite/gcc.target/i386/hle-clear-rel.c |    9 +++++++++
 gcc/testsuite/gcc.target/i386/hle-store-rel.c |    9 +++++++++
 4 files changed, 36 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/i386/hle-clear-rel.c
 create mode 100644 gcc/testsuite/gcc.target/i386/hle-store-rel.c

diff --git a/gcc/builtins.c b/gcc/builtins.c
index 2b615a1..c283869 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -5556,6 +5556,8 @@ expand_builtin_atomic_clear (tree exp)
       return const0_rtx;
     }
 
+  /* need target hook there to check for not hle acquire */
+
   if (HAVE_atomic_clear)
     {
       emit_insn (gen_atomic_clear (mem, model));
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 8d22a5e..9eae57f 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -23,6 +23,7 @@
   UNSPEC_SFENCE
   UNSPEC_MFENCE
   UNSPEC_MOVA	; For __atomic support
+  UNSPEC_MOVA_RELEASE
   UNSPEC_LDA
   UNSPEC_STA
 ])
@@ -194,6 +195,14 @@
   DONE;
 })
 
+(define_insn "atomic_store_hle_release<mode>"
+  [(set (match_operand:ATOMIC 0 "memory_operand")
+	(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand")
+			(match_operand:SI 2 "const_int_operand")]
+		       UNSPEC_MOVA_RELEASE))]
+  ""
+  "%K2mov{<imodesuffix>}\t{%1, %0|%0, %1}")
+
 (define_expand "atomic_store<mode>"
   [(set (match_operand:ATOMIC 0 "memory_operand")
 	(unspec:ATOMIC [(match_operand:ATOMIC 1 "register_operand")
@@ -214,6 +223,13 @@
     }
   else
     {
+      if (model & IX86_HLE_RELEASE)
+        {
+      	  emit_insn (gen_atomic_store_hle_release<mode> (operands[0], operands[1],
+	  	  				         operands[2]));
+	  DONE;
+        }					       
+
       /* For seq-cst stores, when we lack MFENCE, use XCHG.  */
       if (model == MEMMODEL_SEQ_CST && !(TARGET_64BIT || TARGET_SSE2))
 	{
diff --git a/gcc/testsuite/gcc.target/i386/hle-clear-rel.c b/gcc/testsuite/gcc.target/i386/hle-clear-rel.c
new file mode 100644
index 0000000..913f6d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/hle-clear-rel.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */
+
+void
+hle_clear (int *p, int v)
+{
+  __atomic_clear (p, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/i386/hle-store-rel.c b/gcc/testsuite/gcc.target/i386/hle-store-rel.c
new file mode 100644
index 0000000..7295d33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/hle-store-rel.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */
+
+void
+hle_store (int *p, int v)
+{
+  __atomic_store_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
-- 
1.7.10.4