From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25002 invoked by alias); 13 Jan 2015 18:57:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 24986 invoked by uid 89); 13 Jan 2015 18:57:16 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-Spam-User: qpsmtpd, 2 recipients X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 13 Jan 2015 18:57:15 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 3267828F015D; Tue, 13 Jan 2015 19:57:12 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IDf1suUFzcVC; Tue, 13 Jan 2015 19:57:12 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 0247B28EF6C3; Tue, 13 Jan 2015 19:57:11 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford , Richard Sandiford , Alan Hayward , "steven@gcc.gnu.org" Subject: Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1 Date: Tue, 13 Jan 2015 19:04:00 -0000 Message-ID: <13670880.MKCSlOSr3D@polaris> User-Agent: KMail/4.7.2 (Linux/3.1.10-1.29-desktop; KDE/4.7.2; x86_64; ; ) In-Reply-To: <87a91qg50x.fsf@googlemail.com> References: <2243996.KNkFcg5eZm@polaris> <87a91qg50x.fsf@googlemail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-SW-Source: 2015-01/txt/msg00918.txt.bz2 > Sorry for the slow response. Jeff has approved the patch in the > meantime, but I didn't want to go ahead and apply it while there > was still disagreement... I still think that it isn't appropriate to short-circuit the main computation as the patch does, but I don't want to block it after Jeff's approval. > (1) we have a non-paradoxical subreg; > (2) both (reg:ymode xregno) and (reg:xmode xregno) occupy full > hard registers (no padding or unused upper bits); > (3) (reg:ymode xregno) and (reg:xmode xregno) store the same number > of bytes (X) in each constituent hard register; > (4) the offset is a multiple of X, i.e. the data we're accessing > is aligned to a register boundary; and > (5) endianness is regular (no differences between words and bytes, > or between registers and memory) OK, that's a nice translation of the new code. :-) It seems to me that the patch wants to extend the support of generic subregs to modes whose sizes are not multiple of each other, which is a requirement of the existing code, but does that in a very specific case for the sake of the ARM port without saying where all the above restrictions come from. -- Eric Botcazou