[Patch ARM] Add big.LITTLE tuning options

[Patch ARM] Add big.LITTLE tuning options

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 1515 bytes --]

Hi,

This patch series adds machinery and functionality to enable
tuning for big.LITTLE systems when compiling for the ARM target.

We take the convention for names to -mcpu that for some big.LITTLE
system where the big core is 'x' and the little core is 'y', the -mcpu
name will be x.y

In order to acheive that, we must first tweak some infrastructure.

First, in order to reduce coupling between assembler versions, we
must add name rewriting for the -mcpu command. big.LITTLE systems
use architecturally compatible cores, so we can be sure that if
we are asked to assemble for cortex-a15.cortex-a7, then we can also
assemble for cortex-a15. Thus, we choose to truncate at the first '.'
delimiter between core names.

The ARM backend presently carries the limitation that each entry in
arm-cores.def must provide a unique 'tuning' target. This is
restrictive and would require constant churn modifications to the
scheduler descriptions to add each big.LITTLE flavour which is released.
We modify this infrastructure to still carry a unique identifier, but also
to carry a potentially shared sheduling identifier.

The final 3 patches add support for new -mcpu values:
cortex-a15.cortex-a7, cortex-a57, cortex-a57.cortex-a53.

The series has been regression tested and built on a number of
configurations, bootstrapped with option --with-cpu=cortex-a15.cortex-a7
and benchmarked on an Cortex-A15 based system and a Cortex-A7 base
system with no regressions.

OK?

Thanks,
James

[ARM 5/5 big.LITTLE] Add support for -mcpu=cortex-a57.cortex-a53

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 500 bytes --]


Hi,

This patch wires up -mcpu=cortex-a57.cortex-a53 as an option to
-mcpu.

Bootstrapped in series, and sanity checked.

OK?

Thanks,
James

---
2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-cores.def (cortex-a57.cortex-a53): New.
	* doc/invoke.texi: Document -mcpu=cortex-a57.cortex-a53.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/bpabi.h
	(BE8_LINK_SPEC): Handle -mcpu=cortex-a57.cortex-a53.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0005-ARM-5-5-big.LITTLE-Add-support-for-mcpu-cortex-a57.c.patch --]
[-- Type: text/x-patch;  name=0005-ARM-5-5-big.LITTLE-Add-support-for-mcpu-cortex-a57.c.patch, Size: 3165 bytes --]

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index d5e562b..9bd3f39 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -154,3 +154,6 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED |
 /* V8 Architecture Processors */
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED, cortex_a53)
 ARM_CORE("cortex-a57",	cortexa57, cortexa15,	8A, FL_LDSCHED, cortex_a15)
+
+/* V8 big.LITTLE implementations */
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 03c1560..702338c 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -291,6 +291,9 @@ Enum(processor_type) String(cortex-a53) Value(cortexa53)
 EnumValue
 Enum(processor_type) String(cortex-a57) Value(cortexa57)
 
+EnumValue
+Enum(processor_type) String(cortex-a57.cortex-a53) Value(cortexa57cortexa53)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index d56956d0ab1bd917ad049f835880bdc0186d7d2a..954cab8efb10329eb40042acb0de2c361d6c13d2 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -30,5 +30,5 @@ (define_attr "tune"
 	cortexa15,cortexr4,cortexr4f,
 	cortexr5,cortexr7,cortexm4,
 	cortexm3,marvell_pj4,cortexa15cortexa7,
-	cortexa53,cortexa57"
+	cortexa53,cortexa57,cortexa57cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 796003b..5cfaeb8 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -64,6 +64,7 @@
    |mcpu=marvell-pj4					\
    |mcpu=cortex-a53					\
    |mcpu=cortex-a57					\
+   |mcpu=cortex-a57.cortex-a53				\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
    |march=armv7e-m|mcpu=cortex-m4                       \
@@ -79,6 +80,7 @@
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a53					\
    |mcpu=cortex-a57					\
+   |mcpu=cortex-a57.cortex-a53				\
    |mcpu=marvell-pj4					\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9743387..b102e13 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12170,8 +12170,8 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
 
 Additionally, this option can specify that GCC should tune the performance
-of the code for a big.LITTLE system.  The only permissible name is:
-@samp{cortex-a15.cortex-a7}.
+of the code for a big.LITTLE system.  Permissible names are:
+@samp{cortex-a15.cortex-a7}, @samp{cortex-a57.cortex-a53}.
 
 @option{-mcpu=generic-@var{arch}} is also permissible, and is
 equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.

[ARM 3/5 big.LITTLE] Add support for -mcpu=cortex-a15.cortex-a7

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 513 bytes --]


Hi,

This patch wires up -mcpu=cortex-a15.cortex-a7 as an option to
-mcpu.

Bootstrapped in series, with --with-cpu=cortex-a15.cortex-a7.

OK?

Thanks,
James

---
2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-cores.def (cortex-a15.cortex-a7): New.
	* doc/invoke.texi: Document -mcpu=cortex-a15.cortex-a7.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/bpabi.h
	(BE8_LINK_SPEC): Handle -mcpu=cortex-a5.cortex-a7.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0003-ARM-3-5-big.LITTLE-Add-support-for-mcpu-cortex-a15.c.patch --]
[-- Type: text/x-patch;  name=0003-ARM-3-5-big.LITTLE-Add-support-for-mcpu-cortex-a15.c.patch, Size: 3087 bytes --]

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 3264eed..0ea5eef 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -148,5 +148,8 @@ ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED, v7m)
 ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED, v7m)
 ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED, 9e)
 
+/* V7 big.LITTLE implementations */
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
+
 /* V8 Architecture Processors */
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED, cortex_a53)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 7da7cc8..d847c10 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -283,6 +283,9 @@ EnumValue
 Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
 
 EnumValue
+Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
+
+EnumValue
 Enum(processor_type) String(cortex-a53) Value(cortexa53)
 
 Enum
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 0386afff7428169ad0e31ae4de4bd677413bc817..beee9af013f6a5a75b7051f3c7077e98fafd45ef 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -29,5 +29,6 @@ (define_attr "tune"
 	cortexa8,cortexa9,cortexa12,
 	cortexa15,cortexr4,cortexr4f,
 	cortexr5,cortexr7,cortexm4,
-	cortexm3,marvell_pj4,cortexa53"
+	cortexm3,marvell_pj4,cortexa15cortexa7,
+	cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index b39c4a9..669884d 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -60,6 +60,7 @@
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
    |mcpu=cortex-a12					\
+   |mcpu=cortex-a15.cortex-a7				\
    |mcpu=marvell-pj4					\
    |mcpu=cortex-a53					\
    |mcpu=generic-armv7-a                                \
@@ -74,6 +75,7 @@
    |mcpu=cortex-a7                                      \
    |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15       \
    |mcpu=cortex-a12					\
+   |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a53					\
    |mcpu=marvell-pj4					\
    |mcpu=generic-armv7-a                                \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b655a64..e069305 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12168,6 +12168,9 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{fa526}, @samp{fa626},
 @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}.
 
+Additionally, this option can specify that GCC should tune the performance
+of the code for a big.LITTLE system.  The only permissible name is:
+@samp{cortex-a15.cortex-a7}.
 
 @option{-mcpu=generic-@var{arch}} is also permissible, and is
 equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.

[ARM 1/5 big.LITTLE] Add driver support for rewriting -mcpu names

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 1009 bytes --]


Hi,

This patch adds machinery to the driver to ensure that big.LITTLE
style tuning names are rewritten before they are passed to the
assembler. This reduces the coupling needed between GCC versions
and assembler versions.

The rule is simple, we truncate the CPU name at the first '.'
character we see.

Thus -mcpu=cortex-a15.cortex-a7 would be truncated to -mcpu=cortex-a15.

Bootstrapped on a ChromeBook and checked for an arm-none-eabi and
an arm-none-linux-gnueabi build.

Thanks,
James

---
gcc/

2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>

	* common/config/arm/arm-common.c (arm_rewrite_selected_cpu): New.
	(arm_rewrite_mcpu): Likewise.
	* config/arm/arm-protos.h (arm_rewrite_selected_cpu): New.
	* config/arm/arm.h (BIG_LITTLE_SPEC): New.
	(BIG_LITTLE_SPEC_FUNCTIONS): Likewise.
	(EXTRA_SPEC_FUNCTIONS): Include BIG_LITTLE_SPEC_FUNCTIONS.
	(ASM_CPU_SPEC): Include BIG_LITTLE_SPEC.
	* config/arm/arm.c (arm_file_start): Rewrite arm_selecetd_cpu values.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-ARM-1-5-big.LITTLE-Add-driver-support-for-rewriting-.patch --]
[-- Type: text/x-patch;  name=0001-ARM-1-5-big.LITTLE-Add-driver-support-for-rewriting-.patch, Size: 3913 bytes --]

diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index c43a2ce..87f18ec 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -63,6 +63,41 @@ arm_except_unwind_info (struct gcc_options *opts)
   return UI_SJLJ;
 }
 
+#define ARM_CPU_NAME_LENGTH 20
+
+/* Truncate NAME at the first '.' character seen, or return
+   NAME unmodified.  */
+
+const char *
+arm_rewrite_selected_cpu (const char *name)
+{
+  static char output_buf[ARM_CPU_NAME_LENGTH + 1] = {0};
+  char *arg_pos;
+
+  strncpy (output_buf, name, ARM_CPU_NAME_LENGTH);
+  arg_pos = strchr (output_buf, '.');
+
+  /* If we found a '.' truncate the entry at that point.  */
+  if (arg_pos)
+    *arg_pos = '\0';
+
+  return output_buf;
+}
+
+/* Called by the driver to rewrite a name passed to the -mcpu
+   argument in preparation to be passed to the assembler.  The
+   name will be in ARGV[0], ARGC should always be 1.  */
+
+const char *
+arm_rewrite_mcpu (int argc, const char **argv)
+{
+  gcc_assert (argc == 1);
+  return arm_rewrite_selected_cpu (argv[0]);
+}
+
+#undef ARM_CPU_NAME_LENGTH
+
+
 #undef  TARGET_DEFAULT_TARGET_FLAGS
 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
 
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index c5b16da..558f134 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -289,4 +289,7 @@ extern bool arm_autoinc_modes_ok_p (enum machine_mode, enum arm_auto_incmodes);
 
 extern void arm_emit_eabi_attribute (const char *, int, int);
 
+/* Defined in gcc/common/config/arm-common.c.  */
+extern const char *arm_rewrite_selected_cpu (const char *name);
+
 #endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7027a26..a4ab6be 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -27527,7 +27527,11 @@ arm_file_start (void)
       else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
 	asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
       else
-	asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name);
+	{
+	  const char* truncated_name
+	    = arm_rewrite_selected_cpu (arm_selected_cpu->name);
+	  asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
+	}
 
       if (TARGET_SOFT_FLOAT)
 	{
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8b8b80e..6539ec6 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2343,16 +2343,25 @@ extern int making_const_table;
    instruction.  */
 #define MAX_LDM_STM_OPS 4
 
+#define BIG_LITTLE_SPEC \
+   " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" \
+
+extern const char *arm_rewrite_mcpu (int argc, const char **argv);
+#define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
+  { "rewrite_mcpu", arm_rewrite_mcpu },
+
 #define ASM_CPU_SPEC \
    " %{mcpu=generic-*:-march=%*;"				\
-   "   :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
+   "   :%{march=*:-march=%*}}"					\
+   BIG_LITTLE_SPEC
 
 /* -mcpu=native handling only makes sense with compiler running on
    an ARM chip.  */
 #if defined(__arm__)
 extern const char *host_detect_local_cpu (int argc, const char **argv);
 # define EXTRA_SPEC_FUNCTIONS						\
-  { "local_cpu_detect", host_detect_local_cpu },
+  { "local_cpu_detect", host_detect_local_cpu },			\
+  BIG_LITTLE_CPU_SPEC_FUNCTIONS
 
 # define MCPU_MTUNE_NATIVE_SPECS					\
    " %{march=native:%<march=native %:local_cpu_detect(arch)}"		\
@@ -2360,6 +2369,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
 #else
 # define MCPU_MTUNE_NATIVE_SPECS ""
+# define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
 #endif
 
 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS

[ARM 2/5 big.LITTLE] Allow tuning parameters without unique tuning targets.

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 1249 bytes --]


Hi,

A limitation in the ARM backend is that each core added to arm-cores.def
must provide a unique identifier to be used for tuning. This restricts
us when we want to share the same identifier between a number of cores.

The machinery here is a bit messy, and we don't really make it any nicer
in this patch. But, this change does allow you to add core names which
use other tuning targets easily.

This, for example allows us to wire up -mcpu=cortex-a15.cortex-a7 to
use the scheduler description for Cortex-A7 without requiring
modifications to the Cortex-A7 scheduler description.

Bootstrapped in series and checked on arm-none-linux-gnueabi and
arm-none-eabi.

OK?

Thanks,
James

---
gcc/

2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-cores.def: Add new column for TUNE_IDENT.
	* config/arm/genopt.sh: Improve layout.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-opts.h (ARM_CORE): Modify macro for TUNE_IDENT.
	* config/arm/arm.c (ARM_CORE): Modify macro for TUNE_IDENT.
	(arm_option_override): When a CPU is chosen, that should also
	form the tune target.
	* config/arm/arm.h (ARM_CORE): Modify macro for TUNE_IDENT.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-ARM-2-5-big.LITTLE-Allow-tuning-parameters-without-u.patch --]
[-- Type: text/x-patch;  name=0002-ARM-2-5-big.LITTLE-Allow-tuning-parameters-without-u.patch, Size: 21432 bytes --]

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index e7cea63..3264eed 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -20,10 +20,13 @@
 
 /* Before using #include to read this file, define a macro:
 
-      ARM_CORE(CORE_NAME, CORE_IDENT, ARCH, FLAGS, COSTS)
+      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, ARCH, FLAGS, COSTS)
 
    The CORE_NAME is the name of the core, represented as a string constant.
-   The CORE_IDENT is the name of the core, represented as an identifier.
+   The INTERNAL_IDENT is the name of the core represented as an identifier.
+   This must be unique for each entry in this table.
+   The TUNE_IDENT is the name of the core for which scheduling decisions
+   should be made, represented as an identifier.
    ARCH is the architecture revision implemented by the chip.
    FLAGS are the bitwise-or of the traits that apply to that core.
    This need not include flags implied by the architecture.
@@ -35,109 +38,115 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2",   arm2,	2,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm250", arm250,	2,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm3",   arm3,	2,	FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm2", 	arm2, arm2,	2, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm250", 	arm250, arm250,	2, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm3",	arm3, arm3,	2, FL_CO_PROC | FL_MODE26, slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",          arm6,		3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm60",         arm60,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm600",        arm600,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm610",        arm610,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm620",        arm620,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7",          arm7,		3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7d",         arm7d,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm7di",        arm7di,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm70",         arm70,	3,	FL_CO_PROC | FL_MODE26, slowmul)
-ARM_CORE("arm700",        arm700,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm700i",       arm700i,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710",        arm710,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm720",        arm720,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm710c",       arm710c,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7100",       arm7100,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-ARM_CORE("arm7500",       arm7500,	3,	             FL_MODE26 | FL_WBUF, slowmul)
-/* Doesn't have an external co-proc, but does have embedded fpa.  */
-ARM_CORE("arm7500fe",     arm7500fe,	3,	FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm6",	arm6, arm6,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm60",	arm60, arm60,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm600",	arm600, arm600,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm610",	arm610, arm610,		3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm620",	arm620, arm620,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7",	arm7, arm7,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm70",	arm70, arm70,		3, FL_CO_PROC | FL_MODE26, slowmul)
+ARM_CORE("arm700",	arm700, arm700,		3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm710",	arm710, arm710,		3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm720",	arm720, arm720,		3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	3, FL_MODE26 | FL_WBUF, slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	3, FL_MODE26 | FL_WBUF, slowmul)
+/* Doesn't have an external co-proc, but does have embedded fpa. */
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	3, FL_CO_PROC | FL_MODE26 | FL_WBUF, slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",         arm7m,	3M,	FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dm",        arm7dm,	3M,	FL_CO_PROC | FL_MODE26, fastmul)
-ARM_CORE("arm7dmi",       arm7dmi,	3M,	FL_CO_PROC | FL_MODE26, fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,	3M, FL_CO_PROC | FL_MODE26, fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,	3M, FL_CO_PROC | FL_MODE26, fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,	3M, FL_CO_PROC | FL_MODE26, fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8,		4,	             FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("arm810",        arm810,	4,	             FL_MODE26 | FL_LDSCHED, fastmul)
-ARM_CORE("strongarm",     strongarm,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm110",  strongarm110,	4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1100", strongarm1100, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("strongarm1110", strongarm1110, 4,	             FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
-ARM_CORE("fa526",         fa526,        4,                               FL_LDSCHED, fastmul)
-ARM_CORE("fa626",         fa626,        4,                               FL_LDSCHED, fastmul)
+ARM_CORE("arm8",          arm8, arm8,			4, FL_MODE26 | FL_LDSCHED, fastmul)
+ARM_CORE("arm810",        arm810, arm810,		4, FL_MODE26 | FL_LDSCHED, fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, FL_MODE26 | FL_LDSCHED | FL_STRONG, strongarm)
+ARM_CORE("fa526",         fa526, fa526,			4, FL_LDSCHED, fastmul)
+ARM_CORE("fa626",         fa626, fa626,			4, FL_LDSCHED, fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",      arm7tdmi,	4T,	FL_CO_PROC          , fastmul)
-ARM_CORE("arm7tdmi-s",    arm7tdmis,	4T,	FL_CO_PROC          , fastmul)
-ARM_CORE("arm710t",       arm710t,	4T,	             FL_WBUF, fastmul)
-ARM_CORE("arm720t",       arm720t,	4T,	             FL_WBUF, fastmul)
-ARM_CORE("arm740t",       arm740t,	4T,	             FL_WBUF, fastmul)
-ARM_CORE("arm9",          arm9,		4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm9tdmi",      arm9tdmi,	4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm920",        arm920,	4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm920t",       arm920t,	4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm922t",       arm922t,	4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm940t",       arm940t,	4T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("ep9312",        ep9312,	4T,	                         FL_LDSCHED, fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	4T, FL_CO_PROC, fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	4T, FL_CO_PROC, fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	4T, FL_WBUF,    fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	4T, FL_WBUF,    fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	4T, FL_WBUF,    fastmul)
+ARM_CORE("arm9",	arm9, arm9,		4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm920",	arm920, arm920,		4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	4T, FL_LDSCHED, fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	4T, FL_LDSCHED, fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		4T, FL_LDSCHED, fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",     arm10tdmi,	5T,	                         FL_LDSCHED, fastmul)
-ARM_CORE("arm1020t",      arm1020t,	5T,	                         FL_LDSCHED, fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	5T, FL_LDSCHED, fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	5T, FL_LDSCHED, fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",         arm9e,	5TE,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm946e-s",     arm946es,	5TE,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm966e-s",     arm966es,	5TE,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm968e-s",     arm968es,	5TE,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm10e",        arm10e,	5TE,				 FL_LDSCHED, fastmul)
-ARM_CORE("arm1020e",      arm1020e,	5TE,				 FL_LDSCHED, fastmul)
-ARM_CORE("arm1022e",      arm1022e,	5TE,				 FL_LDSCHED, fastmul)
-ARM_CORE("xscale",        xscale,	5TE,	                         FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
-ARM_CORE("iwmmxt",        iwmmxt,	5TE,	                         FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
-ARM_CORE("iwmmxt2",       iwmmxt2,	5TE,	                         FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale)
-ARM_CORE("fa606te",       fa606te,      5TE,                             FL_LDSCHED, 9e)
-ARM_CORE("fa626te",       fa626te,      5TE,                             FL_LDSCHED, 9e)
-ARM_CORE("fmp626",        fmp626,       5TE,                             FL_LDSCHED, 9e)
-ARM_CORE("fa726te",       fa726te,      5TE,                             FL_LDSCHED, fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		5TE, FL_LDSCHED, 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	5TE, FL_LDSCHED, 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	5TE, FL_LDSCHED, 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	5TE, FL_LDSCHED, 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		5TE, FL_LDSCHED, fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	5TE, FL_LDSCHED, fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	5TE, FL_LDSCHED, fastmul)
+ARM_CORE("xscale",	xscale, xscale,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2, xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	5TE, FL_LDSCHED, 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	5TE, FL_LDSCHED, 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		5TE, FL_LDSCHED, 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	5TE, FL_LDSCHED, fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",    arm926ejs,	5TEJ,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm1026ej-s",   arm1026ejs,	5TEJ,	                         FL_LDSCHED, 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	5TEJ, FL_LDSCHED, 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	5TEJ, FL_LDSCHED, 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",    arm1136js,	6J,	                         FL_LDSCHED, 9e)
-ARM_CORE("arm1136jf-s",   arm1136jfs,	6J,	                         FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1176jz-s",	  arm1176jzs,	6ZK,				 FL_LDSCHED, 9e)
-ARM_CORE("arm1176jzf-s",  arm1176jzfs,	6ZK,				 FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("mpcorenovfp",	  mpcorenovfp,	6K,				 FL_LDSCHED, 9e)
-ARM_CORE("mpcore",	  mpcore,	6K,				 FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1156t2-s",	  arm1156t2s,	6T2,				 FL_LDSCHED, v6t2)
-ARM_CORE("arm1156t2f-s",  arm1156t2fs,  6T2,				 FL_LDSCHED | FL_VFPV2, v6t2)
-ARM_CORE("generic-armv7-a", genericv7a,	7A,				 FL_LDSCHED, cortex)
-ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
-ARM_CORE("cortex-a7",	  cortexa7,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
-ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
-ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
-ARM_CORE("cortex-a12",	  cortexa12,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
-ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
-ARM_CORE("cortex-a53",	  cortexa53,	8A,				 FL_LDSCHED, cortex_a53)
-ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
-ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
-ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-r7",	  cortexr7,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-m4",	  cortexm4,	7EM,				 FL_LDSCHED, v7m)
-ARM_CORE("cortex-m3",	  cortexm3,	7M,				 FL_LDSCHED, v7m)
-ARM_CORE("cortex-m1",	  cortexm1,	6M,				 FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0",	  cortexm0,	6M,				 FL_LDSCHED, v6m)
-ARM_CORE("cortex-m0plus", cortexm0plus,	6M,				 FL_LDSCHED, v6m)
-ARM_CORE("marvell-pj4",   marvell_pj4,  7A,                              FL_LDSCHED, 9e)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		6J,  FL_LDSCHED, 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		6J,  FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		6ZK, FL_LDSCHED, 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	6ZK, FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	6K,  FL_LDSCHED, 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			6K,  FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		6T2, FL_LDSCHED, v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	6T2, FL_LDSCHED | FL_VFPV2, v6t2)
+
+/* V6M Architecture Processors */
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		6M, FL_LDSCHED, v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	6M, FL_LDSCHED, v6m)
+
+/* V7 Architecture Processors */
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		7A,  FL_LDSCHED, cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		7A,  FL_LDSCHED, cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		7A,  FL_LDSCHED, cortex)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		7A,  FL_LDSCHED, cortex_a9)
+ARM_CORE("cortex-a12",	  	cortexa12, cortexa12,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		7R,  FL_LDSCHED, cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		7R,  FL_LDSCHED, cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		7R,  FL_LDSCHED | FL_ARM_DIV, cortex)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		7EM, FL_LDSCHED, v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		7M,  FL_LDSCHED, v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	7A,  FL_LDSCHED, 9e)
+
+/* V8 Architecture Processors */
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED, cortex_a53)
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index a3ef364..dab308e 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -23,8 +23,9 @@
 /* The various ARM cores.  */
 enum processor_type
 {
-#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
-  IDENT,
+#undef ARM_CORE
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
+  INTERNAL_IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
   /* Used to indicate that no processor has been specified.  */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index b3e7a7c..7da7cc8 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -232,6 +232,15 @@ EnumValue
 Enum(processor_type) String(arm1156t2f-s) Value(arm1156t2fs)
 
 EnumValue
+Enum(processor_type) String(cortex-m1) Value(cortexm1)
+
+EnumValue
+Enum(processor_type) String(cortex-m0) Value(cortexm0)
+
+EnumValue
+Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus)
+
+EnumValue
 Enum(processor_type) String(generic-armv7-a) Value(genericv7a)
 
 EnumValue
@@ -253,9 +262,6 @@ EnumValue
 Enum(processor_type) String(cortex-a15) Value(cortexa15)
 
 EnumValue
-Enum(processor_type) String(cortex-a53) Value(cortexa53)
-
-EnumValue
 Enum(processor_type) String(cortex-r4) Value(cortexr4)
 
 EnumValue
@@ -274,16 +280,10 @@ EnumValue
 Enum(processor_type) String(cortex-m3) Value(cortexm3)
 
 EnumValue
-Enum(processor_type) String(cortex-m1) Value(cortexm1)
-
-EnumValue
-Enum(processor_type) String(cortex-m0) Value(cortexm0)
-
-EnumValue
-Enum(processor_type) String(cortex-m0plus) Value(cortexm0plus)
+Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
 
 EnumValue
-Enum(processor_type) String(marvell-pj4) Value(marvell_pj4)
+Enum(processor_type) String(cortex-a53) Value(cortexa53)
 
 Enum
 Name(arm_arch) Type(int)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index e10d0aa95449dca4030bd83ff8141a51b9e0010a..0386afff7428169ad0e31ae4de4bd677413bc817 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -1,5 +1,33 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from arm-cores.def
 (define_attr "tune"
-	"arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa12,cortexa15,cortexa53,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
+	"arm2,arm250,arm3,
+	arm6,arm60,arm600,
+	arm610,arm620,arm7,
+	arm7d,arm7di,arm70,
+	arm700,arm700i,arm710,
+	arm720,arm710c,arm7100,
+	arm7500,arm7500fe,arm7m,
+	arm7dm,arm7dmi,arm8,
+	arm810,strongarm,strongarm110,
+	strongarm1100,strongarm1110,fa526,
+	fa626,arm7tdmi,arm7tdmis,
+	arm710t,arm720t,arm740t,
+	arm9,arm9tdmi,arm920,
+	arm920t,arm922t,arm940t,
+	ep9312,arm10tdmi,arm1020t,
+	arm9e,arm946es,arm966es,
+	arm968es,arm10e,arm1020e,
+	arm1022e,xscale,iwmmxt,
+	iwmmxt2,fa606te,fa626te,
+	fmp626,fa726te,arm926ejs,
+	arm1026ejs,arm1136js,arm1136jfs,
+	arm1176jzs,arm1176jzfs,mpcorenovfp,
+	mpcore,arm1156t2s,arm1156t2fs,
+	cortexm1,cortexm0,cortexm0plus,
+	genericv7a,cortexa5,cortexa7,
+	cortexa8,cortexa9,cortexa12,
+	cortexa15,cortexr4,cortexr4f,
+	cortexr5,cortexr7,cortexm4,
+	cortexm3,marvell_pj4,cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a4ab6be..2bc9bf1 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1742,7 +1742,7 @@ const struct tune_params arm_fa726te_tune =
 static const struct processors all_cores[] =
 {
   /* ARM Cores */
-#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
   {NAME, IDENT, #ARCH, BASE_ARCH_##ARCH,	  \
     FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune},
 #include "arm-cores.def"
@@ -2251,7 +2251,10 @@ arm_option_override (void)
     arm_selected_arch = &all_architectures[arm_arch_option];
 
   if (global_options_set.x_arm_cpu_option)
-    arm_selected_cpu = &all_cores[(int) arm_cpu_option];
+    {
+      arm_selected_cpu = &all_cores[(int) arm_cpu_option];
+      arm_selected_tune = &all_cores[(int) arm_cpu_option];
+    }
 
   if (global_options_set.x_arm_tune_option)
     arm_selected_tune = &all_cores[(int) arm_tune_option];
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 6539ec6..7b5a7f9 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -162,8 +162,8 @@ extern char arm_arch_name[];
 
 enum target_cpus
 {
-#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
-  TARGET_CPU_##IDENT,
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
+  TARGET_CPU_##INTERNAL_IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
   TARGET_CPU_generic
diff --git a/gcc/config/arm/gentune.sh b/gcc/config/arm/gentune.sh
index 725ae0f..2893ab4 100755
--- a/gcc/config/arm/gentune.sh
+++ b/gcc/config/arm/gentune.sh
@@ -25,5 +25,5 @@ echo ";; Generated automatically by gentune.sh from arm-cores.def"
 allcores=`awk -F'[(, 	]+' '/^ARM_CORE/ { cores = cores$3"," } END { print cores } ' $1`
 
 echo "(define_attr \"tune\""
-echo "	\"$allcores\"" | sed -e 's/,"$/"/'
+echo "	\"$allcores\"" | sed -e 's/,"$/"/' | sed -e 's/\([a-z0-9_]\+,[a-z0-9_]\+,[a-z0-9_]\+,\)/\1\n\t/g'
 echo "	(const (symbol_ref \"((enum attr_tune) arm_tune)\")))"

[ARM 4/5 big.LITTLE] Add support for -mcpu=cortex-a57

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 603 bytes --]


Hi,

This patch wires up -mcpu=cortex-a57 as an option to
-mcpu. As we don't yet have a scheduling model for Cortex-A57
available, for now we use the scheduling description for another
"big" core, the Cortex-A15.

Bootstrapped in series and sanity checked.

OK?

Thanks,
James

---
2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/arm/arm-cores.def (cortex-a57): New.
	* doc/invoke.texi: Document -mcpu=cortex-a57.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Handle -mcpu=cortex-a57.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0004-ARM-4-5-big.LITTLE-Add-support-for-mcpu-cortex-a57.patch --]
[-- Type: text/x-patch;  name=0004-ARM-4-5-big.LITTLE-Add-support-for-mcpu-cortex-a57.patch, Size: 2978 bytes --]

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 0ea5eef..d5e562b 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -153,3 +153,4 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,  FL_LDSCHED |
 
 /* V8 Architecture Processors */
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A, FL_LDSCHED, cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa15,	8A, FL_LDSCHED, cortex_a15)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index d847c10..03c1560 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -288,6 +288,9 @@ Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7)
 EnumValue
 Enum(processor_type) String(cortex-a53) Value(cortexa53)
 
+EnumValue
+Enum(processor_type) String(cortex-a57) Value(cortexa57)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index beee9af013f6a5a75b7051f3c7077e98fafd45ef..d56956d0ab1bd917ad049f835880bdc0186d7d2a 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -30,5 +30,5 @@ (define_attr "tune"
 	cortexa15,cortexr4,cortexr4f,
 	cortexr5,cortexr7,cortexm4,
 	cortexm3,marvell_pj4,cortexa15cortexa7,
-	cortexa53"
+	cortexa53,cortexa57"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 669884d..796003b 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -63,6 +63,7 @@
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=marvell-pj4					\
    |mcpu=cortex-a53					\
+   |mcpu=cortex-a57					\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
    |march=armv7e-m|mcpu=cortex-m4                       \
@@ -77,6 +78,7 @@
    |mcpu=cortex-a12					\
    |mcpu=cortex-a15.cortex-a7				\
    |mcpu=cortex-a53					\
+   |mcpu=cortex-a57					\
    |mcpu=marvell-pj4					\
    |mcpu=generic-armv7-a                                \
    |march=armv7-m|mcpu=cortex-m3                        \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e069305..9743387 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12157,7 +12157,8 @@ assembly code.  Permissible names are: @samp{arm2}, @samp{arm250},
 @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
 @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
 @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
-@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-r4},
+@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57},
+@samp{cortex-r4},
 @samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4},
 @samp{cortex-m3},
 @samp{cortex-m1},

Re: [ARM 1/5 big.LITTLE] Add driver support for rewriting -mcpu names

[Richard Earnshaw]

On 17/12/13 10:40, James Greenhalgh wrote:
> 
> Hi,
> 
> This patch adds machinery to the driver to ensure that big.LITTLE
> style tuning names are rewritten before they are passed to the
> assembler. This reduces the coupling needed between GCC versions
> and assembler versions.
> 
> The rule is simple, we truncate the CPU name at the first '.'
> character we see.
> 
> Thus -mcpu=cortex-a15.cortex-a7 would be truncated to -mcpu=cortex-a15.
> 
> Bootstrapped on a ChromeBook and checked for an arm-none-eabi and
> an arm-none-linux-gnueabi build.
> 
> Thanks,
> James
> 
> ---
> gcc/
> 
> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* common/config/arm/arm-common.c (arm_rewrite_selected_cpu): New.
> 	(arm_rewrite_mcpu): Likewise.
> 	* config/arm/arm-protos.h (arm_rewrite_selected_cpu): New.
> 	* config/arm/arm.h (BIG_LITTLE_SPEC): New.
> 	(BIG_LITTLE_SPEC_FUNCTIONS): Likewise.
> 	(EXTRA_SPEC_FUNCTIONS): Include BIG_LITTLE_SPEC_FUNCTIONS.
> 	(ASM_CPU_SPEC): Include BIG_LITTLE_SPEC.
> 	* config/arm/arm.c (arm_file_start): Rewrite arm_selecetd_cpu values.
> 

OK.

R.

Re: [ARM 2/5 big.LITTLE] Allow tuning parameters without unique tuning targets.

[Richard Earnshaw]

On 17/12/13 10:40, James Greenhalgh wrote:
> 
> Hi,
> 
> A limitation in the ARM backend is that each core added to arm-cores.def
> must provide a unique identifier to be used for tuning. This restricts
> us when we want to share the same identifier between a number of cores.
> 
> The machinery here is a bit messy, and we don't really make it any nicer
> in this patch. But, this change does allow you to add core names which
> use other tuning targets easily.
> 
> This, for example allows us to wire up -mcpu=cortex-a15.cortex-a7 to
> use the scheduler description for Cortex-A7 without requiring
> modifications to the Cortex-A7 scheduler description.
> 
> Bootstrapped in series and checked on arm-none-linux-gnueabi and
> arm-none-eabi.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> gcc/
> 
> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/arm-cores.def: Add new column for TUNE_IDENT.
> 	* config/arm/genopt.sh: Improve layout.
> 	* config/arm/arm-tune.md: Regenerate.
> 	* config/arm/arm-tables.opt: Regenerate.
> 	* config/arm/arm-opts.h (ARM_CORE): Modify macro for TUNE_IDENT.
> 	* config/arm/arm.c (ARM_CORE): Modify macro for TUNE_IDENT.
> 	(arm_option_override): When a CPU is chosen, that should also
> 	form the tune target.
> 	* config/arm/arm.h (ARM_CORE): Modify macro for TUNE_IDENT.
> 

OK.

R.

Re: [ARM 3/5 big.LITTLE] Add support for -mcpu=cortex-a15.cortex-a7

[Richard Earnshaw]

On 17/12/13 10:40, James Greenhalgh wrote:
> 
> Hi,
> 
> This patch wires up -mcpu=cortex-a15.cortex-a7 as an option to
> -mcpu.
> 
> Bootstrapped in series, with --with-cpu=cortex-a15.cortex-a7.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/arm-cores.def (cortex-a15.cortex-a7): New.
> 	* doc/invoke.texi: Document -mcpu=cortex-a15.cortex-a7.
> 	* config/arm/arm-tables.opt: Regenerate.
> 	* config/arm/arm-tune.md: Regenerate.
> 	* config/arm/bpabi.h
> 	(BE8_LINK_SPEC): Handle -mcpu=cortex-a5.cortex-a7.
> 
> 
OK.

R.

Re: [ARM 4/5 big.LITTLE] Add support for -mcpu=cortex-a57

[Richard Earnshaw]

On 17/12/13 10:40, James Greenhalgh wrote:
> 
> Hi,
> 
> This patch wires up -mcpu=cortex-a57 as an option to
> -mcpu. As we don't yet have a scheduling model for Cortex-A57
> available, for now we use the scheduling description for another
> "big" core, the Cortex-A15.
> 
> Bootstrapped in series and sanity checked.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/arm-cores.def (cortex-a57): New.
> 	* doc/invoke.texi: Document -mcpu=cortex-a57.
> 	* config/arm/arm-tables.opt: Regenerate.
> 	* config/arm/arm-tune.md: Regenerate.
> 	* config/arm/bpabi.h (BE8_LINK_SPEC): Handle -mcpu=cortex-a57.
> 
> 

OK.

R.

Re: [ARM 5/5 big.LITTLE] Add support for -mcpu=cortex-a57.cortex-a53

[Richard Earnshaw]

On 17/12/13 10:40, James Greenhalgh wrote:
> 
> Hi,
> 
> This patch wires up -mcpu=cortex-a57.cortex-a53 as an option to
> -mcpu.
> 
> Bootstrapped in series, and sanity checked.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* config/arm/arm-cores.def (cortex-a57.cortex-a53): New.
> 	* doc/invoke.texi: Document -mcpu=cortex-a57.cortex-a53.
> 	* config/arm/arm-tables.opt: Regenerate.
> 	* config/arm/arm-tune.md: Regenerate.
> 	* config/arm/bpabi.h
> 	(BE8_LINK_SPEC): Handle -mcpu=cortex-a57.cortex-a53.
> 
> 

OK.

R.

Re: [ARM 1/5 big.LITTLE] Add driver support for rewriting -mcpu names

[Charles Baylis]

Hi James,

This commit (SVN r206045) seems to have introduced a problem when
compiling multiple source files if a -mcpu option is also present on
the command line.

This can be reproduced in a arm-unknown-linux-gnueabihf build with any
source file which use floating point arguments/results. For example

===== t.c
float f(void) { return 1.0f;}
=====

Note that the example command line here specifies t.c twice, although
any two source files can be used. It is the second compilation which
triggers the error.
$ ~/tools/tools-arm-unknown-linux-gnueabihf-trunk/bin/arm-unknown-linux-gnueabihf-gcc
-mcpu=cortex-a15 -O2 -c t.c t.c
t.c: In function ‘f’:
t.c:2:1: sorry, unimplemented: Thumb-1 hard-float VFP ABI
 float f(void) { return 1.0f;}
 ^

Thanks in advance for taking a look
Charles


On 17 December 2013 11:53, Richard Earnshaw <rearnsha@arm.com> wrote:
> On 17/12/13 10:40, James Greenhalgh wrote:
>>
>> Hi,
>>
>> This patch adds machinery to the driver to ensure that big.LITTLE
>> style tuning names are rewritten before they are passed to the
>> assembler. This reduces the coupling needed between GCC versions
>> and assembler versions.
>>
>> The rule is simple, we truncate the CPU name at the first '.'
>> character we see.
>>
>> Thus -mcpu=cortex-a15.cortex-a7 would be truncated to -mcpu=cortex-a15.
>>
>> Bootstrapped on a ChromeBook and checked for an arm-none-eabi and
>> an arm-none-linux-gnueabi build.
>>
>> Thanks,
>> James
>>
>> ---
>> gcc/
>>
>> 2013-12-17  James Greenhalgh  <james.greenhalgh@arm.com>
>>
>>       * common/config/arm/arm-common.c (arm_rewrite_selected_cpu): New.
>>       (arm_rewrite_mcpu): Likewise.
>>       * config/arm/arm-protos.h (arm_rewrite_selected_cpu): New.
>>       * config/arm/arm.h (BIG_LITTLE_SPEC): New.
>>       (BIG_LITTLE_SPEC_FUNCTIONS): Likewise.
>>       (EXTRA_SPEC_FUNCTIONS): Include BIG_LITTLE_SPEC_FUNCTIONS.
>>       (ASM_CPU_SPEC): Include BIG_LITTLE_SPEC.
>>       * config/arm/arm.c (arm_file_start): Rewrite arm_selecetd_cpu values.
>>
>
> OK.
>
> R.
>
>

Re: [ARM 1/5 big.LITTLE] Add driver support for rewriting -mcpu names

[James Greenhalgh]

On Wed, Jan 15, 2014 at 08:36:09PM +0000, Charles Baylis wrote:
> Hi James,
> 
> This commit (SVN r206045) seems to have introduced a problem when
> compiling multiple source files if a -mcpu option is also present on
> the command line.
> 
> This can be reproduced in a arm-unknown-linux-gnueabihf build with any
> source file which use floating point arguments/results. For example
> 
> ===== t.c
> float f(void) { return 1.0f;}
> =====
> 
> Note that the example command line here specifies t.c twice, although
> any two source files can be used. It is the second compilation which
> triggers the error.
> $ ~/tools/tools-arm-unknown-linux-gnueabihf-trunk/bin/arm-unknown-linux-gnueabihf-gcc
> -mcpu=cortex-a15 -O2 -c t.c t.c
> t.c: In function ‘f’:
> t.c:2:1: sorry, unimplemented: Thumb-1 hard-float VFP ABI
>  float f(void) { return 1.0f;}
>  ^

Hi Charles,

I can't reproduce exactly the error you see, but I do see a bug
which explains what is happening.

The key can be seen by turning on -v. You will notice that
COLLECT_GCC_OPTIONS for the first invocation of cc1 has a
-mcpu value, but the second invocation does not.

At a guess, your configuration is set with --with-mode=thumb,
and probably has a default architecture of armv4. With the first
invocation of cc1 the -mcpu overrides the default architecture and
you get an armv7-a, hard-float, thumb mode binary. With the
second invocation of cc1 there is no -mcpu and the compiler will try
to build an armv4, hard-float, thumb mode binary - and fail with the
message above.

It should be the case that if we fix BIG_LITTLE_SPEC in
arm.h such that the second invocation of cc1 also gets a -mcpu
value, your issue will be resolved.

I'll work on a fix.

Thanks,
James

Re: [ARM 1/5 big.LITTLE] Add driver support for rewriting -mcpu names

[Charles Baylis]

On 16 January 2014 14:26, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>
> At a guess, your configuration is set with --with-mode=thumb,
> and probably has a default architecture of armv4. With the first
> invocation of cc1 the -mcpu overrides the default architecture and

Apologies, I should have included my configure line. I provide it here
in case it helps.
 --target=arm-unknown-linux-gnueabihf --with-arch=armv7-a
--with-tune=cortex-a9 --with-fpu=vfpv3-d16 --with-float=hard
--with-mode=thumb  --enable-languages=c,c++ --with-sysroot=$SYSROOT

Thanks
Charles

[AArch64] fix big.LITTLE spec rewriting

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 1179 bytes --]


Hi,

As Charles Baylis pointed out here:

http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00921.html

The way that we rewrite command lines for big.LITTLE systems
causes bugs where more than one source file is to be used.
The problem fundamentally is that -mcpu never makes it to
the second cc1 invocation.

This patch changes the spec command we use and updates
aarch64-common.c to handle that fact. I confess that the specs
stuff all looks like magic to me, but this approach seems to
make sense. In English, I think I am saying:

"If you find an mcpu= followed by some name, rewrite that to be
 -mcpu followed by the results of passing all other -mcpu values
 we find through aarch64_rewrite_mcpu"

I've regression tested this patch on aarch64-none-elf with no
issues and checked combinations of zero or more -mcpu values with
one or more source files, and things seem to work as expected.

OK?

Thanks,
James

---
2014-01-21  James Greenhalgh  <james.greenhalgh@arm.com>

	* common/config/aarch64/aarch64-common.c
	(aarch64_rewrite_mcpu): Handle multiple names.
	* config/aarch64/aarch64.h
	(BIG_LITTLE_SPEC): Do not discard mcpu switches.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-AArch64-fix-big.LITTLE-spec-rewriting.patch --]
[-- Type: text/x-patch;  name=0001-AArch64-fix-big.LITTLE-spec-rewriting.patch, Size: 1522 bytes --]

diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c
index 6107007..e44b40a 100644
--- a/gcc/common/config/aarch64/aarch64-common.c
+++ b/gcc/common/config/aarch64/aarch64-common.c
@@ -110,13 +110,15 @@ aarch64_rewrite_selected_cpu (const char *name)
 
 /* Called by the driver to rewrite a name passed to the -mcpu
    argument in preparation to be passed to the assembler.  The
-   name will be in ARGV[0], ARGC should always be 1.  */
+   names passed from the commend line will be in ARGV, we want
+   to use the right-most argument, which should be in
+   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
 
 const char *
 aarch64_rewrite_mcpu (int argc, const char **argv)
 {
-  gcc_assert (argc == 1);
-  return aarch64_rewrite_selected_cpu (argv[0]);
+  gcc_assert (argc);
+  return aarch64_rewrite_selected_cpu (argv[argc - 1]);
 }
 
 #undef AARCH64_CPU_NAME_LENGTH
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index a08dee0..13c424c 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -857,7 +857,7 @@ extern enum aarch64_code_model aarch64_cmodel;
   (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
 
 #define BIG_LITTLE_SPEC \
-   " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
+   " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
 
 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \

[ARM] fix big.LITTLE spec rewriting

[James Greenhalgh]

[-- Attachment #1: Type: text/plain, Size: 822 bytes --]


Hi,

As with the AArch64 case,
( http://gcc.gnu.org/ml/gcc-patches/2014-01/msg01317.html )
the way that we rewrite command lines for big.LITTLE systems
causes bugs where more than one source file is to be used.

The solution here is identical to that proposed for AArch64,
we update the spec command and compensate for that with an
change to arm_rewrite_mcpu to handle multiple names.

The patch has been bootstrapped on a chromebook, and I've
checked combinations of zero or more -mcpu values with
one or more source files, and things seem to work as expected.

OK?

Thanks,
James

---
2014-01-21  James Greenhalgh  <james.greenhalgh@arm.com>

	* common/config/arm/arm-common.c
	(arm_rewrite_mcpu): Handle multiple names.
	* config/arm/arm.h
	(BIG_LITTLE_SPEC): Do not discard mcpu switches.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-ARM-fix-big.LITTLE-spec-rewriting.patch --]
[-- Type: text/x-patch;  name=0001-ARM-fix-big.LITTLE-spec-rewriting.patch, Size: 1388 bytes --]

diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index 065de7d..8ef8d83 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -86,13 +86,15 @@ arm_rewrite_selected_cpu (const char *name)
 
 /* Called by the driver to rewrite a name passed to the -mcpu
    argument in preparation to be passed to the assembler.  The
-   name will be in ARGV[0], ARGC should always be 1.  */
+   names passed from the commend line will be in ARGV, we want
+   to use the right-most argument, which should be in
+   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
 
 const char *
 arm_rewrite_mcpu (int argc, const char **argv)
 {
-  gcc_assert (argc == 1);
-  return arm_rewrite_selected_cpu (argv[0]);
+  gcc_assert (argc);
+  return arm_rewrite_selected_cpu (argv[argc - 1]);
 }
 
 #undef ARM_CPU_NAME_LENGTH
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index b815488..bed056e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2356,7 +2356,7 @@ extern int making_const_table;
 #define MAX_LDM_STM_OPS 4
 
 #define BIG_LITTLE_SPEC \
-   " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" \
+   " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
 
 extern const char *arm_rewrite_mcpu (int argc, const char **argv);
 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \

Re: [AArch64] fix big.LITTLE spec rewriting

[James Greenhalgh]

*ping*

On Tue, Jan 21, 2014 at 10:48:04AM +0000, James Greenhalgh wrote:
> 
> Hi,
> 
> As Charles Baylis pointed out here:
> 
> http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00921.html
> 
> The way that we rewrite command lines for big.LITTLE systems
> causes bugs where more than one source file is to be used.
> The problem fundamentally is that -mcpu never makes it to
> the second cc1 invocation.
> 
> This patch changes the spec command we use and updates
> aarch64-common.c to handle that fact. I confess that the specs
> stuff all looks like magic to me, but this approach seems to
> make sense. In English, I think I am saying:
> 
> "If you find an mcpu= followed by some name, rewrite that to be
>  -mcpu followed by the results of passing all other -mcpu values
>  we find through aarch64_rewrite_mcpu"
> 
> I've regression tested this patch on aarch64-none-elf with no
> issues and checked combinations of zero or more -mcpu values with
> one or more source files, and things seem to work as expected.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2014-01-21  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* common/config/aarch64/aarch64-common.c
> 	(aarch64_rewrite_mcpu): Handle multiple names.
> 	* config/aarch64/aarch64.h
> 	(BIG_LITTLE_SPEC): Do not discard mcpu switches.
> 

> diff --git a/gcc/common/config/aarch64/aarch64-common.c b/gcc/common/config/aarch64/aarch64-common.c
> index 6107007..e44b40a 100644
> --- a/gcc/common/config/aarch64/aarch64-common.c
> +++ b/gcc/common/config/aarch64/aarch64-common.c
> @@ -110,13 +110,15 @@ aarch64_rewrite_selected_cpu (const char *name)
>  
>  /* Called by the driver to rewrite a name passed to the -mcpu
>     argument in preparation to be passed to the assembler.  The
> -   name will be in ARGV[0], ARGC should always be 1.  */
> +   names passed from the commend line will be in ARGV, we want
> +   to use the right-most argument, which should be in
> +   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
>  
>  const char *
>  aarch64_rewrite_mcpu (int argc, const char **argv)
>  {
> -  gcc_assert (argc == 1);
> -  return aarch64_rewrite_selected_cpu (argv[0]);
> +  gcc_assert (argc);
> +  return aarch64_rewrite_selected_cpu (argv[argc - 1]);
>  }
>  
>  #undef AARCH64_CPU_NAME_LENGTH
> diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
> index a08dee0..13c424c 100644
> --- a/gcc/config/aarch64/aarch64.h
> +++ b/gcc/config/aarch64/aarch64.h
> @@ -857,7 +857,7 @@ extern enum aarch64_code_model aarch64_cmodel;
>    (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
>  
>  #define BIG_LITTLE_SPEC \
> -   " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
> +   " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
>  
>  extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
>  #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \

Re: [ARM] fix big.LITTLE spec rewriting

[James Greenhalgh]

*Ping*

On Tue, Jan 21, 2014 at 10:52:14AM +0000, James Greenhalgh wrote:
> 
> Hi,
> 
> As with the AArch64 case,
> ( http://gcc.gnu.org/ml/gcc-patches/2014-01/msg01317.html )
> the way that we rewrite command lines for big.LITTLE systems
> causes bugs where more than one source file is to be used.
> 
> The solution here is identical to that proposed for AArch64,
> we update the spec command and compensate for that with an
> change to arm_rewrite_mcpu to handle multiple names.
> 
> The patch has been bootstrapped on a chromebook, and I've
> checked combinations of zero or more -mcpu values with
> one or more source files, and things seem to work as expected.
> 
> OK?
> 
> Thanks,
> James
> 
> ---
> 2014-01-21  James Greenhalgh  <james.greenhalgh@arm.com>
> 
> 	* common/config/arm/arm-common.c
> 	(arm_rewrite_mcpu): Handle multiple names.
> 	* config/arm/arm.h
> 	(BIG_LITTLE_SPEC): Do not discard mcpu switches.
> 

> diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
> index 065de7d..8ef8d83 100644
> --- a/gcc/common/config/arm/arm-common.c
> +++ b/gcc/common/config/arm/arm-common.c
> @@ -86,13 +86,15 @@ arm_rewrite_selected_cpu (const char *name)
>  
>  /* Called by the driver to rewrite a name passed to the -mcpu
>     argument in preparation to be passed to the assembler.  The
> -   name will be in ARGV[0], ARGC should always be 1.  */
> +   names passed from the commend line will be in ARGV, we want
> +   to use the right-most argument, which should be in
> +   ARGV[ARGC - 1].  ARGC should always be greater than 0.  */
>  
>  const char *
>  arm_rewrite_mcpu (int argc, const char **argv)
>  {
> -  gcc_assert (argc == 1);
> -  return arm_rewrite_selected_cpu (argv[0]);
> +  gcc_assert (argc);
> +  return arm_rewrite_selected_cpu (argv[argc - 1]);
>  }
>  
>  #undef ARM_CPU_NAME_LENGTH
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index b815488..bed056e 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -2356,7 +2356,7 @@ extern int making_const_table;
>  #define MAX_LDM_STM_OPS 4
>  
>  #define BIG_LITTLE_SPEC \
> -   " %{mcpu=*:%<mcpu=* -mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" \
> +   " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
>  
>  extern const char *arm_rewrite_mcpu (int argc, const char **argv);
>  #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \

Re: [AArch64] fix big.LITTLE spec rewriting

[Marcus Shawcroft]

On 21 January 2014 10:48, James Greenhalgh <james.greenhalgh@arm.com> wrote:

> 2014-01-21  James Greenhalgh  <james.greenhalgh@arm.com>
>
>         * common/config/aarch64/aarch64-common.c
>         (aarch64_rewrite_mcpu): Handle multiple names.
>         * config/aarch64/aarch64.h
>         (BIG_LITTLE_SPEC): Do not discard mcpu switches.

OK /Marcus

Re: [ARM] fix big.LITTLE spec rewriting

[Ramana Radhakrishnan]

On 21/01/14 10:52, James Greenhalgh wrote:
> +   names passed from the commend line will be in ARGV, we want

s/commend/command.


Otherwise OK if no regressions.


Thanks,
Ramana