From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27154 invoked by alias); 17 Dec 2013 10:41:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 27093 invoked by uid 89); 17 Dec 2013 10:41:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Dec 2013 10:41:25 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 17 Dec 2013 10:41:22 +0000 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 17 Dec 2013 10:41:21 +0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, ramana.radhakrishnan@arm.com Subject: [ARM 3/5 big.LITTLE] Add support for -mcpu=cortex-a15.cortex-a7 Date: Tue, 17 Dec 2013 10:41:00 -0000 Message-Id: <1387276843-21770-4-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1387276843-21770-1-git-send-email-james.greenhalgh@arm.com> References: <1387276843-21770-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113121710412214901 Content-Type: multipart/mixed; boundary="------------1.8.3-rc0" X-IsSubscribed: yes X-SW-Source: 2013-12/txt/msg01478.txt.bz2 This is a multi-part message in MIME format. --------------1.8.3-rc0 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 499 Hi, This patch wires up -mcpu=3Dcortex-a15.cortex-a7 as an option to -mcpu. Bootstrapped in series, with --with-cpu=3Dcortex-a15.cortex-a7. OK? Thanks, James --- 2013-12-17 James Greenhalgh * config/arm/arm-cores.def (cortex-a15.cortex-a7): New. * doc/invoke.texi: Document -mcpu=3Dcortex-a15.cortex-a7. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/bpabi.h (BE8_LINK_SPEC): Handle -mcpu=3Dcortex-a5.cortex-a7. --------------1.8.3-rc0 Content-Type: text/x-patch; name=0003-ARM-3-5-big.LITTLE-Add-support-for-mcpu-cortex-a15.c.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0003-ARM-3-5-big.LITTLE-Add-support-for-mcpu-cortex-a15.c.patch" Content-length: 3077 diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 3264eed..0ea5eef 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -148,5 +148,8 @@ ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDS= CHED, v7m) ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m) ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e) =20 +/* V7 big.LITTLE implementations */ +ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, FL_LDSC= HED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) + /* V8 Architecture Processors */ ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, FL_LDSCHED, cortex_a53) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 7da7cc8..d847c10 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -283,6 +283,9 @@ EnumValue Enum(processor_type) String(marvell-pj4) Value(marvell_pj4) =20 EnumValue +Enum(processor_type) String(cortex-a15.cortex-a7) Value(cortexa15cortexa7) + +EnumValue Enum(processor_type) String(cortex-a53) Value(cortexa53) =20 Enum diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 0386afff7428169ad0e31ae4de4bd677413bc817..beee9af013f6a5a75b7051f3c70= 77e98fafd45ef 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -29,5 +29,6 @@ (define_attr "tune" cortexa8,cortexa9,cortexa12, cortexa15,cortexr4,cortexr4f, cortexr5,cortexr7,cortexm4, - cortexm3,marvell_pj4,cortexa53" + cortexm3,marvell_pj4,cortexa15cortexa7, + cortexa53" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index b39c4a9..669884d 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -60,6 +60,7 @@ |mcpu=3Dcortex-a7 \ |mcpu=3Dcortex-a8|mcpu=3Dcortex-a9|mcpu=3Dcortex-a15 \ |mcpu=3Dcortex-a12 \ + |mcpu=3Dcortex-a15.cortex-a7 \ |mcpu=3Dmarvell-pj4 \ |mcpu=3Dcortex-a53 \ |mcpu=3Dgeneric-armv7-a \ @@ -74,6 +75,7 @@ |mcpu=3Dcortex-a7 \ |mcpu=3Dcortex-a8|mcpu=3Dcortex-a9|mcpu=3Dcortex-a15 \ |mcpu=3Dcortex-a12 \ + |mcpu=3Dcortex-a15.cortex-a7 \ |mcpu=3Dcortex-a53 \ |mcpu=3Dmarvell-pj4 \ |mcpu=3Dgeneric-armv7-a \ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b655a64..e069305 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12168,6 +12168,9 @@ assembly code. Permissible names are: @samp{arm2},= @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. =20 +Additionally, this option can specify that GCC should tune the performance +of the code for a big.LITTLE system. The only permissible name is: +@samp{cortex-a15.cortex-a7}. =20 @option{-mcpu=3Dgeneric-@var{arch}} is also permissible, and is equivalent to @option{-march=3D@var{arch} -mtune=3Dgeneric-@var{arch}}.= --------------1.8.3-rc0--