From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1946 invoked by alias); 18 Feb 2014 21:10:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 1586 invoked by uid 89); 18 Feb 2014 21:10:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00 autolearn=ham version=3.3.2 X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 18 Feb 2014 21:10:33 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WFrvr-00042j-Ma for gcc-patches@gcc.gnu.org; Tue, 18 Feb 2014 16:10:31 -0500 Received: from vegas.theobroma-systems.com ([144.76.126.164]:44191 helo=mail.theobroma-systems.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WFrvr-00041R-Gc for gcc-patches@gcc.gnu.org; Tue, 18 Feb 2014 16:10:23 -0500 Received: from [85.31.14.210] (port=52453 helo=android.com) by mail.theobroma-systems.com with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1WFrvk-0007JV-MI; Tue, 18 Feb 2014 22:10:16 +0100 From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: philipp.tomsich@theobroma-systems.com Subject: [AArch64 05/14] Add AArch64 'prefetch'-pattern. Date: Tue, 18 Feb 2014 21:10:00 -0000 Message-Id: <1392757787-25629-6-git-send-email-philipp.tomsich@theobroma-systems.com> In-Reply-To: <1392757787-25629-1-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1392757787-25629-1-git-send-email-philipp.tomsich@theobroma-systems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 144.76.126.164 X-SW-Source: 2014-02/txt/msg01075.txt.bz2 --- gcc/config/aarch64/aarch64.md | 17 +++++++++++++++++ gcc/config/arm/types.md | 2 ++ 2 files changed, 19 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 99a6ac8..b972a1b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -293,6 +293,23 @@ [(set_attr "type" "no_insn")] ) +(define_insn "prefetch" + [(prefetch (match_operand:DI 0 "register_operand" "r") + (match_operand:QI 1 "const_int_operand" "n") + (match_operand:QI 2 "const_int_operand" "n"))] + "" + "* +{ + if (INTVAL(operands[2]) == 0) + /* no temporal locality */ + return (INTVAL(operands[1])) ? \"prfm\\tPSTL1STRM, [%0, #0]\" : \"prfm\\tPLDL1STRM, [%0, #0]\"; + + /* temporal locality */ + return (INTVAL(operands[1])) ? \"prfm\\tPSTL1KEEP, [%0, #0]\" : \"prfm\\tPLDL1KEEP, [%0, #0]\"; +}" + [(set_attr "type" "prefetch")] +) + (define_insn "trap" [(trap_if (const_int 1) (const_int 8))] "" diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index cc39cd1..1d1280d 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -117,6 +117,7 @@ ; mvn_shift_reg inverting move instruction, shifted operand by a register. ; no_insn an insn which does not represent an instruction in the ; final output, thus having no impact on scheduling. +; prefetch a prefetch instruction ; rbit reverse bits. ; rev reverse bytes. ; sdiv signed division. @@ -553,6 +554,7 @@ call,\ clz,\ no_insn,\ + prefetch,\ csel,\ crc,\ extend,\ -- 1.9.0