From: Xi Ruoyao <xry111@mengyan1223.wang>
To: gcc-patches@gcc.gnu.org
Cc: "Martin Li�0�8ka" <marxin@gcc.gnu.org>,
"Matthew Fortune" <mfortune@gmail.com>,
"Maciej W. Rozycki" <macro@orcam.me.uk>,
"Richard Sandiford" <richard.sandiford@arm.com>,
xry111@mengyan1223.wang
Subject: PING^4: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132]
Date: Fri, 23 Jul 2021 20:46:43 +0800 [thread overview]
Message-ID: <13ee28a6944e6b04b292ddd3ed068b2df18566e7.camel@mengyan1223.wang> (raw)
In-Reply-To: <1c61137b2e714a8a45e2b078a79851acc2eb5b8c.camel@mengyan1223.wang>
Ping again.
On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote:
> Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
> ICE on MIPS with MSA enabled. Add the pattern to prevent it.
>
> Bootstrapped and regression tested on mips64el-linux-gnu.
> Ok for trunk?
>
> gcc/
>
> * config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Declare.
> * config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
> * config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
> expander.
> (vec_cmpu<IMSA:mode><mode_i>): New expander.
> ---
> gcc/config/mips/mips-msa.md | 22 ++++++++++++++++++++++
> gcc/config/mips/mips-protos.h | 1 +
> gcc/config/mips/mips.c | 11 +++++++++++
> 3 files changed, 34 insertions(+)
>
> diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
> index 3ecf2bde19f..3a67f25be56 100644
> --- a/gcc/config/mips/mips-msa.md
> +++ b/gcc/config/mips/mips-msa.md
> @@ -435,6 +435,28 @@
> DONE;
> })
>
> +(define_expand "vec_cmp<MSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:MSA 2 "register_operand")
> + (match_operand:MSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> +(define_expand "vec_cmpu<IMSA:mode><mode_i>"
> + [(match_operand:<VIMODE> 0 "register_operand")
> + (match_operator 1 ""
> + [(match_operand:IMSA 2 "register_operand")
> + (match_operand:IMSA 3 "register_operand")])]
> + "ISA_HAS_MSA"
> +{
> + mips_expand_vec_cmp_expr (operands);
> + DONE;
> +})
> +
> (define_insn "msa_insert_<msafmt_f>"
> [(set (match_operand:MSA 0 "register_operand" "=f,f")
> (vec_merge:MSA
> diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
> index 2cf4ed50292..a685f7f7dd5 100644
> --- a/gcc/config/mips/mips-protos.h
> +++ b/gcc/config/mips/mips-protos.h
> @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code);
>
> extern void mips_register_frame_header_opt (void);
> extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *);
> +extern void mips_expand_vec_cmp_expr (rtx *);
>
> /* Routines implemented in mips-d.c */
> extern void mips_d_target_versions (void);
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 00a8eef96aa..8f043399a8e 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1)
> }
> }
>
> +void
> +mips_expand_vec_cmp_expr (rtx *operands)
> +{
> + rtx cond = operands[1];
> + rtx op0 = operands[2];
> + rtx op1 = operands[3];
> + rtx res = operands[0];
> +
> + mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1);
> +}
> +
> /* Expand VEC_COND_EXPR, where:
> MODE is mode of the result
> VIMODE equivalent integer mode
--
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University
next prev parent reply other threads:[~2021-07-23 12:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 13:42 Xi Ruoyao
2021-07-01 8:11 ` Xi Ruoyao
2021-07-09 6:50 ` PING^2: " Xi Ruoyao
2021-07-16 5:57 ` PING^3: " Xi Ruoyao
2021-07-23 12:46 ` Xi Ruoyao [this message]
2021-07-30 4:56 ` PING^5: " Xi Ruoyao
2021-07-30 8:04 ` Richard Sandiford
2021-07-30 8:17 ` Xi Ruoyao
2021-07-30 18:06 ` committed: " Xi Ruoyao
2021-07-30 8:30 ` PING^5: " Richard Biener
2021-07-30 12:13 ` Maciej W. Rozycki
2021-07-30 15:57 ` Jeff Law
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