From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 97C0839AE84F; Fri, 23 Jul 2021 12:46:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 97C0839AE84F Received: from [192.168.124.4] (unknown [113.200.174.5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id 0D61365F07; Fri, 23 Jul 2021 08:46:45 -0400 (EDT) Message-ID: <13ee28a6944e6b04b292ddd3ed068b2df18566e7.camel@mengyan1223.wang> Subject: PING^4: [PATCH] mips: add MSA vec_cmp and vec_cmpu expand pattern [PR101132] From: Xi Ruoyao Reply-To: xry111@mengyan1223.wang To: gcc-patches@gcc.gnu.org Cc: Martin =?gb2312?Q?Li=810=948ka?= , Matthew Fortune , "Maciej W. Rozycki" , Richard Sandiford , xry111@mengyan1223.wang Date: Fri, 23 Jul 2021 20:46:43 +0800 In-Reply-To: <1c61137b2e714a8a45e2b078a79851acc2eb5b8c.camel@mengyan1223.wang> References: <1c61137b2e714a8a45e2b078a79851acc2eb5b8c.camel@mengyan1223.wang> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-3037.9 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Jul 2021 12:46:50 -0000 Ping again. On Mon, 2021-06-21 at 21:42 +0800, Xi Ruoyao wrote: > Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing > ICE on MIPS with MSA enabled.  Add the pattern to prevent it. > > Bootstrapped and regression tested on mips64el-linux-gnu. > Ok for trunk? > > gcc/ > >         * config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Declare. >         * config/mips/mips.c (mips_expand_vec_cmp_expr): New function. >         * config/mips/mips-msa.md (vec_cmp): New >           expander. >           (vec_cmpu): New expander. > --- >  gcc/config/mips/mips-msa.md   | 22 ++++++++++++++++++++++ >  gcc/config/mips/mips-protos.h |  1 + >  gcc/config/mips/mips.c        | 11 +++++++++++ >  3 files changed, 34 insertions(+) > > diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md > index 3ecf2bde19f..3a67f25be56 100644 > --- a/gcc/config/mips/mips-msa.md > +++ b/gcc/config/mips/mips-msa.md > @@ -435,6 +435,28 @@ >    DONE; >  }) >   > +(define_expand "vec_cmp" > +  [(match_operand: 0 "register_operand") > +   (match_operator 1 "" > +     [(match_operand:MSA 2 "register_operand") > +      (match_operand:MSA 3 "register_operand")])] > +  "ISA_HAS_MSA" > +{ > +  mips_expand_vec_cmp_expr (operands); > +  DONE; > +}) > + > +(define_expand "vec_cmpu" > +  [(match_operand: 0 "register_operand") > +   (match_operator 1 "" > +     [(match_operand:IMSA 2 "register_operand") > +      (match_operand:IMSA 3 "register_operand")])] > +  "ISA_HAS_MSA" > +{ > +  mips_expand_vec_cmp_expr (operands); > +  DONE; > +}) > + >  (define_insn "msa_insert_" >    [(set (match_operand:MSA 0 "register_operand" "=f,f") >         (vec_merge:MSA > diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h > index 2cf4ed50292..a685f7f7dd5 100644 > --- a/gcc/config/mips/mips-protos.h > +++ b/gcc/config/mips/mips-protos.h > @@ -385,6 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code); >   >  extern void mips_register_frame_header_opt (void); >  extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *); > +extern void mips_expand_vec_cmp_expr (rtx *); >   >  /* Routines implemented in mips-d.c  */ >  extern void mips_d_target_versions (void); > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > index 00a8eef96aa..8f043399a8e 100644 > --- a/gcc/config/mips/mips.c > +++ b/gcc/config/mips/mips.c > @@ -22321,6 +22321,17 @@ mips_expand_msa_cmp (rtx dest, enum rtx_code cond, rtx op0, rtx op1) >      } >  } >   > +void > +mips_expand_vec_cmp_expr (rtx *operands) > +{ > +  rtx cond = operands[1]; > +  rtx op0 = operands[2]; > +  rtx op1 = operands[3]; > +  rtx res = operands[0]; > + > +  mips_expand_msa_cmp (res, GET_CODE (cond), op0, op1); > +} > + >  /* Expand VEC_COND_EXPR, where: >     MODE is mode of the result >     VIMODE equivalent integer mode -- Xi Ruoyao School of Aerospace Science and Technology, Xidian University