From: Jeff Law <jeffreyalaw@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)
Date: Mon, 25 Mar 2024 14:49:18 -0600 [thread overview]
Message-ID: <13fe668d-7856-4881-8ff2-f7e91b3a72da@gmail.com> (raw)
In-Reply-To: <mhng-33bb8861-68a4-4319-a6fe-195f54692d48@palmer-ri-x1c9>
On 3/25/24 2:31 PM, Palmer Dabbelt wrote:
> On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote:
>> I'd doubt it's worth the complexity. Picking some reasonable value gets
>> you the vast majority of the benefit. Something like
>> COSTS_N_INSNS(6) is enough to get CSE to trigger. So what's left is a
>> reasonable cost, particularly for the division-by-constant case where we
>> need a ceiling for synth_mult.
>
> Ya, makes sense. I noticed our multi-word multiply costs are a bit odd
> too (they really only work for 64-bit mul on 32-bit targets), but that's
> probably not worth worrying about either.
We do have a changes locally that adjust various costs. One of which is
highpart multiply. One of the many things to start working through once
gcc-15 opens for development. Hence my desire to help keep gcc-14 on
track for an on-time release.
Jeff
next prev parent reply other threads:[~2024-03-25 20:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-27 8:52 [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture Jiawei
2024-03-19 2:54 ` Jeff Law
2024-03-19 12:43 ` jiawei
2024-03-25 19:48 ` TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.) Xi Ruoyao
2024-03-25 19:59 ` Jeff Law
2024-03-25 20:13 ` Palmer Dabbelt
2024-03-25 20:27 ` Jeff Law
2024-03-25 20:31 ` Palmer Dabbelt
2024-03-25 20:49 ` Jeff Law [this message]
2024-03-25 20:57 ` Palmer Dabbelt
2024-03-25 21:41 ` Jeff Law
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