[SH, committed] PR 54236 add another addc case

[SH, committed] PR 54236 add another addc case

[Oleg Endo]

[-- Attachment #1: Type: text/plain, Size: 519 bytes --]

Hi,

The attached patch adds another addc pattern in order to catch 'reg + T'
opportunities.
Tested on rev 210624 with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

and no new failures.
Committed as rev 210682.

Cheers,
Oleg

gcc/ChangeLog:
	PR target/54236
	* config/sh/sh.md (*addc_r_1): Rename to addc_t_r.  Remove empty
	constraints.
	(*addc_r_t): Add new insn_and_split.

testsuite/ChangeLog:
	PR target/54236
	* gcc.target/sh/pr54236-3.c: New.


[-- Attachment #2: sh_pr54236_5.patch --]
[-- Type: text/x-patch, Size: 2858 bytes --]

Index: gcc/testsuite/gcc.target/sh/pr54236-3.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pr54236-3.c	(revision 0)
+++ gcc/testsuite/gcc.target/sh/pr54236-3.c	(revision 0)
@@ -0,0 +1,31 @@
+/* Tests to check the utilization of the addc and subc instructions.
+   If everything works as expected we won't see any movt instructions in
+   these cases.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-times "addc" 1 } } */
+/* { dg-final { scan-assembler-times "subc" 1 } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+
+int
+test_000 (int* x, unsigned int c)
+{
+  /* 1x addc  */
+  int s = 0;
+  unsigned int i;
+  for (i = 0; i < c; ++i)
+    s += ! (x[i] & 0x3000);
+  return s;
+}
+
+int
+test_001 (int* x, unsigned int c)
+{
+  /* 1x subc  */
+  int s = 0;
+  unsigned int i;
+  for (i = 0; i < c; ++i)
+    s -= ! (x[i] & 0x3000);
+  return s;
+}
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 205675)
+++ gcc/config/sh/sh.md	(working copy)
@@ -1830,6 +1830,8 @@
 ;; We allow a reg or 0 for one of the operands in order to be able to
 ;; do 'reg + T' sequences.  Reload will load the constant 0 into the reg
 ;; as needed.
+;; FIXME: The load of constant 0 should be split out before reload, or else
+;; it will be difficult to hoist or combine the constant load.
 (define_insn "*addc"
   [(set (match_operand:SI 0 "arith_reg_dest" "=r")
 	(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
@@ -1898,10 +1900,10 @@
 ;; can be scheduled much better since the load of the constant can be
 ;; done earlier, before any comparison insns that store the result in
 ;; the T bit.
-(define_insn_and_split "*addc_r_1"
-  [(set (match_operand:SI 0 "arith_reg_dest" "")
-	(plus:SI (match_operand:SI 1 "t_reg_operand" "")
-		 (match_operand:SI 2 "arith_reg_operand" "")))
+(define_insn_and_split "*addc_t_r"
+  [(set (match_operand:SI 0 "arith_reg_dest")
+	(plus:SI (match_operand:SI 1 "t_reg_operand")
+		 (match_operand:SI 2 "arith_reg_operand")))
    (clobber (reg:SI T_REG))]
   "TARGET_SH1"
   "#"
@@ -1911,6 +1913,19 @@
 			    (match_dup 1)))
 	      (clobber (reg:SI T_REG))])])
 
+(define_insn_and_split "*addc_r_t"
+  [(set (match_operand:SI 0 "arith_reg_dest")
+	(plus:SI (match_operand:SI 1 "arith_reg_operand")
+		 (match_operand:SI 2 "t_reg_operand")))
+   (clobber (reg:SI T_REG))]
+  "TARGET_SH1"
+  "#"
+  "&& 1"
+  [(parallel [(set (match_dup 0)
+		   (plus:SI (plus:SI (match_dup 1) (const_int 0))
+			    (match_dup 2)))
+	      (clobber (reg:SI T_REG))])])
+
 ;; Use shlr-addc to do 'reg + (reg & 1)'.
 (define_insn_and_split "*addc_r_lsb"
   [(set (match_operand:SI 0 "arith_reg_dest")