From: Christophe Lyon <christophe.lyon@linaro.org>
To: gcc-patches@gcc.gnu.org
Subject: [Patch ARM-AArch64/testsuite v2 21/21] Add vuzp and vzip tests.
Date: Tue, 01 Jul 2014 10:07:00 -0000 [thread overview]
Message-ID: <1404209174-25364-22-git-send-email-christophe.lyon@linaro.org> (raw)
In-Reply-To: <1404209174-25364-1-git-send-email-christophe.lyon@linaro.org>
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 775257e..14f80a0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,10 @@
2014-06-30 Christophe Lyon <christophe.lyon@linaro.org>
+ * gcc.target/aarch64/neon-intrinsics/vuzp.c: New file.
+ * gcc.target/aarch64/neon-intrinsics/vzip.c: Likewise.
+
+2014-06-30 Christophe Lyon <christophe.lyon@linaro.org>
+
* gcc.target/aarch64/neon-intrinsics/vmul.c: New file.
2014-06-30 Christophe Lyon <christophe.lyon@linaro.org>
diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vuzp.c
new file mode 100644
index 0000000..53f875e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vuzp.c
@@ -0,0 +1,245 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results splitted in several chunks. */
+/* Chunk 0. */
+VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0,
+ 0xfffffff1 };
+VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5,
+ 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1600000, 0xc1500000 };
+
+/* Chunk 1. */
+VECT_VAR_DECL(expected1,int,8,8) [] = { 0x11, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,4) [] = { 0x22, 0x22, 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,8) [] = { 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,4) [] = { 0x66, 0x66, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,8) [] = { 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,4) [] = { 0x66, 0x66, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+VECT_VAR_DECL(expected1,int,8,16) [] = { 0x11, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,8) [] = { 0x22, 0x22, 0x22, 0x22,
+ 0x22, 0x22, 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,4) [] = { 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,16) [] = { 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
+ 0x66, 0x66, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,4) [] = { 0x77, 0x77, 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,16) [] = { 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
+ 0x66, 0x66, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
+ 0x42073333, 0x42073333 };
+
+#ifndef INSN_NAME
+#define INSN_NAME vuzp
+#define TEST_MSG "VUZP/VUZPQ"
+#endif
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* In this case, output variables are arrays of vectors. */
+#define DECL_VUZP(T1, W, N) \
+ VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
+ VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
+
+ /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result. */
+#define TEST_VUZP(INSN, Q, T1, T2, W, N) \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
+ memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ /* Overwrite "result" with the contents of "result_bis"[X]. */
+#define TEST_EXTRA_CHUNK(T1, W, N, X) \
+ memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ DECL_VARIABLE_ALL_VARIANTS(vector1);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+
+ /* We don't need 64 bits variants. */
+#define DECL_ALL_VUZP() \
+ DECL_VUZP(int, 8, 8); \
+ DECL_VUZP(int, 16, 4); \
+ DECL_VUZP(int, 32, 2); \
+ DECL_VUZP(uint, 8, 8); \
+ DECL_VUZP(uint, 16, 4); \
+ DECL_VUZP(uint, 32, 2); \
+ DECL_VUZP(poly, 8, 8); \
+ DECL_VUZP(poly, 16, 4); \
+ DECL_VUZP(float, 32, 2); \
+ DECL_VUZP(int, 8, 16); \
+ DECL_VUZP(int, 16, 8); \
+ DECL_VUZP(int, 32, 4); \
+ DECL_VUZP(uint, 8, 16); \
+ DECL_VUZP(uint, 16, 8); \
+ DECL_VUZP(uint, 32, 4); \
+ DECL_VUZP(poly, 8, 16); \
+ DECL_VUZP(poly, 16, 8); \
+ DECL_VUZP(float, 32, 4)
+
+ DECL_ALL_VUZP();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
+ VLOAD(vector1, buffer, , float, f, 32, 2);
+ VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+ /* Choose arbitrary initialization values. */
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , uint, u, 8, 8, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x66);
+ VDUP(vector2, , uint, u, 32, 2, 0x77);
+ VDUP(vector2, , poly, p, 8, 8, 0x55);
+ VDUP(vector2, , poly, p, 16, 4, 0x66);
+ VDUP(vector2, , float, f, 32, 2, 33.6f);
+
+ VDUP(vector2, q, int, s, 8, 16, 0x11);
+ VDUP(vector2, q, int, s, 16, 8, 0x22);
+ VDUP(vector2, q, int, s, 32, 4, 0x33);
+ VDUP(vector2, q, uint, u, 8, 16, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x66);
+ VDUP(vector2, q, uint, u, 32, 4, 0x77);
+ VDUP(vector2, q, poly, p, 8, 16, 0x55);
+ VDUP(vector2, q, poly, p, 16, 8, 0x66);
+ VDUP(vector2, q, float, f, 32, 4, 33.8f);
+
+#define TEST_ALL_VUZP(INSN) \
+ TEST_VUZP(INSN, , int, s, 8, 8); \
+ TEST_VUZP(INSN, , int, s, 16, 4); \
+ TEST_VUZP(INSN, , int, s, 32, 2); \
+ TEST_VUZP(INSN, , uint, u, 8, 8); \
+ TEST_VUZP(INSN, , uint, u, 16, 4); \
+ TEST_VUZP(INSN, , uint, u, 32, 2); \
+ TEST_VUZP(INSN, , poly, p, 8, 8); \
+ TEST_VUZP(INSN, , poly, p, 16, 4); \
+ TEST_VUZP(INSN, , float, f, 32, 2); \
+ TEST_VUZP(INSN, q, int, s, 8, 16); \
+ TEST_VUZP(INSN, q, int, s, 16, 8); \
+ TEST_VUZP(INSN, q, int, s, 32, 4); \
+ TEST_VUZP(INSN, q, uint, u, 8, 16); \
+ TEST_VUZP(INSN, q, uint, u, 16, 8); \
+ TEST_VUZP(INSN, q, uint, u, 32, 4); \
+ TEST_VUZP(INSN, q, poly, p, 8, 16); \
+ TEST_VUZP(INSN, q, poly, p, 16, 8); \
+ TEST_VUZP(INSN, q, float, f, 32, 4)
+
+#define TEST_ALL_EXTRA_CHUNKS() \
+ TEST_EXTRA_CHUNK(int, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(int, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 4, 1)
+
+ clean_results ();
+
+ /* Execute the tests. */
+ TEST_ALL_VUZP(INSN_NAME);
+
+ CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
+
+ TEST_ALL_EXTRA_CHUNKS();
+ CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vzip.c b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vzip.c
new file mode 100644
index 0000000..a1f1eee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/neon-intrinsics/vzip.c
@@ -0,0 +1,243 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results splitted in several chunks. */
+/* Chunk 0. */
+VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf4, 0x11, 0x11,
+ 0xf1, 0xf5, 0x11, 0x11 };
+VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff2,
+ 0x22, 0x22 };
+VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55,
+ 0xf1, 0xf5, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff2,
+ 0x66, 0x66 };
+VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf4, 0x55, 0x55,
+ 0xf1, 0xf5, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff2,
+ 0x66, 0x66 };
+VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf8, 0x11, 0x11,
+ 0xf1, 0xf9, 0x11, 0x11,
+ 0xf2, 0xfa, 0x11, 0x11,
+ 0xf3, 0xfb, 0x11, 0x11 };
+VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff4, 0x22, 0x22,
+ 0xfff1, 0xfff5, 0x22, 0x22 };
+VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff2,
+ 0x33, 0x33 };
+VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55,
+ 0xf1, 0xf9, 0x55, 0x55,
+ 0xf2, 0xfa, 0x55, 0x55,
+ 0xf3, 0xfb, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff4, 0x66, 0x66,
+ 0xfff1, 0xfff5, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff2,
+ 0x77, 0x77 };
+VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf8, 0x55, 0x55,
+ 0xf1, 0xf9, 0x55, 0x55,
+ 0xf2, 0xfa, 0x55, 0x55,
+ 0xf3, 0xfb, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff4, 0x66, 0x66,
+ 0xfff1, 0xfff5, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1600000,
+ 0x42073333, 0x42073333 };
+
+/* Chunk 1. */
+VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf2, 0xf6, 0x11, 0x11,
+ 0xf3, 0xf7, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff1, 0xfff3,
+ 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55,
+ 0xf3, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff1, 0xfff3,
+ 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf2, 0xf6, 0x55, 0x55,
+ 0xf3, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff3,
+ 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf4, 0xfc, 0x11, 0x11,
+ 0xf5, 0xfd, 0x11, 0x11,
+ 0xf6, 0xfe, 0x11, 0x11,
+ 0xf7, 0xff, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff2, 0xfff6, 0x22, 0x22,
+ 0xfff3, 0xfff7, 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff1, 0xfffffff3,
+ 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55,
+ 0xf5, 0xfd, 0x55, 0x55,
+ 0xf6, 0xfe, 0x55, 0x55,
+ 0xf7, 0xff, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
+ 0xfff3, 0xfff7, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff1, 0xfffffff3,
+ 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf4, 0xfc, 0x55, 0x55,
+ 0xf5, 0xfd, 0x55, 0x55,
+ 0xf6, 0xfe, 0x55, 0x55,
+ 0xf7, 0xff, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
+ 0xfff3, 0xfff7, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
+ 0x42073333, 0x42073333 };
+
+#ifndef INSN_NAME
+#define INSN_NAME vzip
+#define TEST_MSG "VZIP/VZIPQ"
+#endif
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* In this case, output variables are arrays of vectors. */
+#define DECL_VZIP(T1, W, N) \
+ VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
+ VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
+
+ /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result. */
+#define TEST_VZIP(INSN, Q, T1, T2, W, N) \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
+ memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ /* Overwrite "result" with the contents of "result_bis"[X]. */
+#define TEST_EXTRA_CHUNK(T1, W, N, X) \
+ memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ DECL_VARIABLE_ALL_VARIANTS(vector1);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+
+ /* We don't need 64 bits variants. */
+#define DECL_ALL_VZIP() \
+ DECL_VZIP(int, 8, 8); \
+ DECL_VZIP(int, 16, 4); \
+ DECL_VZIP(int, 32, 2); \
+ DECL_VZIP(uint, 8, 8); \
+ DECL_VZIP(uint, 16, 4); \
+ DECL_VZIP(uint, 32, 2); \
+ DECL_VZIP(poly, 8, 8); \
+ DECL_VZIP(poly, 16, 4); \
+ DECL_VZIP(float, 32, 2); \
+ DECL_VZIP(int, 8, 16); \
+ DECL_VZIP(int, 16, 8); \
+ DECL_VZIP(int, 32, 4); \
+ DECL_VZIP(uint, 8, 16); \
+ DECL_VZIP(uint, 16, 8); \
+ DECL_VZIP(uint, 32, 4); \
+ DECL_VZIP(poly, 8, 16); \
+ DECL_VZIP(poly, 16, 8); \
+ DECL_VZIP(float, 32, 4)
+
+ DECL_ALL_VZIP();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
+ VLOAD(vector1, buffer, , float, f, 32, 2);
+ VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+ /* Choose arbitrary initialization values. */
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , uint, u, 8, 8, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x66);
+ VDUP(vector2, , uint, u, 32, 2, 0x77);
+ VDUP(vector2, , poly, p, 8, 8, 0x55);
+ VDUP(vector2, , poly, p, 16, 4, 0x66);
+ VDUP(vector2, , float, f, 32, 2, 33.6f);
+
+ VDUP(vector2, q, int, s, 8, 16, 0x11);
+ VDUP(vector2, q, int, s, 16, 8, 0x22);
+ VDUP(vector2, q, int, s, 32, 4, 0x33);
+ VDUP(vector2, q, uint, u, 8, 16, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x66);
+ VDUP(vector2, q, uint, u, 32, 4, 0x77);
+ VDUP(vector2, q, poly, p, 8, 16, 0x55);
+ VDUP(vector2, q, poly, p, 16, 8, 0x66);
+ VDUP(vector2, q, float, f, 32, 4, 33.8f);
+
+#define TEST_ALL_VZIP(INSN) \
+ TEST_VZIP(INSN, , int, s, 8, 8); \
+ TEST_VZIP(INSN, , int, s, 16, 4); \
+ TEST_VZIP(INSN, , int, s, 32, 2); \
+ TEST_VZIP(INSN, , uint, u, 8, 8); \
+ TEST_VZIP(INSN, , uint, u, 16, 4); \
+ TEST_VZIP(INSN, , uint, u, 32, 2); \
+ TEST_VZIP(INSN, , poly, p, 8, 8); \
+ TEST_VZIP(INSN, , poly, p, 16, 4); \
+ TEST_VZIP(INSN, , float, f, 32, 2); \
+ TEST_VZIP(INSN, q, int, s, 8, 16); \
+ TEST_VZIP(INSN, q, int, s, 16, 8); \
+ TEST_VZIP(INSN, q, int, s, 32, 4); \
+ TEST_VZIP(INSN, q, uint, u, 8, 16); \
+ TEST_VZIP(INSN, q, uint, u, 16, 8); \
+ TEST_VZIP(INSN, q, uint, u, 32, 4); \
+ TEST_VZIP(INSN, q, poly, p, 8, 16); \
+ TEST_VZIP(INSN, q, poly, p, 16, 8); \
+ TEST_VZIP(INSN, q, float, f, 32, 4)
+
+#define TEST_ALL_EXTRA_CHUNKS() \
+ TEST_EXTRA_CHUNK(int, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(int, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 4, 1)
+
+ clean_results ();
+
+ /* Execute the tests. */
+ TEST_ALL_VZIP(INSN_NAME);
+
+ CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
+
+ TEST_ALL_EXTRA_CHUNKS();
+ CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+
+ return 0;
+}
--
1.8.3.2
next prev parent reply other threads:[~2014-07-01 10:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-01 10:07 [Patch ARM-AArch64/testsuite v2 00/21] Neon intrinsics executable tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 18/21] Add vld2/vld3/vld4 tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 01/21] Neon intrinsics execution tests initial framework Christophe Lyon
2014-07-03 11:06 ` Ramana Radhakrishnan
2014-07-03 21:04 ` Christophe Lyon
2014-07-10 10:12 ` Marcus Shawcroft
2014-07-11 10:41 ` Richard Earnshaw
2014-09-30 14:27 ` Christophe Lyon
2014-10-01 15:11 ` Marcus Shawcroft
2014-10-07 13:33 ` Christophe Lyon
2014-10-08 12:16 ` Ramana Radhakrishnan
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 06/21] Add unary saturating operators: vqabs and vqneg Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 11/21] Add vaddhn tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 16/21] Add vdup and vmov tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 14/21] Add vbsl tests Christophe Lyon
2014-07-01 10:07 ` Christophe Lyon [this message]
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 13/21] Add vaddw tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 19/21] Add vld2_lane, vld3_lane and vld4_lane Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 12/21] Add vaddl tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 15/21] Add vclz tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 04/21] Add comparison operators: vceq, vcge, vcgt, vcle and vclt Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 20/21] Add vmul tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 02/21] Add unary operators: vabs and vneg Christophe Lyon
2014-07-03 11:07 ` Ramana Radhakrishnan
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 08/21] Add vabal tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 05/21] Add comparison operators with floating-point operands: vcage, vcagt, vcale and cvalt Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 07/21] Add binary saturating operators: vqadd, vqsub Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 09/21] Add vabd tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 10/21] Add vabdl tests Christophe Lyon
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 03/21] Add binary operators: vadd, vand, vbic, veor, vorn, vorr, vsub Christophe Lyon
2014-07-03 11:08 ` Ramana Radhakrishnan
2014-07-01 10:07 ` [Patch ARM-AArch64/testsuite v2 17/21] Add vld1_dup tests Christophe Lyon
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