Index: gcc/config/mn10300/mn10300.c
===================================================================
--- gcc/config/mn10300/mn10300.c	(revision 214575)
+++ gcc/config/mn10300/mn10300.c	(working copy)
@@ -2742,21 +2742,21 @@
 }
 
 static inline bool
-is_load_insn (rtx insn)
+is_load_pat (rtx pat)
 {
-  if (GET_CODE (PATTERN (insn)) != SET)
+  if (GET_CODE (pat) != SET)
     return false;
 
-  return MEM_P (SET_SRC (PATTERN (insn)));
+  return MEM_P (SET_SRC (pat));
 }
 
 static inline bool
-is_store_insn (rtx insn)
+is_store_pat (rtx pat)
 {
-  if (GET_CODE (PATTERN (insn)) != SET)
+  if (GET_CODE (pat) != SET)
     return false;
 
-  return MEM_P (SET_DEST (PATTERN (insn)));
+  return MEM_P (SET_DEST (pat));
 }
 
 /* Update scheduling costs for situations that cannot be
@@ -2768,33 +2768,38 @@
 static int
 mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
 {
+  rtx insn_pat;
+  rtx dep_pat;
+
   int timings = get_attr_timings (insn);
 
   if (!TARGET_AM33)
     return 1;
 
-  if (GET_CODE (insn) == PARALLEL)
-    insn = XVECEXP (insn, 0, 0);
+  insn_pat = PATTERN (insn);
+  if (GET_CODE (insn_pat) == PARALLEL)
+    insn_pat = XVECEXP (insn_pat, 0, 0);
 
-  if (GET_CODE (dep) == PARALLEL)
-    dep = XVECEXP (dep, 0, 0);
+  dep_pat = PATTERN (dep);
+  if (GET_CODE (dep_pat) == PARALLEL)
+    dep_pat = XVECEXP (dep_pat, 0, 0);
 
   /* For the AM34 a load instruction that follows a
      store instruction incurs an extra cycle of delay.  */
   if (mn10300_tune_cpu == PROCESSOR_AM34
-      && is_load_insn (dep)
-      && is_store_insn (insn))
+      && is_load_pat (dep_pat)
+      && is_store_pat (insn_pat))
     cost += 1;
 
   /* For the AM34 a non-store, non-branch FPU insn that follows
      another FPU insn incurs a one cycle throughput increase.  */
   else if (mn10300_tune_cpu == PROCESSOR_AM34
-      && ! is_store_insn (insn)
+      && ! is_store_pat (insn_pat)
       && ! JUMP_P (insn)
-      && GET_CODE (PATTERN (dep)) == SET
-      && GET_CODE (PATTERN (insn)) == SET
-      && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT
-      && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
+      && GET_CODE (dep_pat) == SET
+      && GET_CODE (insn_pat) == SET
+      && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_pat))) == MODE_FLOAT
+      && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_pat))) == MODE_FLOAT)
     cost += 1;
 
   /*  Resolve the conflict described in section 1-7-4 of
@@ -2816,20 +2821,20 @@
     return cost;
 
   /* Check that the instruction about to scheduled is an FPU instruction.  */
-  if (GET_CODE (PATTERN (dep)) != SET)
+  if (GET_CODE (dep_pat) != SET)
     return cost;
 
-  if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT)
+  if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_pat))) != MODE_FLOAT)
     return cost;
 
   /* Now check to see if the previous instruction is a load or store.  */
-  if (! is_load_insn (insn) && ! is_store_insn (insn))
+  if (! is_load_pat (insn_pat) && ! is_store_pat (insn_pat))
     return cost;
 
   /* XXX: Verify: The text of 1-7-4 implies that the restriction
      only applies when an INTEGER load/store precedes an FPU
      instruction, but is this true ?  For now we assume that it is.  */
-  if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
+  if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_pat))) != MODE_INT)
     return cost;
 
   /* Extract the latency value from the timings attribute.  */