From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19977 invoked by alias); 25 Sep 2014 15:05:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 19965 invoked by uid 89); 25 Sep 2014 15:05:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 25 Sep 2014 15:05:53 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 25 Sep 2014 16:05:50 +0100 Received: from e106375-lin.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 25 Sep 2014 16:05:49 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: rth@redhat.com, marcus.shawcroft@arm.com Subject: Re: [AArch64] Tighten predicates on SIMD shift intrinsics Date: Thu, 25 Sep 2014 15:05:00 -0000 Message-Id: <1411657518-25872-1-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <541C6062.5080702@redhat.com> References: <541C6062.5080702@redhat.com> MIME-Version: 1.0 X-MC-Unique: 114092516055004001 Content-Type: multipart/mixed; boundary="------------1.8.3-rc0" X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg02272.txt.bz2 This is a multi-part message in MIME format. --------------1.8.3-rc0 Content-Type: text/plain; charset=UTF-8; format=fixed Content-Transfer-Encoding: quoted-printable Content-length: 2100 On Fri, Sep 19, 2014 at 05:57:06PM +0100, Richard Henderson wrote: > On 09/11/2014 01:29 AM, James Greenhalgh wrote: > > +;; Predicates used by the various SIMD shift operations. These > > +;; fall in to 3 categories. > > +;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) > > +;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) > > +;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) > > +(define_predicate "aarch64_simd_shift_imm_qi" > > + (and (match_code "const_int") > > + (match_test "aarch64_simd_const_bounds (op, 0, 7)"))) > > The function call should be removed and this should be written as > > (match_test "IN_RANGE (ival, 0, 7)") > Quite right, updated as attached. Cross-tested for aarch64-none-elf with no issues. OK? Thanks, James --- gcc/ 2014-09-25 James Greenhalgh * config/aarch64/aarch64-protos.h (aarch64_simd_const_bounds): Delete. * config/aarch64/aarch64-simd.md (aarch64_qshl): Use new predicates. (aarch64_shll2_n): Likewise. (aarch64_shr_n): Likewise. (aarch64_sra_n: Likewise. (aarch64_si_n): Likewise. (aarch64_qshl_n): Likewise. * config/aarch64/aarch64.c (aarch64_simd_const_bounds): Delete. * config/aarch64/iterators.md (ve_mode): New. (offsetlr): Remap to infix text for use in new predicates. * config/aarch64/predicates.md (aarch64_simd_shift_imm_qi): New. (aarch64_simd_shift_imm_hi): Likewise. (aarch64_simd_shift_imm_si): Likewise. (aarch64_simd_shift_imm_di): Likewise. (aarch64_simd_shift_imm_offset_qi): Likewise. (aarch64_simd_shift_imm_offset_hi): Likewise. (aarch64_simd_shift_imm_offset_si): Likewise. (aarch64_simd_shift_imm_offset_di): Likewise. (aarch64_simd_shift_imm_bitsize_qi): Likewise. (aarch64_simd_shift_imm_bitsize_hi): Likewise. (aarch64_simd_shift_imm_bitsize_si): Likewise. (aarch64_simd_shift_imm_bitsize_di): Likewise. gcc/testsuite/ 2014-09-25 James Greenhalgh * gcc.target/aarch64/simd/vqshlb_1.c: New. --------------1.8.3-rc0 Content-Type: text/x-patch; name=0001-Re-AArch64-Tighten-predicates-on-SIMD-shift-intrinsi.patch Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="0001-Re-AArch64-Tighten-predicates-on-SIMD-shift-intrinsi.patch" Content-length: 10552 diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch= 64-protos.h index e32ef64..b5f53d2 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -256,7 +256,6 @@ void aarch64_emit_call_insn (rtx); /* Initialize builtins for SIMD intrinsics. */ void init_aarch64_simd_builtins (void); =20 -void aarch64_simd_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); void aarch64_simd_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); =20 /* Emit code to place a AdvSIMD pair result in memory locations (with equal diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch6= 4-simd.md index 45ea9d7895e93d4c4b137de1c01f6a1e93942d11..cab26a341ecefb65b81d13d066b= 349d3be354616 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3607,12 +3607,12 @@ (define_insn "aarch64_qshl (define_insn "aarch64_shll_n" [(set (match_operand: 0 "register_operand" "=3Dw") (unspec: [(match_operand:VDW 1 "register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] + (match_operand:SI 2 + "aarch64_simd_shift_imm_bitsize_" "i")] VSHLL))] "TARGET_SIMD" "* int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); if (INTVAL (operands[2]) =3D=3D bit_width) { return \"shll\\t%0., %1., %2\"; @@ -3633,7 +3633,6 @@ (define_insn "aarch64_shll2_n "TARGET_SIMD" "* int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[2], 0, bit_width + 1); if (INTVAL (operands[2]) =3D=3D bit_width) { return \"shll2\\t%0., %1., %2\"; @@ -3649,13 +3648,11 @@ (define_insn "aarch64_shll2_n (define_insn "aarch64_shr_n" [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=3Dw") (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "= w") - (match_operand:SI 2 "immediate_operand" "i")] + (match_operand:SI 2 + "aarch64_simd_shift_imm_offset_" "i")] VRSHR_N))] "TARGET_SIMD" - "* - int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); - return \"shr\\t%0, %1, %2\";" + "shr\\t%0, %1, %2" [(set_attr "type" "neon_sat_shift_imm")] ) =20 @@ -3665,13 +3662,11 @@ (define_insn "aarch64_sra_n" [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=3Dw") (unspec:VSDQ_I_DI [(match_operand:VSDQ_I_DI 1 "register_operand" "0") (match_operand:VSDQ_I_DI 2 "register_operand" "w") - (match_operand:SI 3 "immediate_operand" "i")] + (match_operand:SI 3 + "aarch64_simd_shift_imm_offset_" "i")] VSRA))] "TARGET_SIMD" - "* - int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[3], 1, bit_width + 1); - return \"sra\\t%0, %2, %3\";" + "sra\\t%0, %2, %3" [(set_attr "type" "neon_shift_acc")] ) =20 @@ -3681,14 +3676,11 @@ (define_insn "aarch64_si_n" "i")] VSLRI))] "TARGET_SIMD" - "* - int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[3], 1 - , - bit_width - + 1); - return \"si\\t%0, %2, %3\";" + "si\\t%0, %2, %3" [(set_attr "type" "neon_shift_imm")] ) =20 @@ -3697,13 +3689,11 @@ (define_insn "aarch64_si_nqshl_n" [(set (match_operand:VSDQ_I 0 "register_operand" "=3Dw") (unspec:VSDQ_I [(match_operand:VSDQ_I 1 "register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] + (match_operand:SI 2 + "aarch64_simd_shift_imm_" "i")] VQSHL_N))] "TARGET_SIMD" - "* - int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[2], 0, bit_width); - return \"qshl\\t%0, %1, %2\";" + "qshl\\t%0, %1, %2" [(set_attr "type" "neon_sat_shift_imm")] ) =20 @@ -3713,13 +3703,11 @@ (define_insn "aarch64_qshl_nqshrn_n" [(set (match_operand: 0 "register_operand" "=3Dw") (unspec: [(match_operand:VSQN_HSDI 1 "register_operand" = "w") - (match_operand:SI 2 "immediate_operand" "i")] + (match_operand:SI 2 + "aarch64_simd_shift_imm_offset_" "i")] VQSHRN_N))] "TARGET_SIMD" - "* - int bit_width =3D GET_MODE_UNIT_SIZE (mode) * BITS_PER_UNIT; - aarch64_simd_const_bounds (operands[2], 1, bit_width + 1); - return \"qshrn\\t%0, %1, %2\";" + "qshrn\\t%0, %1, %2" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] ) =20 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3483081..dc6a754 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -7975,16 +7975,6 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT= low, HOST_WIDE_INT high) error ("lane out of range"); } =20 -void -aarch64_simd_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT h= igh) -{ - gcc_assert (CONST_INT_P (operand)); - HOST_WIDE_INT lane =3D INTVAL (operand); - - if (lane < low || lane >=3D high) - error ("constant out of range"); -} - /* Emit code to place a AdvSIMD pair result in memory locations (with equal registers). */ void diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators= .md index daa5d9f70963208bec31f749e760b7324f579513..efd006f83619405190400ddd0c8= 9834208e15480 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -538,6 +538,14 @@ (define_mode_attr v_cmp_result [(V8QI "v (V2DF "v2di") (DF "di") (SF "si")]) =20 +;; Lower case element modes (as used in shift immediate patterns). +(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") + (V4HI "hi") (V8HI "hi") + (V2SI "si") (V4SI "si") + (DI "di") (V2DI "di") + (QI "qi") (HI "hi") + (SI "si")]) + ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") (V2SI "w") (V4SI "w") (SI "w")]) @@ -1007,8 +1015,9 @@ (define_int_attr addsub [(UNSPEC_SHADD " (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")]) =20 -(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") - (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) +(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") + (UNSPEC_SSRI "offset_") + (UNSPEC_USRI "offset_")]) =20 ;; Standard pattern names for floating-point rounding instructions. (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicat= es.md index 8191169e89b1eaf04c00ea709af70412d2cee361..d5b0b2a9d8dd8215a193e7fd8f4= addb319f2f2a6 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -279,3 +279,56 @@ (define_special_predicate "aarch64_simd_ { return aarch64_const_vec_all_same_int_p (op, -1); }) + +;; Predicates used by the various SIMD shift operations. These +;; fall in to 3 categories. +;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm) +;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset) +;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize) +(define_predicate "aarch64_simd_shift_imm_qi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) + +(define_predicate "aarch64_simd_shift_imm_hi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) + +(define_predicate "aarch64_simd_shift_imm_si" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) + +(define_predicate "aarch64_simd_shift_imm_di" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) + +(define_predicate "aarch64_simd_shift_imm_offset_qi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 8)"))) + +(define_predicate "aarch64_simd_shift_imm_offset_hi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 16)"))) + +(define_predicate "aarch64_simd_shift_imm_offset_si" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 32)"))) + +(define_predicate "aarch64_simd_shift_imm_offset_di" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 1, 64)"))) + +(define_predicate "aarch64_simd_shift_imm_bitsize_qi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 8)"))) + +(define_predicate "aarch64_simd_shift_imm_bitsize_hi" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 16)"))) + +(define_predicate "aarch64_simd_shift_imm_bitsize_si" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 32)"))) + +(define_predicate "aarch64_simd_shift_imm_bitsize_di" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 64)"))) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqshlb_1.c b/gcc/testsui= te/gcc.target/aarch64/simd/vqshlb_1.c new file mode 100644 index 0000000..ae741de --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vqshlb_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-options "-O3" } */ + +#include "arm_neon.h" + +extern void abort (); + +int +main (int argc, char **argv) +{ + int8_t arg1 =3D -1; + int8_t arg2 =3D 127; + int8_t exp =3D -128; + int8_t got =3D vqshlb_s8 (arg1, arg2); + + if (exp !=3D got) + abort (); + + return 0; +} += --------------1.8.3-rc0--