From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29403 invoked by alias); 12 Oct 2014 22:46:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 29307 invoked by uid 89); 12 Oct 2014 22:46:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,FROM_LOCAL_NOVOWEL,HK_RANDOM_ENVFROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f48.google.com Received: from mail-la0-f48.google.com (HELO mail-la0-f48.google.com) (209.85.215.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Sun, 12 Oct 2014 22:46:26 +0000 Received: by mail-la0-f48.google.com with SMTP id gi9so5864463lab.35 for ; Sun, 12 Oct 2014 15:46:23 -0700 (PDT) X-Received: by 10.112.161.135 with SMTP id xs7mr19845162lbb.13.1413153983238; Sun, 12 Oct 2014 15:46:23 -0700 (PDT) Received: from octofox.metropolis ([5.19.183.212]) by mx.google.com with ESMTPSA id ad3sm3991662lbc.45.2014.10.12.15.46.21 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Oct 2014 15:46:22 -0700 (PDT) From: Max Filippov To: gcc-patches@gcc.gnu.org Cc: Sterling Augustine , Marc Gauthier , Max Filippov Subject: [PATCH 2/2] xtensa: use pre- and postincrement FP load/store when available Date: Sun, 12 Oct 2014 23:19:00 -0000 Message-Id: <1413153962-2519-3-git-send-email-jcmvbkbc@gmail.com> In-Reply-To: <1413153962-2519-1-git-send-email-jcmvbkbc@gmail.com> References: <1413153962-2519-1-git-send-email-jcmvbkbc@gmail.com> X-IsSubscribed: yes X-SW-Source: 2014-10/txt/msg01087.txt.bz2 Earlier versions of xtensa FPU used to support preincrement FP load and store instructions (lsiu/ssiu). Recent FPU supports postincrement FP load and store instructions only (lsip/ssip). Use configuration macro to decide which version is available. 2014-10-10 Max Filippov gcc/ * config/xtensa/xtensa.h (TARGET_HARD_FLOAT_POSTINC): new macro. * config/xtensa/xtensa.md (*lsiu, *ssiu): add dependency on !TARGET_HARD_FLOAT_POSTINC. (*lsip, *ssip): new instructions. --- gcc/config/xtensa/xtensa.h | 4 ++++ gcc/config/xtensa/xtensa.md | 36 ++++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index c4a8f88..54bfea4 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -39,6 +39,9 @@ extern unsigned xtensa_current_frame_size; #ifndef XCHAL_HAVE_THREADPTR #define XCHAL_HAVE_THREADPTR 0 #endif +#ifndef XCHAL_HAVE_FP_POSTINC +#define XCHAL_HAVE_FP_POSTINC 0 +#endif #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE #define TARGET_DENSITY XCHAL_HAVE_DENSITY #define TARGET_MAC16 XCHAL_HAVE_MAC16 @@ -55,6 +58,7 @@ extern unsigned xtensa_current_frame_size; #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT +#define TARGET_HARD_FLOAT_POSTINC XCHAL_HAVE_FP_POSTINC #define TARGET_ABS XCHAL_HAVE_ABS #define TARGET_ADDX XCHAL_HAVE_ADDX #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 0e3f033..b8acebb 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -922,7 +922,7 @@ (match_operand:SI 2 "fpmem_offset_operand" "i")))) (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC" { if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn))) output_asm_insn ("memw", operands); @@ -938,7 +938,7 @@ (match_operand:SF 2 "register_operand" "f")) (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC" { if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn))) output_asm_insn ("memw", operands); @@ -948,6 +948,38 @@ (set_attr "mode" "SF") (set_attr "length" "3")]) +(define_insn "*lsip" + [(set (match_operand:SF 0 "register_operand" "=f") + (mem:SF (match_operand:SI 1 "register_operand" "+a"))) + (set (match_dup 1) + (plus:SI (match_dup 1) + (match_operand:SI 2 "fpmem_offset_operand" "i")))] + "TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC" +{ + if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn))) + output_asm_insn ("memw", operands); + return "lsip\t%0, %1, %2"; +} + [(set_attr "type" "fload") + (set_attr "mode" "SF") + (set_attr "length" "3")]) + +(define_insn "*ssip" + [(set (mem:SF (match_operand:SI 0 "register_operand" "+a")) + (match_operand:SF 1 "register_operand" "f")) + (set (match_dup 0) + (plus:SI (match_dup 0) + (match_operand:SI 2 "fpmem_offset_operand" "i")))] + "TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC" +{ + if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn))) + output_asm_insn ("memw", operands); + return "ssip\t%1, %0, %2"; +} + [(set_attr "type" "fstore") + (set_attr "mode" "SF") + (set_attr "length" "3")]) + ;; 64-bit floating point moves (define_expand "movdf" -- 1.8.1.4