From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12467 invoked by alias); 9 Dec 2014 15:28:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 12331 invoked by uid 89); 9 Dec 2014 15:28:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f176.google.com Received: from mail-wi0-f176.google.com (HELO mail-wi0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 09 Dec 2014 15:28:03 +0000 Received: by mail-wi0-f176.google.com with SMTP id ex7so8254814wid.3 for ; Tue, 09 Dec 2014 07:28:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=MhjHOlYVtuxa3FAVGpF9evIQdfV1V3g7sHQiTKUcsVM=; b=bP1zg2BRXiB3H4FBtwwgERPy7A4JAofryr35kNnuxiYHWNeJOa+o4lM5AHk8a6lD/u 5N7cBAUwjdL+ogg7Yy5O4wMK29ID/HpAbaDYtKGwvJBPEK79P/SfYs9OCVE0TvSiUE5h gzeek6HxsDFjR7HIXJKiaTKH1qwlnZwLYSbTtAo/0lmzo9uc4kdB49eUGRC44+2CZAm1 8DRCVIpW1YYcqbFnpxBuydqBaVohktnlupppKZreqcC7cQlDjBgI8Ffr/ZaBLh1YV75b 3pbR5xPw9t7YP45L8czrlj+tgFBso3dBRL/JmpviKhTdwb02pTNyKNs6tKLJnTqji523 /C2g== X-Gm-Message-State: ALoCoQn6LopgheXicawfKaOBmaEfQBJ0rVSnXv2FZKrKdcezBnN1s8lzNQJPCJVjXgYa3QJPaU8g X-Received: by 10.180.95.97 with SMTP id dj1mr5164331wib.43.1418138880313; Tue, 09 Dec 2014 07:28:00 -0800 (PST) Received: from sale.linaroharston ([81.128.185.34]) by mx.google.com with ESMTPSA id jp3sm14246558wid.9.2014.12.09.07.27.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 Dec 2014 07:27:59 -0800 (PST) From: charles.baylis@linaro.org To: rearnsha@arm.com, gcc-patches@gcc.gnu.org, marcus.shawcroft@arm.com, tejas.belagod@arm.com, alan.lawrence@arm.com Subject: [PATCH 2/4] vldN_lane error message enhancements (D registers) Date: Tue, 09 Dec 2014 15:28:00 -0000 Message-Id: <1418138874-13285-3-git-send-email-charles.baylis@linaro.org> In-Reply-To: <1418138874-13285-1-git-send-email-charles.baylis@linaro.org> References: <1418138874-13285-1-git-send-email-charles.baylis@linaro.org> X-IsSubscribed: yes X-SW-Source: 2014-12/txt/msg00797.txt.bz2 From: Charles Baylis gcc/ChangeLog Charles Baylis * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Add explicit lane bounds check. (__LD3_LANE_FUNC): Likewise. (__LD4_LANE_FUNC): Likewise gcc/testsuite/ChangeLog: Charles Baylis * gcc.target/aarch64/simd/vld4_lane.c: New test. Change-Id: Ia95fbed34b50cf710ea9032ff3428a5f1432e0aa --- gcc/config/aarch64/arm_neon.h | 6 ++++++ gcc/testsuite/gcc.target/aarch64/simd/vld4_lane.c | 15 +++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vld4_lane.c diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 8cff719..22df564 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -17901,6 +17901,8 @@ vld2_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ __o = __builtin_aarch64_set_qregoi##mode (__o, \ (signedtype) __temp.val[1], \ 1); \ + __builtin_aarch64_im_lane_boundsi (__c, \ + sizeof (vectype) / sizeof (*__ptr)); \ __o = __builtin_aarch64_ld2_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregoidi (__o, 0); \ @@ -17991,6 +17993,8 @@ vld3_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ __o = __builtin_aarch64_set_qregci##mode (__o, \ (signedtype) __temp.val[2], \ 2); \ + __builtin_aarch64_im_lane_boundsi (__c, \ + sizeof (vectype) / sizeof (*__ptr)); \ __o = __builtin_aarch64_ld3_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregcidi (__o, 0); \ @@ -18089,6 +18093,8 @@ vld4_lane_##funcsuffix (const ptrtype * __ptr, intype __b, const int __c) \ __o = __builtin_aarch64_set_qregxi##mode (__o, \ (signedtype) __temp.val[3], \ 3); \ + __builtin_aarch64_im_lane_boundsi (__c, \ + sizeof (vectype) / sizeof (*__ptr)); \ __o = __builtin_aarch64_ld4_lane##mode ( \ (__builtin_aarch64_simd_##ptrmode *) __ptr, __o, __c); \ __b.val[0] = (vectype) __builtin_aarch64_get_dregxidi (__o, 0); \ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane.c b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane.c new file mode 100644 index 0000000..d14e6c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vld4_lane.c @@ -0,0 +1,15 @@ +/* Test error message when passing an invalid value as a lane index. */ + +/* { dg-do compile } */ + +#include + +int8x8x4_t +f_vld4_lane (int8_t * p, int8x8x4_t v) +{ + int8x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */ + res = vld4_lane_s8 (p, v, 8); + return res; +} + -- 1.9.1