* [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (26 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
` (8 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
new file mode 100644
index 0000000..978cd9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
@@ -0,0 +1,104 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffface0, 0xffffb212 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b66666, 0xc3ab0000 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc,
+ 0xffd0, 0xffd4, 0xffd8, 0xffdc };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffde0, 0xfffffe02,
+ 0xfffffe24, 0xfffffe46 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c,
+ 0xccd0, 0xd114, 0xd558, 0xd99c };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffface0, 0xffffb212,
+ 0xffffb744, 0xffffbc76 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc3b66666, 0xc3ab0000,
+ 0xc39f9999, 0xc3943333 };
+
+#define TEST_MSG "VMUL_LANE"
+void exec_vmul_lane (void)
+{
+#define DECL_VMUL(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, uint, 32, 4); \
+ DECL_VARIABLE(VAR, float, 32, 4)
+
+ /* vector_res = vmul_lane(vector,vector2,lane), then store the result. */
+#define TEST_VMUL_LANE(Q, T1, T2, W, N, N2, L) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vmul##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N2), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VMUL(vector);
+ DECL_VMUL(vector_res);
+
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+ DECL_VARIABLE(vector2, float, 32, 2);
+
+ clean_results ();
+
+ /* Initialize vector from pre-initialized values. */
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x4);
+ VDUP(vector2, , int, s, 32, 2, 0x22);
+ VDUP(vector2, , uint, u, 16, 4, 0x444);
+ VDUP(vector2, , uint, u, 32, 2, 0x532);
+ VDUP(vector2, , float, f, 32, 2, 22.8f);
+
+ /* Choose lane arbitrarily. */
+ TEST_VMUL_LANE(, int, s, 16, 4, 4, 2);
+ TEST_VMUL_LANE(, int, s, 32, 2, 2, 1);
+ TEST_VMUL_LANE(, uint, u, 16, 4, 4, 2);
+ TEST_VMUL_LANE(, uint, u, 32, 2, 2, 1);
+ TEST_VMUL_LANE(, float, f, 32, 2, 2, 1);
+ TEST_VMUL_LANE(q, int, s, 16, 8, 4, 2);
+ TEST_VMUL_LANE(q, int, s, 32, 4, 2, 0);
+ TEST_VMUL_LANE(q, uint, u, 16, 8, 4, 2);
+ TEST_VMUL_LANE(q, uint, u, 32, 4, 2, 1);
+ TEST_VMUL_LANE(q, float, f, 32, 4, 2, 0);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ exec_vmul_lane ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 22/36] Add vmovn tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (14 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
` (20 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
new file mode 100644
index 0000000..bc2c2ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+
+#define TEST_MSG "VMOVN"
+void exec_vmovn (void)
+{
+ /* Basic test: vec64=vmovn(vec128), then store the result. */
+#define TEST_VMOVN(T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = \
+ vmovn_##T2##W(VECT_VAR(vector128, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector128);
+
+ TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer);
+
+ clean_results ();
+
+ TEST_VMOVN(int, s, 16, 8, 8);
+ TEST_VMOVN(int, s, 32, 16, 4);
+ TEST_VMOVN(int, s, 64, 32, 2);
+ TEST_VMOVN(uint, u, 16, 8, 8);
+ TEST_VMOVN(uint, u, 32, 16, 4);
+ TEST_VMOVN(uint, u, 64, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ exec_vmovn ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (6 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-19 16:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
` (28 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
new file mode 100644
index 0000000..e71a624
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
@@ -0,0 +1,86 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x200, 0x1c2, 0x188, 0x152 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x200, 0x1c2 };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffff,
+ 0x7fffffffffffffff };
+
+#define INSN_NAME vqdmull
+#define TEST_MSG "VQDMULL"
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=vqdmull(x,x), then store the result. */
+#define TEST_VQDMULL2(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), \
+ VECT_VAR(vector_res, T1, W2, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL2(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULL(T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL1(INSN_NAME, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector2, buffer, , int, s, 16, 4);
+ VLOAD(vector2, buffer, , int, s, 32, 2);
+
+ TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat, "");
+ TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat, "");
+
+ CHECK (TEST_MSG, int, 32, 4, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 64, 2, PRIx32, expected, "");
+
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector2, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector2, , int, s, 32, 2, 0x80000000);
+
+#define TEST_MSG2 "with saturation"
+ TEST_VQDMULL(int, s, 16, 32, 4, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULL(int, s, 32, 64, 2, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK (TEST_MSG, int, 32, 4, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 64, 2, PRIx32, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
` (35 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
new file mode 100644
index 0000000..d3aa879
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
@@ -0,0 +1,66 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x2000, 0x2000 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x2000, 0x2000 };
+
+#define TEST_MSG "VMULL_LANE"
+void exec_vmull_lane (void)
+{
+ /* vector_res = vmull_lane(vector,vector2,lane), then store the result. */
+#define TEST_VMULL_LANE(T1, T2, W, W2, N, L) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ vmull##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ L); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize vector. */
+ VDUP(vector, , int, s, 16, 4, 0x1000);
+ VDUP(vector, , int, s, 32, 2, 0x1000);
+ VDUP(vector, , uint, u, 16, 4, 0x1000);
+ VDUP(vector, , uint, u, 32, 2, 0x1000);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x4);
+ VDUP(vector2, , int, s, 32, 2, 0x2);
+ VDUP(vector2, , uint, u, 16, 4, 0x4);
+ VDUP(vector2, , uint, u, 32, 2, 0x2);
+
+ /* Choose lane arbitrarily. */
+ TEST_VMULL_LANE(int, s, 16, 32, 4, 2);
+ TEST_VMULL_LANE(int, s, 32, 64, 2, 1);
+ TEST_VMULL_LANE(uint, u, 16, 32, 4, 2);
+ TEST_VMULL_LANE(uint, u, 32, 64, 2, 1);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ exec_vmull_lane ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (20 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
` (14 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
new file mode 100644
index 0000000..cd61fd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
@@ -0,0 +1,63 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = OP(vector, vector3, vector4),
+ then store the result. */
+#define TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector3, T1, W2, N), \
+ VECT_VAR(vector4, T1, W2, N)); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMLXL(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector4, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector4, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+
+ VDUP(vector3, , int, s, 16, 4, 0x55);
+ VDUP(vector4, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0x55);
+ VDUP(vector4, , int, s, 32, 2, 0xBB);
+
+ TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat, "");
+ TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat, "");
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+
+ VDUP(vector3, , int, s, 16, 4, 0x8000);
+ VDUP(vector4, , int, s, 16, 4, 0x8000);
+ VDUP(vector3, , int, s, 32, 2, 0x80000000);
+ VDUP(vector4, , int, s, 32, 2, 0x80000000);
+
+#define TEST_MSG2 "with saturation"
+ TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c
new file mode 100644
index 0000000..c53a90a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c
@@ -0,0 +1,27 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlal
+#define TEST_MSG "VQDMLAL"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x7c1e, 0x7c1f, 0x7c20, 0x7c21 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x7c1e, 0x7c1f };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0,
+ 0x7ffffff1, 0x7ffffff2 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef,
+ 0x7ffffffffffffff0 };
+
+#include "vqdmlXl.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c
new file mode 100644
index 0000000..56e0b61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c
@@ -0,0 +1,29 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlsl
+#define TEST_MSG "VQDMLSL"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffff83c2, 0xffff83c3,
+ 0xffff83c4, 0xffff83c5 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffff83c2,
+ 0xffffffffffff83c3 };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+#include "vqdmlXl.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
` (33 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
new file mode 100644
index 0000000..ca45134
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
@@ -0,0 +1,70 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vmlxl_lane(vector, vector3, vector4, lane),
+ then store the result. */
+#define TEST_VMLXL_LANE1(INSN, T1, T2, W, W2, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector3, T1, W2, N), \
+ VECT_VAR(vector4, T1, W2, N), \
+ V); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLXL_LANE(INSN, T1, T2, W, W2, N, V) \
+ TEST_VMLXL_LANE1(INSN, T1, T2, W, W2, N, V)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector4, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector4, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector3, uint, 16, 4);
+ DECL_VARIABLE(vector4, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector3, uint, 32, 2);
+ DECL_VARIABLE(vector4, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector3, , int, s, 16, 4, 0x55);
+ VDUP(vector4, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0x55);
+ VDUP(vector4, , int, s, 32, 2, 0xBB);
+ VDUP(vector3, , uint, u, 16, 4, 0x55);
+ VDUP(vector4, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0x55);
+ VDUP(vector4, , uint, u, 32, 2, 0xBB);
+
+ TEST_VMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 2);
+ TEST_VMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 1);
+ TEST_VMLXL_LANE(INSN_NAME, uint, u, 32, 16, 4, 2);
+ TEST_VMLXL_LANE(INSN_NAME, uint, u, 64, 32, 2, 1);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c
new file mode 100644
index 0000000..0a384a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_lane
+#define TEST_MSG "VMLAL_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl_lane.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c
new file mode 100644
index 0000000..8b944a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c
@@ -0,0 +1,18 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_lane
+#define TEST_MSG "VMLSL_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+
+#include "vmlXl_lane.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (3 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-19 16:48 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
` (31 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c
new file mode 100644
index 0000000..ab66e2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c
@@ -0,0 +1,110 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+int VECT_VAR(expected_cumulative_sat,int,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x19, 0x19, 0x19, 0x19 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x4, 0x4 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xa, 0xa, 0xa, 0xa };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,16,8) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+
+#define INSN_NAME vqdmulh
+#define TEST_MSG "VQDMULH_N"
+#define FNNAME1(NAME) exec_ ## NAME ## _n
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ int i;
+
+ /* vector_res = vqdmulh_n(vector,val), then store the result. */
+#define TEST_VQDMULH_N2(INSN, Q, T1, T2, W, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULH_N1(INSN, Q, T1, T2, W, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH_N2(INSN, Q, T1, T2, W, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULH_N(Q, T1, T2, W, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH_N1(INSN_NAME, Q, T1, T2, W, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ clean_results ();
+
+ /* Initialize vector. */
+ VDUP(vector, , int, s, 16, 4, 0x1000);
+ VDUP(vector, , int, s, 32, 2, 0x100023);
+ VDUP(vector, q, int, s, 16, 8, 0x1000);
+ VDUP(vector, q, int, s, 32, 4, 0x100045);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VQDMULH_N(, int, s, 16, 4, 0xCF, expected_cumulative_sat, "");
+ TEST_VQDMULH_N(, int, s, 32, 2, 0x2344, expected_cumulative_sat, "");
+ TEST_VQDMULH_N(q, int, s, 16, 8, 0x80, expected_cumulative_sat, "");
+ TEST_VQDMULH_N(q, int, s, 32, 4, 0x5422, expected_cumulative_sat, "");
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected, "");
+
+ /* Choose input values to trigger saturation. */
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector, q, int, s, 16, 8, 0x8000);
+ VDUP(vector, q, int, s, 32, 4, 0x80000000);
+
+#define TEST_MSG2 " (check mul cumulative saturation)"
+ TEST_VQDMULH_N(, int, s, 16, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_N(, int, s, 32, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_N(q, int, s, 16, 8, 0x8000, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_N(q, int, s, 32, 4, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:30 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
` (34 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
new file mode 100644
index 0000000..34cdbe8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
@@ -0,0 +1,78 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_N(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, float, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 4)
+
+ /* vector_res = vmlx_n(vector, vector2, val),
+ then store the result. */
+#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V) \
+ TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)
+
+ DECL_VMLX_N(vector);
+ DECL_VMLX_N(vector2);
+ DECL_VMLX_N(vector_res);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+ VDUP(vector2, , float, f, 32, 2, 55.2f);
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+ VDUP(vector2, q, float, f, 32, 4, 55.9f);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11);
+ TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44);
+ TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88);
+ TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
new file mode 100644
index 0000000..8376fe1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c,
+ 0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776,
+ 0x2777, 0x2778, 0x2779, 0x277a };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b,
+ 0x4568287b, 0x4568387b };
+
+#include "vmlX_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
new file mode 100644
index 0000000..b7619f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba,
+ 0xe3bb, 0xe3bc, 0xe3bd, 0xe3be };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13,
+ 0xffffde14, 0xffffde15 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870,
+ 0xd871, 0xd872, 0xd873, 0xd874 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9,
+ 0xffffd2ca, 0xffffd2cb };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b,
+ 0xc569e87b, 0xc569d87b };
+
+#include "vmlX_n.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 25/36] Add vmull tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (27 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
` (7 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
new file mode 100644
index 0000000..3fdd51e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
@@ -0,0 +1,75 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x100, 0xe1, 0xc4, 0xa9,
+ 0x90, 0x79, 0x64, 0x51 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x100, 0xe1, 0xc4, 0xa9 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x100, 0xe1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xe100, 0xe2e1, 0xe4c4, 0xe6a9,
+ 0xe890, 0xea79, 0xec64, 0xee51 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffe00100, 0xffe200e1,
+ 0xffe400c4, 0xffe600a9 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffe000000100,
+ 0xffffffe2000000e1 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x5500, 0x5501, 0x5504, 0x5505,
+ 0x5510, 0x5511, 0x5514, 0x5515 };
+
+#define TEST_MSG "VMULL"
+void exec_vmull (void)
+{
+ /* Basic test: y=vmull(x,x), then store the result. */
+#define TEST_VMULL(T1, T2, W, W2, N) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ vmull_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, poly, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+ DECL_VARIABLE(vector_res, poly, 16, 8);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , poly, p, 8, 8);
+
+ TEST_VMULL(int, s, 8, 16, 8);
+ TEST_VMULL(int, s, 16, 32, 4);
+ TEST_VMULL(int, s, 32, 64, 2);
+ TEST_VMULL(uint, u, 8, 16, 8);
+ TEST_VMULL(uint, u, 16, 32, 4);
+ TEST_VMULL(uint, u, 32, 64, 2);
+ TEST_VMULL(poly, p, 8, 16, 8);
+
+ CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
+}
+
+int main (void)
+{
+ exec_vmull ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (2 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:24 ` Tejas Belagod
2015-01-19 15:23 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
` (32 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
new file mode 100644
index 0000000..be0ee65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
@@ -0,0 +1,96 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfef0, 0xff01, 0xff12, 0xff23 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfcd0, 0xfd03, 0xfd36, 0xfd69 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffbc0, 0xfffffc04 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b26666, 0xc3a74000 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf,
+ 0xfc04, 0xfc59, 0xfcae, 0xfd03 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffff9a0, 0xfffffa06,
+ 0xfffffa6c, 0xfffffad2 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf890, 0xf907, 0xf97e, 0xf9f5,
+ 0xfa6c, 0xfae3, 0xfb5a, 0xfbd1 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff780, 0xfffff808,
+ 0xfffff890, 0xfffff918 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4b1cccd, 0xc4a6b000,
+ 0xc49b9333, 0xc4907667 };
+
+#define INSN_NAME vmul_n
+#define TEST_MSG "VMUL_N"
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMUL(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, uint, 32, 4); \
+ DECL_VARIABLE(VAR, float, 32, 4)
+
+ /* vector_res = vmul_n(vector,val), then store the result. */
+#define TEST_VMUL_N(Q, T1, T2, W, N, L) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ vmul##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+ DECL_VMUL(vector);
+ DECL_VMUL(vector_res);
+
+ clean_results ();
+
+ /* Initialize vector from pre-initialized values. */
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMUL_N(, int, s, 16, 4, 0x11);
+ TEST_VMUL_N(, int, s, 32, 2, 0x22);
+ TEST_VMUL_N(, uint, u, 16, 4, 0x33);
+ TEST_VMUL_N(, uint, u, 32, 2, 0x44);
+ TEST_VMUL_N(, float, f, 32, 2, 22.3f);
+ TEST_VMUL_N(q, int, s, 16, 8, 0x55);
+ TEST_VMUL_N(q, int, s, 32, 4, 0x66);
+ TEST_VMUL_N(q, uint, u, 16, 8, 0x77);
+ TEST_VMUL_N(q, uint, u, 32, 4, 0x88);
+ TEST_VMUL_N(q, float, f, 32, 4, 88.9f);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests.
@ 2015-01-13 15:19 Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
` (36 more replies)
0 siblings, 37 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
This patch series is a follow-up of the conversion of my existing
testsuite into DejaGnu. It does not yet cover all the tests I wrote,
but I chose to post this set to have a chance to have it accepted
before stage 4. I will have 35 more files to convert after this set.
Most of the patches only add new tests/files, but a few modify
existing files as follows:
Patch 1: Fix dependency for Neon cumulative saturation (QC) flag.
Patch 2: Add traces in the CHECK* macro, to assert that a test was
actually executed.
Patch 8: Refactor vuzp and vzip tests.
Patch 9: Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code
with other new tests.
Patch 19: Put most of the code in common with vaddl in vXXXl.inc.
Patch 20: Put most of the code in common with vaddw through vXXWw.inc
Christophe Lyon (36):
Add explicit dependency on Neon Cumulative Saturation flag (QC).
Be more verbose, and actually confirm that a test was checked.
Add vmax, vmin, vhadd, vhsub and vrhadd tests.
Add vld1_lane tests.
Add vldX_dup test.
Add vmla and vmls tests.
Add vmla_lane and vmls_lane tests.
Add vtrn tests. Refactor vzup and vzip tests.
Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc
and vaddhn.c to share code with other new tests.
Add vmlal and vmlsl tests.
Add vmlal_lane and vmlsl_lane tests.
Add vmlal_n and vmlsl_n tests.
Add vmla_n and vmls_n tests.
Add vqdmlal and vqdmlsl tests.
Add vqdmlal_lane and vqdmlsl_lane tests.
Add vqdmlal_n and vqdmlsl_n tests.
Add vpadd, vpmax and vpmin tests.
Add vsli_n and vsri_n tests.
Add vsubl tests, put most of the code in common with vaddl in
vXXXl.inc.
Add vsubw tests, putting most of the code in common with vaddw through
vXXWw.inc
Add vmovl tests.
Add vmovn tests.
Add vmul_lane tests.
Add vmul_n tests.
Add vmull tests.
Add vmull_lane tests.
Add vmull_n tests.
Add vmnv tests.
Add vpadal tests.
Add vpaddl tests.
Add vqdmulh tests.
Add vqdmulh_lane tests.
Add vqdmulh_n tests.
Add vqdmull tests.
Add vqdmull_lane tests.
Add vqdmull_n tests.
.../aarch64/advsimd-intrinsics/arm-neon-ref.h | 35 +-
.../aarch64/advsimd-intrinsics/binary_op_no64.inc | 120 ++++
.../aarch64/advsimd-intrinsics/binary_sat_op.inc | 2 +-
.../aarch64/advsimd-intrinsics/unary_sat_op.inc | 2 +-
.../aarch64/advsimd-intrinsics/vXXXhn.inc | 50 ++
.../aarch64/advsimd-intrinsics/vXXXl.inc | 70 +++
.../aarch64/advsimd-intrinsics/vXXXw.inc | 70 +++
.../gcc.target/aarch64/advsimd-intrinsics/vaddhn.c | 57 +-
.../gcc.target/aarch64/advsimd-intrinsics/vaddl.c | 77 +--
.../gcc.target/aarch64/advsimd-intrinsics/vaddw.c | 77 +--
.../gcc.target/aarch64/advsimd-intrinsics/vhadd.c | 54 ++
.../gcc.target/aarch64/advsimd-intrinsics/vhsub.c | 52 ++
.../aarch64/advsimd-intrinsics/vld1_lane.c | 129 ++++
.../aarch64/advsimd-intrinsics/vldX_dup.c | 671 +++++++++++++++++++++
.../gcc.target/aarch64/advsimd-intrinsics/vmax.c | 64 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmin.c | 66 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmlX.inc | 110 ++++
.../aarch64/advsimd-intrinsics/vmlX_lane.inc | 91 +++
.../aarch64/advsimd-intrinsics/vmlX_n.inc | 78 +++
.../aarch64/advsimd-intrinsics/vmlXl.inc | 89 +++
.../aarch64/advsimd-intrinsics/vmlXl_lane.inc | 70 +++
.../aarch64/advsimd-intrinsics/vmlXl_n.inc | 61 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmla.c | 50 ++
.../aarch64/advsimd-intrinsics/vmla_lane.c | 50 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmla_n.c | 50 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmlal.c | 18 +
.../aarch64/advsimd-intrinsics/vmlal_lane.c | 14 +
.../aarch64/advsimd-intrinsics/vmlal_n.c | 14 +
.../gcc.target/aarch64/advsimd-intrinsics/vmls.c | 52 ++
.../aarch64/advsimd-intrinsics/vmls_lane.c | 52 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmls_n.c | 52 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmlsl.c | 22 +
.../aarch64/advsimd-intrinsics/vmlsl_lane.c | 18 +
.../aarch64/advsimd-intrinsics/vmlsl_n.c | 18 +
.../gcc.target/aarch64/advsimd-intrinsics/vmovl.c | 77 +++
.../gcc.target/aarch64/advsimd-intrinsics/vmovn.c | 50 ++
.../aarch64/advsimd-intrinsics/vmul_lane.c | 104 ++++
.../gcc.target/aarch64/advsimd-intrinsics/vmul_n.c | 96 +++
.../gcc.target/aarch64/advsimd-intrinsics/vmull.c | 75 +++
.../aarch64/advsimd-intrinsics/vmull_lane.c | 66 ++
.../aarch64/advsimd-intrinsics/vmull_n.c | 61 ++
.../gcc.target/aarch64/advsimd-intrinsics/vmvn.c | 136 +++++
.../aarch64/advsimd-intrinsics/vpXXX.inc | 67 ++
.../gcc.target/aarch64/advsimd-intrinsics/vpadal.c | 155 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vpadd.c | 19 +
.../gcc.target/aarch64/advsimd-intrinsics/vpaddl.c | 129 ++++
.../gcc.target/aarch64/advsimd-intrinsics/vpmax.c | 20 +
.../gcc.target/aarch64/advsimd-intrinsics/vpmin.c | 20 +
.../aarch64/advsimd-intrinsics/vqdmlXl.inc | 63 ++
.../aarch64/advsimd-intrinsics/vqdmlXl_lane.inc | 73 +++
.../aarch64/advsimd-intrinsics/vqdmlXl_n.inc | 59 ++
.../aarch64/advsimd-intrinsics/vqdmlal.c | 27 +
.../aarch64/advsimd-intrinsics/vqdmlal_lane.c | 38 ++
.../aarch64/advsimd-intrinsics/vqdmlal_n.c | 27 +
.../aarch64/advsimd-intrinsics/vqdmlsl.c | 29 +
.../aarch64/advsimd-intrinsics/vqdmlsl_lane.c | 40 ++
.../aarch64/advsimd-intrinsics/vqdmlsl_n.c | 29 +
.../aarch64/advsimd-intrinsics/vqdmulh.c | 122 ++++
.../aarch64/advsimd-intrinsics/vqdmulh_lane.c | 121 ++++
.../aarch64/advsimd-intrinsics/vqdmulh_n.c | 110 ++++
.../aarch64/advsimd-intrinsics/vqdmull.c | 86 +++
.../aarch64/advsimd-intrinsics/vqdmull_lane.c | 94 +++
.../aarch64/advsimd-intrinsics/vqdmull_n.c | 92 +++
.../aarch64/advsimd-intrinsics/vraddhn.c | 58 ++
.../gcc.target/aarch64/advsimd-intrinsics/vrhadd.c | 54 ++
.../aarch64/advsimd-intrinsics/vrsubhn.c | 58 ++
.../aarch64/advsimd-intrinsics/vsXi_n.inc | 82 +++
.../aarch64/advsimd-intrinsics/vshuffle.inc | 139 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vsli_n.c | 162 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vsri_n.c | 164 +++++
.../gcc.target/aarch64/advsimd-intrinsics/vsubhn.c | 58 ++
.../gcc.target/aarch64/advsimd-intrinsics/vsubl.c | 48 ++
.../gcc.target/aarch64/advsimd-intrinsics/vsubw.c | 50 ++
.../gcc.target/aarch64/advsimd-intrinsics/vtrn.c | 93 +++
.../gcc.target/aarch64/advsimd-intrinsics/vuzp.c | 142 +----
.../gcc.target/aarch64/advsimd-intrinsics/vzip.c | 142 +----
76 files changed, 5342 insertions(+), 498 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (7 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:18 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
` (27 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
new file mode 100644
index 0000000..427c9ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
@@ -0,0 +1,77 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#define TEST_MSG "VMOVL"
+void exec_vmovl (void)
+{
+ /* Basic test: vec128=vmovl(vec64), then store the result. */
+#define TEST_VMOVL(T1, T2, W, W2, N) \
+ VECT_VAR(vector128, T1, W2, N) = \
+ vmovl_##T2##W(VECT_VAR(vector64, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector128, T1, W2, N))
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector128);
+
+ TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64, buffer);
+
+ clean_results ();
+
+ TEST_VMOVL(int, s, 8, 16, 8);
+ TEST_VMOVL(int, s, 16, 32, 4);
+ TEST_VMOVL(int, s, 32, 64, 2);
+ TEST_VMOVL(uint, u, 8, 16, 8);
+ TEST_VMOVL(uint, u, 16, 32, 4);
+ TEST_VMOVL(uint, u, 32, 64, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vmovl ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (9 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
2015-01-19 13:42 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
` (25 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc
new file mode 100644
index 0000000..1c8f1be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc
@@ -0,0 +1,110 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX(T, W, N) \
+ DECL_VARIABLE(vector1, T, W, N); \
+ DECL_VARIABLE(vector2, T, W, N); \
+ DECL_VARIABLE(vector3, T, W, N); \
+ DECL_VARIABLE(vector_res, T, W, N)
+
+ /* vector_res = vmla(vector, vector3, vector4),
+ then store the result. */
+#define TEST_VMLX1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ VECT_VAR(vector3, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX(INSN, Q, T1, T2, W, N) \
+ TEST_VMLX1(INSN, Q, T1, T2, W, N)
+
+ DECL_VMLX(int, 8, 8);
+ DECL_VMLX(int, 16, 4);
+ DECL_VMLX(int, 32, 2);
+ DECL_VMLX(uint, 8, 8);
+ DECL_VMLX(uint, 16, 4);
+ DECL_VMLX(uint, 32, 2);
+ DECL_VMLX(float, 32, 2);
+ DECL_VMLX(int, 8, 16);
+ DECL_VMLX(int, 16, 8);
+ DECL_VMLX(int, 32, 4);
+ DECL_VMLX(uint, 8, 16);
+ DECL_VMLX(uint, 16, 8);
+ DECL_VMLX(uint, 32, 4);
+ DECL_VMLX(float, 32, 4);
+
+ clean_results ();
+
+ VLOAD(vector1, buffer, , int, s, 8, 8);
+ VLOAD(vector1, buffer, , int, s, 16, 4);
+ VLOAD(vector1, buffer, , int, s, 32, 2);
+ VLOAD(vector1, buffer, , uint, u, 8, 8);
+ VLOAD(vector1, buffer, , uint, u, 16, 4);
+ VLOAD(vector1, buffer, , uint, u, 32, 2);
+ VLOAD(vector1, buffer, , float, f, 32, 2);
+ VLOAD(vector1, buffer, q, int, s, 8, 16);
+ VLOAD(vector1, buffer, q, int, s, 16, 8);
+ VLOAD(vector1, buffer, q, int, s, 32, 4);
+ VLOAD(vector1, buffer, q, uint, u, 8, 16);
+ VLOAD(vector1, buffer, q, uint, u, 16, 8);
+ VLOAD(vector1, buffer, q, uint, u, 32, 4);
+ VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , uint, u, 8, 8, 0x44);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x66);
+ VDUP(vector2, , float, f, 32, 2, 33.1f);
+ VDUP(vector2, q, int, s, 8, 16, 0x77);
+ VDUP(vector2, q, int, s, 16, 8, 0x88);
+ VDUP(vector2, q, int, s, 32, 4, 0x99);
+ VDUP(vector2, q, uint, u, 8, 16, 0xAA);
+ VDUP(vector2, q, uint, u, 16, 8, 0xBB);
+ VDUP(vector2, q, uint, u, 32, 4, 0xCC);
+ VDUP(vector2, q, float, f, 32, 4, 99.2f);
+
+ VDUP(vector3, , int, s, 8, 8, 0xFF);
+ VDUP(vector3, , int, s, 16, 4, 0xEE);
+ VDUP(vector3, , int, s, 32, 2, 0xDD);
+ VDUP(vector3, , uint, u, 8, 8, 0xCC);
+ VDUP(vector3, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0xAA);
+ VDUP(vector3, , float, f, 32, 2, 10.23f);
+ VDUP(vector3, q, int, s, 8, 16, 0x99);
+ VDUP(vector3, q, int, s, 16, 8, 0x88);
+ VDUP(vector3, q, int, s, 32, 4, 0x77);
+ VDUP(vector3, q, uint, u, 8, 16, 0x66);
+ VDUP(vector3, q, uint, u, 16, 8, 0x55);
+ VDUP(vector3, q, uint, u, 32, 4, 0x44);
+ VDUP(vector3, q, float, f, 32, 4, 77.8f);
+
+ TEST_VMLX(INSN_NAME, , int, s, 8, 8);
+ TEST_VMLX(INSN_NAME, , int, s, 16, 4);
+ TEST_VMLX(INSN_NAME, , int, s, 32, 2);
+ TEST_VMLX(INSN_NAME, , uint, u, 8, 8);
+ TEST_VMLX(INSN_NAME, , uint, u, 16, 4);
+ TEST_VMLX(INSN_NAME, , uint, u, 32, 2);
+ TEST_VMLX(INSN_NAME, , float, f, 32, 2);
+ TEST_VMLX(INSN_NAME, q, int, s, 8, 16);
+ TEST_VMLX(INSN_NAME, q, int, s, 16, 8);
+ TEST_VMLX(INSN_NAME, q, int, s, 32, 4);
+ TEST_VMLX(INSN_NAME, q, uint, u, 8, 16);
+ TEST_VMLX(INSN_NAME, q, uint, u, 16, 8);
+ TEST_VMLX(INSN_NAME, q, uint, u, 32, 4);
+ TEST_VMLX(INSN_NAME, q, float, f, 32, 4);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c
new file mode 100644
index 0000000..e3da60c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xdf, 0xe0, 0xe1, 0xe2,
+ 0xe3, 0xe4, 0xe5, 0xe6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x1f8c, 0x1f8d, 0x1f8e, 0x1f8f };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x2bf7, 0x2bf8 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x20, 0x21, 0x22, 0x23,
+ 0x24, 0x25, 0x26, 0x27 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x43ac, 0x43ad };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x43a14e76, 0x43a1ce76 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf, 0x10, 0x11, 0x12,
+ 0x13, 0x14, 0x15, 0x16,
+ 0x17, 0x18, 0x19, 0x1a,
+ 0x1b, 0x1c, 0x1d, 0x1e };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x4830, 0x4831, 0x4832, 0x4833,
+ 0x4834, 0x4835, 0x4836, 0x4837 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x470f, 0x4710, 0x4711, 0x4712 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xac, 0xad, 0xae, 0xaf,
+ 0xb0, 0xb1, 0xb2, 0xb3,
+ 0xb4, 0xb5, 0xb6, 0xb7,
+ 0xb8, 0xb9, 0xba, 0xbb };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3620, 0x3621, 0x3622, 0x3623 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x45f0ae15, 0x45f0b615,
+ 0x45f0be15, 0x45f0c615 };
+
+#include "vmlX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c
new file mode 100644
index 0000000..b3443ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x1, 0x2, 0x3, 0x4,
+ 0x5, 0x6, 0x7, 0x8 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xe054, 0xe055, 0xe056, 0xe057 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffd3e9, 0xffffd3ea };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc0, 0xc1, 0xc2, 0xc3,
+ 0xc4, 0xc5, 0xc6, 0xc7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffbc34, 0xffffbc35 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b14e76, 0xc3b0ce76 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xd1, 0xd2, 0xd3, 0xd4,
+ 0xd5, 0xd6, 0xd7, 0xd8,
+ 0xd9, 0xda, 0xdb, 0xdc,
+ 0xdd, 0xde, 0xdf, 0xe0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xb7b0, 0xb7b1, 0xb7b2, 0xb7b3,
+ 0xb7b4, 0xb7b5, 0xb7b6, 0xb7b7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffb8d1, 0xffffb8d2,
+ 0xffffb8d3, 0xffffb8d4 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x34, 0x35, 0x36, 0x37,
+ 0x38, 0x39, 0x3a, 0x3b,
+ 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x40, 0x41, 0x42, 0x43 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc9c0, 0xffffc9c1,
+ 0xffffc9c2, 0xffffc9c3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc5f1ae15, 0xc5f1a615,
+ 0xc5f19e15, 0xc5f19615 };
+
+#include "vmlX.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (12 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
` (22 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc
new file mode 100644
index 0000000..b644a0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc
@@ -0,0 +1,91 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_LANE(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, uint, 32, 4); \
+ DECL_VARIABLE(VAR, float, 32, 4)
+
+ /* vector_res = vmlx_lane(vector, vector2, vector3, lane),
+ then store the result. */
+#define TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, L) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ VECT_VAR(vector3, T1, W, N2), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_LANE(INSN, Q, T1, T2, W, N, N2, V) \
+ TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, V)
+
+ DECL_VMLX_LANE(vector);
+ DECL_VMLX_LANE(vector2);
+ DECL_VMLX_LANE(vector_res);
+
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector3, uint, 16, 4);
+ DECL_VARIABLE(vector3, uint, 32, 2);
+ DECL_VARIABLE(vector3, float, 32, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+ VDUP(vector2, , float, f, 32, 2, 55.3f);
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+ VDUP(vector2, q, float, f, 32, 4, 55.8f);
+
+ VDUP(vector3, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0xBB);
+ VDUP(vector3, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0xBB);
+ VDUP(vector3, , float, f, 32, 2, 11.34f);
+
+ /* Choose lane arbitrarily. */
+ TEST_VMLX_LANE(INSN_NAME, , int, s, 16, 4, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, , int, s, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, , uint, u, 16, 4, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, , uint, u, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, , float, f, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, int, s, 16, 8, 4, 3);
+ TEST_VMLX_LANE(INSN_NAME, q, int, s, 32, 4, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, uint, u, 16, 8, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, q, uint, u, 32, 4, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, float, f, 32, 4, 2, 1);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c
new file mode 100644
index 0000000..f4b89d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4418c687, 0x44190687 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x441a3168, 0x441a7168,
+ 0x441ab168, 0x441af168 };
+
+#include "vmlX_lane.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c
new file mode 100644
index 0000000..80054e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffc1d9, 0xffffc1da };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffc1d9, 0xffffc1da };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc420c687, 0xc4208687 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4223168, 0xc421f168,
+ 0xc421b168, 0xc4217168 };
+
+#include "vmlX_lane.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (13 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
` (21 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
new file mode 100644
index 0000000..a968584
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
@@ -0,0 +1,61 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vmlxl_n(vector, vector2, val),
+ then store the result. */
+#define TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W2, N), \
+ V); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLXL_N(INSN, T1, T2, W, W2, N, V) \
+ TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x11);
+ TEST_VMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x22);
+ TEST_VMLXL_N(INSN_NAME, uint, u, 32, 16, 4, 0x33);
+ TEST_VMLXL_N(INSN_NAME, uint, u, 64, 32, 2, 0x33);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c
new file mode 100644
index 0000000..118068c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c
@@ -0,0 +1,14 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal_n
+#define TEST_MSG "VMLAL_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x10df, 0x10e0 };
+
+#include "vmlXl_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c
new file mode 100644
index 0000000..a26c69f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c
@@ -0,0 +1,18 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl_n
+#define TEST_MSG "VMLSL_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffa4b, 0xfffffa4c,
+ 0xfffffa4d, 0xfffffa4e };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffff4a6,
+ 0xfffffffffffff4a7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffef01, 0xffffef02,
+ 0xffffef03, 0xffffef04 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffef01,
+ 0xffffffffffffef02 };
+
+#include "vmlXl_n.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (16 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:21 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
` (18 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
vXXXhn.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 0000000..0dbcc92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,50 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
+#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
+ TEST_VADDHN1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector1);
+ DECL_VARIABLE_128BITS_VARIANTS(vector2);
+
+ clean_results ();
+
+ /* Fill input vector1 and vector2 with arbitrary values */
+ VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
+ VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
+ VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
+ VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
+ VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
+ VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
+
+ VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
+ VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
+
+ TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
+ TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
+ TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2);
+ TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8);
+ TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4);
+ TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
index 58fd5ea..88c92f3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
@@ -8,6 +8,9 @@
#include <stdint.h>
#endif
+#define INSN_NAME vaddhn
+#define TEST_MSG "VADDHN"
+
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32 };
@@ -52,56 +55,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
0x33333333, 0x33333333 };
-#define INSN_NAME vaddhn
-#define TEST_MSG "VADDHN"
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
-#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
- VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
-
-#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
- TEST_VADDHN1(INSN, T1, T2, W, W2, N)
-
- DECL_VARIABLE_64BITS_VARIANTS(vector64);
- DECL_VARIABLE_128BITS_VARIANTS(vector1);
- DECL_VARIABLE_128BITS_VARIANTS(vector2);
-
- clean_results ();
-
- /* Fill input vector1 and vector2 with arbitrary values */
- VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
- VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
- VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
- VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
- VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
- VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
-
- VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
- VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
-
- TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
- TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
- TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2);
- TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8);
- TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4);
- TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2);
-
- CHECK_RESULTS (TEST_MSG, "");
-}
-
-int main (void)
-{
- FNNAME (INSN_NAME) ();
- return 0;
-}
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
new file mode 100644
index 0000000..6cd737c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
@@ -0,0 +1,58 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vraddhn
+#define TEST_MSG "VRADDHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4,
+ 0x4, 0x4, 0x4, 0x4 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x38, 0x38, 0x38, 0x38 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x4, 0x4 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
new file mode 100644
index 0000000..9f0630d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
@@ -0,0 +1,58 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vrsubhn
+#define TEST_MSG "VRSUBHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+ 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
new file mode 100644
index 0000000..b0b7893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
@@ -0,0 +1,58 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vsubhn
+#define TEST_MSG "VSUBHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+ 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vXXXhn.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (25 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:06 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
` (9 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
vshuffle.inc.
* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
vshuffle.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
new file mode 100644
index 0000000..928f338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
@@ -0,0 +1,139 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* In this case, output variables are arrays of vectors. */
+#define DECL_VSHUFFLE(T1, W, N) \
+ VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
+ VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
+
+ /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result. */
+#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N) \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
+ VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
+ memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ /* Overwrite "result" with the contents of "result_bis"[X]. */
+#define TEST_EXTRA_CHUNK(T1, W, N, X) \
+ memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+ DECL_VARIABLE_ALL_VARIANTS(vector1);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+
+ /* We don't need 64 bits variants. */
+#define DECL_ALL_VSHUFFLE() \
+ DECL_VSHUFFLE(int, 8, 8); \
+ DECL_VSHUFFLE(int, 16, 4); \
+ DECL_VSHUFFLE(int, 32, 2); \
+ DECL_VSHUFFLE(uint, 8, 8); \
+ DECL_VSHUFFLE(uint, 16, 4); \
+ DECL_VSHUFFLE(uint, 32, 2); \
+ DECL_VSHUFFLE(poly, 8, 8); \
+ DECL_VSHUFFLE(poly, 16, 4); \
+ DECL_VSHUFFLE(float, 32, 2); \
+ DECL_VSHUFFLE(int, 8, 16); \
+ DECL_VSHUFFLE(int, 16, 8); \
+ DECL_VSHUFFLE(int, 32, 4); \
+ DECL_VSHUFFLE(uint, 8, 16); \
+ DECL_VSHUFFLE(uint, 16, 8); \
+ DECL_VSHUFFLE(uint, 32, 4); \
+ DECL_VSHUFFLE(poly, 8, 16); \
+ DECL_VSHUFFLE(poly, 16, 8); \
+ DECL_VSHUFFLE(float, 32, 4)
+
+ DECL_ALL_VSHUFFLE();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
+ VLOAD(vector1, buffer, , float, f, 32, 2);
+ VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+ /* Choose arbitrary initialization values. */
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , uint, u, 8, 8, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x66);
+ VDUP(vector2, , uint, u, 32, 2, 0x77);
+ VDUP(vector2, , poly, p, 8, 8, 0x55);
+ VDUP(vector2, , poly, p, 16, 4, 0x66);
+ VDUP(vector2, , float, f, 32, 2, 33.6f);
+
+ VDUP(vector2, q, int, s, 8, 16, 0x11);
+ VDUP(vector2, q, int, s, 16, 8, 0x22);
+ VDUP(vector2, q, int, s, 32, 4, 0x33);
+ VDUP(vector2, q, uint, u, 8, 16, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x66);
+ VDUP(vector2, q, uint, u, 32, 4, 0x77);
+ VDUP(vector2, q, poly, p, 8, 16, 0x55);
+ VDUP(vector2, q, poly, p, 16, 8, 0x66);
+ VDUP(vector2, q, float, f, 32, 4, 33.8f);
+
+#define TEST_ALL_VSHUFFLE(INSN) \
+ TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
+ TEST_VSHUFFLE(INSN, , int, s, 16, 4); \
+ TEST_VSHUFFLE(INSN, , int, s, 32, 2); \
+ TEST_VSHUFFLE(INSN, , uint, u, 8, 8); \
+ TEST_VSHUFFLE(INSN, , uint, u, 16, 4); \
+ TEST_VSHUFFLE(INSN, , uint, u, 32, 2); \
+ TEST_VSHUFFLE(INSN, , poly, p, 8, 8); \
+ TEST_VSHUFFLE(INSN, , poly, p, 16, 4); \
+ TEST_VSHUFFLE(INSN, , float, f, 32, 2); \
+ TEST_VSHUFFLE(INSN, q, int, s, 8, 16); \
+ TEST_VSHUFFLE(INSN, q, int, s, 16, 8); \
+ TEST_VSHUFFLE(INSN, q, int, s, 32, 4); \
+ TEST_VSHUFFLE(INSN, q, uint, u, 8, 16); \
+ TEST_VSHUFFLE(INSN, q, uint, u, 16, 8); \
+ TEST_VSHUFFLE(INSN, q, uint, u, 32, 4); \
+ TEST_VSHUFFLE(INSN, q, poly, p, 8, 16); \
+ TEST_VSHUFFLE(INSN, q, poly, p, 16, 8); \
+ TEST_VSHUFFLE(INSN, q, float, f, 32, 4)
+
+#define TEST_ALL_EXTRA_CHUNKS() \
+ TEST_EXTRA_CHUNK(int, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 2, 1); \
+ TEST_EXTRA_CHUNK(int, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(int, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(int, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
+ TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
+ TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
+ TEST_EXTRA_CHUNK(float, 32, 4, 1)
+
+ clean_results ();
+
+ /* Execute the tests. */
+ TEST_ALL_VSHUFFLE(INSN_NAME);
+
+ CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
+
+ TEST_ALL_EXTRA_CHUNKS();
+ CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
new file mode 100644
index 0000000..be18c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
@@ -0,0 +1,93 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results splitted in several chunks. */
+/* Chunk 0. */
+VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11,
+ 0xf2, 0xf3, 0x11, 0x11 };
+VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 };
+VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 0xf2, 0xf3, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 0xf2, 0xf3, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
+ 0xf2, 0xf3, 0x11, 0x11,
+ 0xf4, 0xf5, 0x11, 0x11,
+ 0xf6, 0xf7, 0x11, 0x11 };
+VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22,
+ 0xfff2, 0xfff3, 0x22, 0x22 };
+VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x33, 0x33 };
+VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 0xf2, 0xf3, 0x55, 0x55,
+ 0xf4, 0xf5, 0x55, 0x55,
+ 0xf6, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
+ 0xfff2, 0xfff3, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x77, 0x77 };
+VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
+ 0xf2, 0xf3, 0x55, 0x55,
+ 0xf4, 0xf5, 0x55, 0x55,
+ 0xf6, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
+ 0xfff2, 0xfff3, 0x66, 0x66 };
+VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0x42073333, 0x42073333 };
+
+/* Chunk 1. */
+VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf4, 0xf5, 0x11, 0x11,
+ 0xf6, 0xf7, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff2, 0xfff3, 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
+ 0xf6, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
+ 0xf6, 0xf7, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
+VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
+ 0xfa, 0xfb, 0x11, 0x11,
+ 0xfc, 0xfd, 0x11, 0x11,
+ 0xfe, 0xff, 0x11, 0x11 };
+VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff4, 0xfff5, 0x22, 0x22,
+ 0xfff6, 0xfff7, 0x22, 0x22 };
+VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x33, 0x33 };
+VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
+ 0xfa, 0xfb, 0x55, 0x55,
+ 0xfc, 0xfd, 0x55, 0x55,
+ 0xfe, 0xff, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
+ 0xfff6, 0xfff7, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x77, 0x77 };
+VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
+ 0xfa, 0xfb, 0x55, 0x55,
+ 0xfc, 0xfd, 0x55, 0x55,
+ 0xfe, 0xff, 0x55, 0x55 };
+VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
+ 0xfff6, 0xfff7, 0x66, 0x66 };
+VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
+ 0x42073333, 0x42073333 };
+
+#define INSN_NAME vtrn
+#define TEST_MSG "VTRN/VTRNQ"
+
+#include "vshuffle.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
index 53f875e..ec9ded3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
@@ -99,147 +99,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
0x42073333, 0x42073333 };
-#ifndef INSN_NAME
#define INSN_NAME vuzp
#define TEST_MSG "VUZP/VUZPQ"
-#endif
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* In this case, output variables are arrays of vectors. */
-#define DECL_VUZP(T1, W, N) \
- VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
- VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
-
- /* We need to use a temporary result buffer (result_bis), because
- the one used for other tests is not large enough. A subset of the
- result data is moved from result_bis to result, and it is this
- subset which is used to check the actual behaviour. The next
- macro enables to move another chunk of data from result_bis to
- result. */
-#define TEST_VUZP(INSN, Q, T1, T2, W, N) \
- VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
- INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
- VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
- memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
- sizeof(VECT_VAR(result, T1, W, N)));
-
- /* Overwrite "result" with the contents of "result_bis"[X]. */
-#define TEST_EXTRA_CHUNK(T1, W, N, X) \
- memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
- sizeof(VECT_VAR(result, T1, W, N)));
-
- DECL_VARIABLE_ALL_VARIANTS(vector1);
- DECL_VARIABLE_ALL_VARIANTS(vector2);
-
- /* We don't need 64 bits variants. */
-#define DECL_ALL_VUZP() \
- DECL_VUZP(int, 8, 8); \
- DECL_VUZP(int, 16, 4); \
- DECL_VUZP(int, 32, 2); \
- DECL_VUZP(uint, 8, 8); \
- DECL_VUZP(uint, 16, 4); \
- DECL_VUZP(uint, 32, 2); \
- DECL_VUZP(poly, 8, 8); \
- DECL_VUZP(poly, 16, 4); \
- DECL_VUZP(float, 32, 2); \
- DECL_VUZP(int, 8, 16); \
- DECL_VUZP(int, 16, 8); \
- DECL_VUZP(int, 32, 4); \
- DECL_VUZP(uint, 8, 16); \
- DECL_VUZP(uint, 16, 8); \
- DECL_VUZP(uint, 32, 4); \
- DECL_VUZP(poly, 8, 16); \
- DECL_VUZP(poly, 16, 8); \
- DECL_VUZP(float, 32, 4)
-
- DECL_ALL_VUZP();
-
- /* Initialize input "vector" from "buffer". */
- TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
- VLOAD(vector1, buffer, , float, f, 32, 2);
- VLOAD(vector1, buffer, q, float, f, 32, 4);
-
- /* Choose arbitrary initialization values. */
- VDUP(vector2, , int, s, 8, 8, 0x11);
- VDUP(vector2, , int, s, 16, 4, 0x22);
- VDUP(vector2, , int, s, 32, 2, 0x33);
- VDUP(vector2, , uint, u, 8, 8, 0x55);
- VDUP(vector2, , uint, u, 16, 4, 0x66);
- VDUP(vector2, , uint, u, 32, 2, 0x77);
- VDUP(vector2, , poly, p, 8, 8, 0x55);
- VDUP(vector2, , poly, p, 16, 4, 0x66);
- VDUP(vector2, , float, f, 32, 2, 33.6f);
-
- VDUP(vector2, q, int, s, 8, 16, 0x11);
- VDUP(vector2, q, int, s, 16, 8, 0x22);
- VDUP(vector2, q, int, s, 32, 4, 0x33);
- VDUP(vector2, q, uint, u, 8, 16, 0x55);
- VDUP(vector2, q, uint, u, 16, 8, 0x66);
- VDUP(vector2, q, uint, u, 32, 4, 0x77);
- VDUP(vector2, q, poly, p, 8, 16, 0x55);
- VDUP(vector2, q, poly, p, 16, 8, 0x66);
- VDUP(vector2, q, float, f, 32, 4, 33.8f);
-
-#define TEST_ALL_VUZP(INSN) \
- TEST_VUZP(INSN, , int, s, 8, 8); \
- TEST_VUZP(INSN, , int, s, 16, 4); \
- TEST_VUZP(INSN, , int, s, 32, 2); \
- TEST_VUZP(INSN, , uint, u, 8, 8); \
- TEST_VUZP(INSN, , uint, u, 16, 4); \
- TEST_VUZP(INSN, , uint, u, 32, 2); \
- TEST_VUZP(INSN, , poly, p, 8, 8); \
- TEST_VUZP(INSN, , poly, p, 16, 4); \
- TEST_VUZP(INSN, , float, f, 32, 2); \
- TEST_VUZP(INSN, q, int, s, 8, 16); \
- TEST_VUZP(INSN, q, int, s, 16, 8); \
- TEST_VUZP(INSN, q, int, s, 32, 4); \
- TEST_VUZP(INSN, q, uint, u, 8, 16); \
- TEST_VUZP(INSN, q, uint, u, 16, 8); \
- TEST_VUZP(INSN, q, uint, u, 32, 4); \
- TEST_VUZP(INSN, q, poly, p, 8, 16); \
- TEST_VUZP(INSN, q, poly, p, 16, 8); \
- TEST_VUZP(INSN, q, float, f, 32, 4)
-
-#define TEST_ALL_EXTRA_CHUNKS() \
- TEST_EXTRA_CHUNK(int, 8, 8, 1); \
- TEST_EXTRA_CHUNK(int, 16, 4, 1); \
- TEST_EXTRA_CHUNK(int, 32, 2, 1); \
- TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
- TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
- TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
- TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
- TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
- TEST_EXTRA_CHUNK(float, 32, 2, 1); \
- TEST_EXTRA_CHUNK(int, 8, 16, 1); \
- TEST_EXTRA_CHUNK(int, 16, 8, 1); \
- TEST_EXTRA_CHUNK(int, 32, 4, 1); \
- TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
- TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
- TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
- TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
- TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
- TEST_EXTRA_CHUNK(float, 32, 4, 1)
-
- clean_results ();
-
- /* Execute the tests. */
- TEST_ALL_VUZP(INSN_NAME);
-
- CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
-
- TEST_ALL_EXTRA_CHUNKS();
- CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
-}
-
-int main (void)
-{
- FNNAME (INSN_NAME) ();
-
- return 0;
-}
+#include "vshuffle.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
index a1f1eee..05faa8a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
@@ -97,147 +97,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
0x42073333, 0x42073333 };
-#ifndef INSN_NAME
#define INSN_NAME vzip
#define TEST_MSG "VZIP/VZIPQ"
-#endif
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* In this case, output variables are arrays of vectors. */
-#define DECL_VZIP(T1, W, N) \
- VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
- VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
-
- /* We need to use a temporary result buffer (result_bis), because
- the one used for other tests is not large enough. A subset of the
- result data is moved from result_bis to result, and it is this
- subset which is used to check the actual behaviour. The next
- macro enables to move another chunk of data from result_bis to
- result. */
-#define TEST_VZIP(INSN, Q, T1, T2, W, N) \
- VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
- INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
- VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
- memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
- sizeof(VECT_VAR(result, T1, W, N)));
-
- /* Overwrite "result" with the contents of "result_bis"[X]. */
-#define TEST_EXTRA_CHUNK(T1, W, N, X) \
- memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
- sizeof(VECT_VAR(result, T1, W, N)));
-
- DECL_VARIABLE_ALL_VARIANTS(vector1);
- DECL_VARIABLE_ALL_VARIANTS(vector2);
-
- /* We don't need 64 bits variants. */
-#define DECL_ALL_VZIP() \
- DECL_VZIP(int, 8, 8); \
- DECL_VZIP(int, 16, 4); \
- DECL_VZIP(int, 32, 2); \
- DECL_VZIP(uint, 8, 8); \
- DECL_VZIP(uint, 16, 4); \
- DECL_VZIP(uint, 32, 2); \
- DECL_VZIP(poly, 8, 8); \
- DECL_VZIP(poly, 16, 4); \
- DECL_VZIP(float, 32, 2); \
- DECL_VZIP(int, 8, 16); \
- DECL_VZIP(int, 16, 8); \
- DECL_VZIP(int, 32, 4); \
- DECL_VZIP(uint, 8, 16); \
- DECL_VZIP(uint, 16, 8); \
- DECL_VZIP(uint, 32, 4); \
- DECL_VZIP(poly, 8, 16); \
- DECL_VZIP(poly, 16, 8); \
- DECL_VZIP(float, 32, 4)
-
- DECL_ALL_VZIP();
-
- /* Initialize input "vector" from "buffer". */
- TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
- VLOAD(vector1, buffer, , float, f, 32, 2);
- VLOAD(vector1, buffer, q, float, f, 32, 4);
-
- /* Choose arbitrary initialization values. */
- VDUP(vector2, , int, s, 8, 8, 0x11);
- VDUP(vector2, , int, s, 16, 4, 0x22);
- VDUP(vector2, , int, s, 32, 2, 0x33);
- VDUP(vector2, , uint, u, 8, 8, 0x55);
- VDUP(vector2, , uint, u, 16, 4, 0x66);
- VDUP(vector2, , uint, u, 32, 2, 0x77);
- VDUP(vector2, , poly, p, 8, 8, 0x55);
- VDUP(vector2, , poly, p, 16, 4, 0x66);
- VDUP(vector2, , float, f, 32, 2, 33.6f);
-
- VDUP(vector2, q, int, s, 8, 16, 0x11);
- VDUP(vector2, q, int, s, 16, 8, 0x22);
- VDUP(vector2, q, int, s, 32, 4, 0x33);
- VDUP(vector2, q, uint, u, 8, 16, 0x55);
- VDUP(vector2, q, uint, u, 16, 8, 0x66);
- VDUP(vector2, q, uint, u, 32, 4, 0x77);
- VDUP(vector2, q, poly, p, 8, 16, 0x55);
- VDUP(vector2, q, poly, p, 16, 8, 0x66);
- VDUP(vector2, q, float, f, 32, 4, 33.8f);
-
-#define TEST_ALL_VZIP(INSN) \
- TEST_VZIP(INSN, , int, s, 8, 8); \
- TEST_VZIP(INSN, , int, s, 16, 4); \
- TEST_VZIP(INSN, , int, s, 32, 2); \
- TEST_VZIP(INSN, , uint, u, 8, 8); \
- TEST_VZIP(INSN, , uint, u, 16, 4); \
- TEST_VZIP(INSN, , uint, u, 32, 2); \
- TEST_VZIP(INSN, , poly, p, 8, 8); \
- TEST_VZIP(INSN, , poly, p, 16, 4); \
- TEST_VZIP(INSN, , float, f, 32, 2); \
- TEST_VZIP(INSN, q, int, s, 8, 16); \
- TEST_VZIP(INSN, q, int, s, 16, 8); \
- TEST_VZIP(INSN, q, int, s, 32, 4); \
- TEST_VZIP(INSN, q, uint, u, 8, 16); \
- TEST_VZIP(INSN, q, uint, u, 16, 8); \
- TEST_VZIP(INSN, q, uint, u, 32, 4); \
- TEST_VZIP(INSN, q, poly, p, 8, 16); \
- TEST_VZIP(INSN, q, poly, p, 16, 8); \
- TEST_VZIP(INSN, q, float, f, 32, 4)
-
-#define TEST_ALL_EXTRA_CHUNKS() \
- TEST_EXTRA_CHUNK(int, 8, 8, 1); \
- TEST_EXTRA_CHUNK(int, 16, 4, 1); \
- TEST_EXTRA_CHUNK(int, 32, 2, 1); \
- TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
- TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
- TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
- TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
- TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
- TEST_EXTRA_CHUNK(float, 32, 2, 1); \
- TEST_EXTRA_CHUNK(int, 8, 16, 1); \
- TEST_EXTRA_CHUNK(int, 16, 8, 1); \
- TEST_EXTRA_CHUNK(int, 32, 4, 1); \
- TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
- TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
- TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
- TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
- TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
- TEST_EXTRA_CHUNK(float, 32, 4, 1)
-
- clean_results ();
-
- /* Execute the tests. */
- TEST_ALL_VZIP(INSN_NAME);
-
- CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
-
- TEST_ALL_EXTRA_CHUNKS();
- CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
-}
-
-int main (void)
-{
- FNNAME (INSN_NAME) ();
-
- return 0;
-}
+#include "vshuffle.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 29/36] Add vpadal tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (21 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:41 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
` (13 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vpadal.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
new file mode 100644
index 0000000..dcedb45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
@@ -0,0 +1,155 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffd1, 0xffd6, 0xffdb, 0xffe0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffd1, 0xffffffd6 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffd1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1d1, 0x1d6, 0x1db, 0x1e0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1ffd1, 0x1ffd6 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffd1 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffd1, 0xffd6, 0xffdb, 0xffe0,
+ 0xffe5, 0xffea, 0xffef, 0xfff4 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffd1, 0xffffffd6,
+ 0xffffffdb, 0xffffffe0 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffd1, 0xffffffffffffffd6 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1d1, 0x1d6, 0x1db, 0x1e0,
+ 0x1e5, 0x1ea, 0x1ef, 0x1f4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1ffd1, 0x1ffd6, 0x1ffdb, 0x1ffe0 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x1ffffffd1, 0x1ffffffd6 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#define INSN_NAME vpadal
+#define TEST_MSG "VPADAL/VPADALQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADAL1(INSN, Q, T1, T2, W, N, W2, N2) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W2, N2), VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VPADAL(INSN, Q, T1, T2, W, N, W2, N2) \
+ TEST_VPADAL1(INSN, Q, T1, T2, W, N, W2, N2)
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, int, 64, 1);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, uint, 64, 1);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector2, int, 8, 8);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 8, 8);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+ DECL_VARIABLE(vector2, int, 8, 16);
+ DECL_VARIABLE(vector2, int, 16, 8);
+ DECL_VARIABLE(vector2, int, 32, 4);
+ DECL_VARIABLE(vector2, uint, 8, 16);
+ DECL_VARIABLE(vector2, uint, 16, 8);
+ DECL_VARIABLE(vector2, uint, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 1);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 1);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , int, s, 64, 1);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 64, 1);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Initialize input "vector2" from "buffer". */
+ VLOAD(vector2, buffer, , int, s, 8, 8);
+ VLOAD(vector2, buffer, , int, s, 16, 4);
+ VLOAD(vector2, buffer, , int, s, 32, 2);
+ VLOAD(vector2, buffer, , uint, u, 8, 8);
+ VLOAD(vector2, buffer, , uint, u, 16, 4);
+ VLOAD(vector2, buffer, , uint, u, 32, 2);
+ VLOAD(vector2, buffer, q, int, s, 8, 16);
+ VLOAD(vector2, buffer, q, int, s, 16, 8);
+ VLOAD(vector2, buffer, q, int, s, 32, 4);
+ VLOAD(vector2, buffer, q, uint, u, 8, 16);
+ VLOAD(vector2, buffer, q, uint, u, 16, 8);
+ VLOAD(vector2, buffer, q, uint, u, 32, 4);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADAL(INSN_NAME, , int, s, 8, 8, 16, 4);
+ TEST_VPADAL(INSN_NAME, , int, s, 16, 4, 32, 2);
+ TEST_VPADAL(INSN_NAME, , int, s, 32, 2, 64 ,1);
+ TEST_VPADAL(INSN_NAME, , uint, u, 8, 8, 16, 4);
+ TEST_VPADAL(INSN_NAME, , uint, u, 16, 4, 32, 2);
+ TEST_VPADAL(INSN_NAME, , uint, u, 32, 2, 64, 1);
+ TEST_VPADAL(INSN_NAME, q, int, s, 8, 16, 16, 8);
+ TEST_VPADAL(INSN_NAME, q, int, s, 16, 8, 32, 4);
+ TEST_VPADAL(INSN_NAME, q, int, s, 32, 4, 64 ,2);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vpadal ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 28/36] Add vmnv tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (11 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:39 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
` (23 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmvn.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
new file mode 100644
index 0000000..04bb5f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
@@ -0,0 +1,136 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xf, 0xe };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xf, 0xe };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#define INSN_NAME vmvn
+#define TEST_MSG "VMVN/VMVNQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_UNARY_OP(INSN, Q, T1, T2, W, N) \
+ TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, poly, 8, 8);
+ DECL_VARIABLE(vector, int, 8, 16);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, uint, 8, 16);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, poly, 8, 16);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, poly, 8, 8);
+ DECL_VARIABLE(vector_res, int, 8, 16);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 8, 16);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, poly, 8, 16);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , poly, p, 8, 8);
+ VLOAD(vector, buffer, q, int, s, 8, 16);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 8, 16);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, poly, p, 8, 16);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_UNARY_OP(INSN_NAME, , int, s, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, , int, s, 16, 4);
+ TEST_UNARY_OP(INSN_NAME, , int, s, 32, 2);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 16, 4);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 32, 2);
+ TEST_UNARY_OP(INSN_NAME, , poly, p, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 8, 16);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 8, 16);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 16, 8);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 32, 4);
+ TEST_UNARY_OP(INSN_NAME, q, poly, p, 8, 16);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vmvn ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (10 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-19 16:46 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
` (24 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c
new file mode 100644
index 0000000..8d2a365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c
@@ -0,0 +1,122 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+int VECT_VAR(expected_cumulative_sat,int,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,16,8) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+
+#define INSN_NAME vqdmulh
+#define TEST_MSG "VQDMULH"
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vqdmulh(vector,vector2,lane), then store the result. */
+#define TEST_VQDMULH2(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULH1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH2(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULH(Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH1(INSN_NAME, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 8);
+ DECL_VARIABLE(vector2, int, 32, 4);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0xBB);
+ VDUP(vector2, q, int, s, 16, 8, 0x33);
+ VDUP(vector2, q, int, s, 32, 4, 0x22);
+
+ TEST_VQDMULH(, int, s, 16, 4, expected_cumulative_sat, "");
+ TEST_VQDMULH(, int, s, 32, 2, expected_cumulative_sat, "");
+ TEST_VQDMULH(q, int, s, 16, 8, expected_cumulative_sat, "");
+ TEST_VQDMULH(q, int, s, 32, 4, expected_cumulative_sat, "");
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected, "");
+
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector2, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector2, , int, s, 32, 2, 0x80000000);
+ VDUP(vector, q, int, s, 16, 8, 0x8000);
+ VDUP(vector2, q, int, s, 16, 8, 0x8000);
+ VDUP(vector, q, int, s, 32, 4, 0x80000000);
+ VDUP(vector2, q, int, s, 32, 4, 0x80000000);
+
+#define TEST_MSG2 "with saturation"
+ TEST_VQDMULH(, int, s, 16, 4, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH(, int, s, 32, 2, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH(q, int, s, 16, 8, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH(q, int, s, 32, 4, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (29 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-19 16:47 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
` (5 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c
new file mode 100644
index 0000000..5260676
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c
@@ -0,0 +1,121 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+int VECT_VAR(expected_cumulative_sat,int,16,8) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,16,8) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,16,4) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,2) [] = { 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,16,8) [] = { 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff };
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+
+#define INSN_NAME vqdmulh
+#define TEST_MSG "VQDMULH_LANE"
+#define FNNAME1(NAME) exec_ ## NAME ## _lane
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vqdmulh_lane(vector,vector2,lane), then store the result. */
+#define TEST_VQDMULH_LANE2(INSN, Q, T1, T2, W, N, N2, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N2), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULH_LANE1(INSN, Q, T1, T2, W, N, N2, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH_LANE2(INSN, Q, T1, T2, W, N, N2, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULH_LANE(Q, T1, T2, W, N, N2, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULH_LANE1(INSN_NAME, Q, T1, T2, W, N, N2, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ /* vector2: vqdmulh_lane and vqdmulhq_lane have a 2nd argument with
+ the same number of elements, so we need only one variable of each
+ type. */
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0xBB);
+
+ /* Choose lane arbitrarily. */
+ TEST_VQDMULH_LANE(, int, s, 16, 4, 4, 2, expected_cumulative_sat, "");
+ TEST_VQDMULH_LANE(, int, s, 32, 2, 2, 1, expected_cumulative_sat, "");
+ TEST_VQDMULH_LANE(q, int, s, 16, 8, 4, 3, expected_cumulative_sat, "");
+ TEST_VQDMULH_LANE(q, int, s, 32, 4, 2, 0, expected_cumulative_sat, "");
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected, "");
+
+ /* Choose input values to trigger saturation. */
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector, q, int, s, 16, 8, 0x8000);
+ VDUP(vector, q, int, s, 32, 4, 0x80000000);
+ VDUP(vector2, , int, s, 16, 4, 0x8000);
+ VDUP(vector2, , int, s, 32, 2, 0x80000000);
+
+#define TEST_MSG2 " (check mul cumulative saturation)"
+ TEST_VQDMULH_LANE(, int, s, 16, 4, 4, 3, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_LANE(, int, s, 32, 2, 2, 1, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_LANE(q, int, s, 16, 8, 4, 2, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULH_LANE(q, int, s, 32, 4, 2, 1, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK (TEST_MSG, int, 16, 4, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 2, PRIx32, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 16, 8, PRIx16, expected2, TEST_MSG2);
+ CHECK (TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (4 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
` (30 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc
new file mode 100644
index 0000000..705f90a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc
@@ -0,0 +1,73 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vqdmlXl_lane(vector, vector3, vector4, lane),
+ then store the result. */
+#define TEST_VQDMLXL_LANE1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector3, T1, W2, N), \
+ VECT_VAR(vector4, T1, W2, N), \
+ V); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMLXL_LANE(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMLXL_LANE1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector4, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector4, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+
+ VDUP(vector3, , int, s, 16, 4, 0x55);
+ VDUP(vector4, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0x55);
+ VDUP(vector4, , int, s, 32, 2, 0xBB);
+
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat, "");
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat, "");
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+
+#define TEST_MSG2 "(mul with input=0)"
+ VDUP(vector3, , int, s, 16, 4, 0);
+ VDUP(vector3, , int, s, 32, 2, 0);
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+
+#define TEST_MSG3 "(mul with saturation)"
+ VDUP(vector3, , int, s, 16, 4, 0x8000);
+ VDUP(vector3, , int, s, 32, 2, 0x80000000);
+ VDUP(vector4, , int, s, 16, 4, 0x8000);
+ VDUP(vector4, , int, s, 32, 2, 0x80000000);
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat3, TEST_MSG3);
+ TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat3, TEST_MSG3);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected3, TEST_MSG3);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected3, TEST_MSG3);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c
new file mode 100644
index 0000000..832a705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c
@@ -0,0 +1,38 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlal_lane
+#define TEST_MSG "VQDMLAL_LANE"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x7c1e, 0x7c1f, 0x7c20, 0x7c21 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x7c1e, 0x7c1f };
+
+/* Expected values of cumulative_saturation flag when multiplying with
+ 0. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 0;
+
+/* Expected values when multiplying with 0. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+
+/* Expected values of cumulative_saturation flag when multiplication
+ saturates. */
+int VECT_VAR(expected_cumulative_sat3,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat3,int,64,2) = 1;
+
+/* Expected values when multiplication saturates. */
+VECT_VAR_DECL(expected3,int,32,4) [] = { 0x7fffffef, 0x7ffffff0,
+ 0x7ffffff1, 0x7ffffff2 };
+VECT_VAR_DECL(expected3,int,64,2) [] = { 0x7fffffffffffffef,
+ 0x7ffffffffffffff0 };
+
+#include "vqdmlXl_lane.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c
new file mode 100644
index 0000000..b95e61c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c
@@ -0,0 +1,40 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlsl_lane
+#define TEST_MSG "VQDMLSL_LANE"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffff83c2, 0xffff83c3,
+ 0xffff83c4, 0xffff83c5 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffff83c2,
+ 0xffffffffffff83c3 };
+
+/* Expected values of cumulative_saturation flag when multiplying with
+ 0. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 0;
+
+/* Expected values when multiplying with 0. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+
+/* Expected values of cumulative_saturation flag when multiplication
+ saturates. */
+int VECT_VAR(expected_cumulative_sat3,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat3,int,64,2) = 1;
+
+/* Expected values when multiplication saturates. */
+VECT_VAR_DECL(expected3,int,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected3,int,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+#include "vqdmlXl_lane.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (19 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 14:08 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
` (15 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
new file mode 100644
index 0000000..36efe3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
@@ -0,0 +1,120 @@
+/* Can't use the standard binary_op.inc template because vmax has no
+ 64 bits variant. */
+
+#include <math.h>
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ int i;
+
+ /* Basic test: y=vmax(x,x), then store the result. */
+#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N) \
+ TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+#ifndef NO_FLOAT_VARIANT
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+#endif
+
+ /* Choose init value arbitrarily, will be used as comparison value. */
+ VDUP(vector2, , int, s, 8, 8, -13);
+ VDUP(vector2, , int, s, 16, 4, -14);
+ VDUP(vector2, , int, s, 32, 2, -16);
+ VDUP(vector2, , uint, u, 8, 8, 0xf3);
+ VDUP(vector2, , uint, u, 16, 4, 0xfff1);
+ VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
+ VDUP(vector2, q, int, s, 8, 16, -12);
+ VDUP(vector2, q, int, s, 16, 8, -13);
+ VDUP(vector2, q, int, s, 32, 4, -15);
+ VDUP(vector2, q, uint, u, 8, 16, 0xf9);
+ VDUP(vector2, q, uint, u, 16, 8, 0xfff2);
+ VDUP(vector2, q, uint, u, 32, 4, 0xfffffff1);
+#ifndef NO_FLOAT_VARIANT
+ VDUP(vector2, , float, f, 32, 2, -15.5f);
+ VDUP(vector2, q, float, f, 32, 4, -14.5f);
+#endif
+
+#ifndef NO_FLOAT_VARIANT
+#define FLOAT_VARIANT(MACRO, VAR) \
+ MACRO(VAR, , float, f, 32, 2); \
+ MACRO(VAR, q, float, f, 32, 4)
+#else
+#define FLOAT_VARIANT(MACRO, VAR)
+#endif
+
+#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR) \
+ MACRO(VAR, , int, s, 8, 8); \
+ MACRO(VAR, , int, s, 16, 4); \
+ MACRO(VAR, , int, s, 32, 2); \
+ MACRO(VAR, , uint, u, 8, 8); \
+ MACRO(VAR, , uint, u, 16, 4); \
+ MACRO(VAR, , uint, u, 32, 2); \
+ MACRO(VAR, q, int, s, 8, 16); \
+ MACRO(VAR, q, int, s, 16, 8); \
+ MACRO(VAR, q, int, s, 32, 4); \
+ MACRO(VAR, q, uint, u, 8, 16); \
+ MACRO(VAR, q, uint, u, 16, 8); \
+ MACRO(VAR, q, uint, u, 32, 4); \
+ FLOAT_VARIANT(MACRO, VAR)
+
+ /* Apply a binary operator named INSN_NAME. */
+ TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME);
+
+ CHECK_RESULTS (TEST_MSG, "");
+
+#ifndef NO_FLOAT_VARIANT
+ /* Extra FP tests with special values (NaN, ....) */
+ VDUP(vector, q, float, f, 32, 4, 1.0f);
+ VDUP(vector2, q, float, f, 32, 4, NAN);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, " FP special (NaN)");
+
+ VDUP(vector, q, float, f, 32, 4, -NAN);
+ VDUP(vector2, q, float, f, 32, 4, 1.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_mnan, " FP special (-NaN)");
+
+ VDUP(vector, q, float, f, 32, 4, 1.0f);
+ VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_inf, " FP special (inf)");
+
+ VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ VDUP(vector2, q, float, f, 32, 4, 1.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_minf, " FP special (-inf)");
+
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ VDUP(vector2, q, float, f, 32, 4, -0.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero1, " FP special (-0.0)");
+
+ VDUP(vector, q, float, f, 32, 4, -0.0f);
+ VDUP(vector2, q, float, f, 32, 4, 0.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero2, " FP special (-0.0)");
+#endif
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c
new file mode 100644
index 0000000..0c67df9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c
@@ -0,0 +1,54 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vhadd
+#define TEST_MSG "VHADD/VHADDQ"
+
+#define NO_FLOAT_VARIANT
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf2, 0xf2, 0xf3,
+ 0xf3, 0xf4, 0xf4, 0xf5 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf2, 0xf2, 0xf3,
+ 0xf3, 0xf4, 0xf4, 0xf5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5,
+ 0xf6, 0xf6, 0xf7, 0xf7,
+ 0xf8, 0xf8, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff4, 0xfff4, 0xfff5 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff2 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf4, 0xf5, 0xf5, 0xf6,
+ 0xf6, 0xf7, 0xf7, 0xf8,
+ 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2,
+ 0xfff3, 0xfff3, 0xfff4, 0xfff4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff2 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c
new file mode 100644
index 0000000..2431288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vhsub
+#define TEST_MSG "VHSUB/VHSUBQ"
+
+#define NO_FLOAT_VARIANT
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xfe, 0xff, 0xff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfe, 0xff, 0xff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0x0, 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xfe, 0xfe, 0xff, 0xff,
+ 0x0, 0x0, 0x1, 0x1,
+ 0x2, 0x2, 0x3, 0x3,
+ 0x4, 0x4, 0x5, 0x5 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffe, 0xffff, 0xffff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0x0, 0x0, 0x1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfb, 0xfc, 0xfc, 0xfd,
+ 0xfd, 0xfe, 0xfe, 0xff,
+ 0xff, 0x0, 0x0, 0x1,
+ 0x1, 0x2, 0x2, 0x3 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffff, 0xffff, 0x0, 0x0,
+ 0x1, 0x1, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
new file mode 100644
index 0000000..2591b16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
@@ -0,0 +1,64 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmax
+#define TEST_MSG "VMAX/VMAXQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf9, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
+ 0xc1600000, 0xc1500000 };
+
+/* Expected results with special FP values. */
+VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
+ 0x7f800000, 0x7f800000 };
+VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
+ 0x3f800000, 0x3f800000 };
+VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
new file mode 100644
index 0000000..2b5e87c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
@@ -0,0 +1,66 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmin
+#define TEST_MSG "VMIN/VMINQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf3, 0xf3, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf3, 0xf3, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf4, 0xf4, 0xf4 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
+ 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1680000, 0xc1680000 };
+/* Expected results with special FP values. */
+VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
+ 0x3f800000, 0x3f800000 };
+VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0xff800000, 0xff800000,
+ 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c
new file mode 100644
index 0000000..8629beb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c
@@ -0,0 +1,54 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vrhadd
+#define TEST_MSG "VRHADD/VRHADDQ"
+
+#define NO_FLOAT_VARIANT
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf3, 0xf3, 0xf4,
+ 0xf4, 0xf5, 0xf5, 0xf6,
+ 0xf6, 0xf7, 0xf7, 0xf8,
+ 0xf8, 0xf9, 0xf9, 0xfa };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff2, 0xfff2, 0xfff3, 0xfff3,
+ 0xfff4, 0xfff4, 0xfff5, 0xfff5 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff2 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf5, 0xf5, 0xf6, 0xf6,
+ 0xf7, 0xf7, 0xf8, 0xf8,
+ 0xf9, 0xf9, 0xfa, 0xfa,
+ 0xfb, 0xfb, 0xfc, 0xfc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff4, 0xfff4, 0xfff5 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff2 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "binary_op_no64.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (17 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
` (17 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
vXXXw.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc
new file mode 100644
index 0000000..c535557
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc
@@ -0,0 +1,70 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=vaddw(x1,x2), then store the result. */
+#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
+ TEST_VADDW1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector2, int, 8, 8);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 8, 8);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector2, , int, s, 8, 8, -13);
+ VDUP(vector2, , int, s, 16, 4, -14);
+ VDUP(vector2, , int, s, 32, 2, -16);
+ VDUP(vector2, , uint, u, 8, 8, 0xf3);
+ VDUP(vector2, , uint, u, 16, 4, 0xfff1);
+ VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
+
+ /* Execute the tests. */
+ TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
+ TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
+ TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
+ TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
+ TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
+ TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
index 95cbb31..27f54f6 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
@@ -2,6 +2,9 @@
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
+#define INSN_NAME vaddw
+#define TEST_MSG "VADDW"
+
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
@@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
0x33333333, 0x33333333 };
-#define INSN_NAME vaddw
-#define TEST_MSG "VADDW"
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* Basic test: y=vaddw(x1,x2), then store the result. */
-#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
- VECT_VAR(vector_res, T1, W2, N) = \
- INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
-
-#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
- TEST_VADDW1(INSN, T1, T2, W, W2, N)
-
- DECL_VARIABLE(vector, int, 16, 8);
- DECL_VARIABLE(vector, int, 32, 4);
- DECL_VARIABLE(vector, int, 64, 2);
- DECL_VARIABLE(vector, uint, 16, 8);
- DECL_VARIABLE(vector, uint, 32, 4);
- DECL_VARIABLE(vector, uint, 64, 2);
-
- DECL_VARIABLE(vector2, int, 8, 8);
- DECL_VARIABLE(vector2, int, 16, 4);
- DECL_VARIABLE(vector2, int, 32, 2);
- DECL_VARIABLE(vector2, uint, 8, 8);
- DECL_VARIABLE(vector2, uint, 16, 4);
- DECL_VARIABLE(vector2, uint, 32, 2);
-
- DECL_VARIABLE(vector_res, int, 16, 8);
- DECL_VARIABLE(vector_res, int, 32, 4);
- DECL_VARIABLE(vector_res, int, 64, 2);
- DECL_VARIABLE(vector_res, uint, 16, 8);
- DECL_VARIABLE(vector_res, uint, 32, 4);
- DECL_VARIABLE(vector_res, uint, 64, 2);
-
- clean_results ();
-
- /* Initialize input "vector" from "buffer". */
- VLOAD(vector, buffer, q, int, s, 16, 8);
- VLOAD(vector, buffer, q, int, s, 32, 4);
- VLOAD(vector, buffer, q, int, s, 64, 2);
- VLOAD(vector, buffer, q, uint, u, 16, 8);
- VLOAD(vector, buffer, q, uint, u, 32, 4);
- VLOAD(vector, buffer, q, uint, u, 64, 2);
-
- /* Choose init value arbitrarily. */
- VDUP(vector2, , int, s, 8, 8, -13);
- VDUP(vector2, , int, s, 16, 4, -14);
- VDUP(vector2, , int, s, 32, 2, -16);
- VDUP(vector2, , uint, u, 8, 8, 0xf3);
- VDUP(vector2, , uint, u, 16, 4, 0xfff1);
- VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
-
- /* Execute the tests. */
- TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
- TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
- TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
- TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
- TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
- TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
-
- CHECK_RESULTS (TEST_MSG, "");
-}
-
-int main (void)
-{
- FNNAME (INSN_NAME) ();
- return 0;
-}
+#include "vXXXw.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
new file mode 100644
index 0000000..3e8bc98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
@@ -0,0 +1,50 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsubw
+#define TEST_MSG "VSUBW"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
+ 0x1, 0x2, 0x3, 0x4 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfefd, 0xfefe, 0xfeff, 0xff00,
+ 0xff01, 0xff02, 0xff03, 0xff04 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffeffff, 0xffff0000,
+ 0xffff0001, 0xffff0002 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffff00000000,
+ 0xffffffff00000001 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vXXXw.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (5 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:11 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
` (29 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsri_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
new file mode 100644
index 0000000..32c0d86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsXi_n.inc
@@ -0,0 +1,82 @@
+#define FNNAME1(NAME) exec_ ## NAME ##_n
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vsxi_n(vector, vector2, val),
+ then store the result. */
+#define TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VSXI_N(INSN, Q, T1, T2, W, N, V) \
+ TEST_VSXI_N1(INSN, Q, T1, T2, W, N, V)
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Fill input vector2 with arbitrary values. */
+ VDUP(vector2, , int, s, 8, 8, 2);
+ VDUP(vector2, , int, s, 16, 4, -4);
+ VDUP(vector2, , int, s, 32, 2, 3);
+ VDUP(vector2, , int, s, 64, 1, 100);
+ VDUP(vector2, , uint, u, 8, 8, 20);
+ VDUP(vector2, , uint, u, 16, 4, 30);
+ VDUP(vector2, , uint, u, 32, 2, 40);
+ VDUP(vector2, , uint, u, 64, 1, 2);
+ VDUP(vector2, , poly, p, 8, 8, 20);
+ VDUP(vector2, , poly, p, 16, 4, 30);
+ VDUP(vector2, q, int, s, 8, 16, -10);
+ VDUP(vector2, q, int, s, 16, 8, -20);
+ VDUP(vector2, q, int, s, 32, 4, -30);
+ VDUP(vector2, q, int, s, 64, 2, 24);
+ VDUP(vector2, q, uint, u, 8, 16, 12);
+ VDUP(vector2, q, uint, u, 16, 8, 3);
+ VDUP(vector2, q, uint, u, 32, 4, 55);
+ VDUP(vector2, q, uint, u, 64, 2, 3);
+ VDUP(vector2, q, poly, p, 8, 16, 12);
+ VDUP(vector2, q, poly, p, 16, 8, 3);
+
+ /* Choose shift amount arbitrarily. */
+ TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 4);
+ TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 3);
+ TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 1);
+ TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 32);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 2);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 10);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 30);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 3);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 2);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 10);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 5);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 3);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 20);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 16);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 3);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 12);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 23);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 53);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 3);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 12);
+
+ CHECK_RESULTS (TEST_MSG, "");
+
+#ifdef EXTRA_TESTS
+ EXTRA_TESTS();
+#endif
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
new file mode 100644
index 0000000..342aec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsli_n.c
@@ -0,0 +1,162 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsli
+#define TEST_MSG "VSLI_N"
+
+/* Extra tests for functions requiring corner cases tests. */
+void vsli_extra(void);
+#define EXTRA_TESTS vsli_extra
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x20, 0x21, 0x22, 0x23,
+ 0x24, 0x25, 0x26, 0x27 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe0, 0xffe1, 0xffe2, 0xffe3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x6, 0x7 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x64fffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
+ 0x50, 0x51, 0x52, 0x53 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3ffffff0, 0x3ffffff1 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x10 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x50, 0x51, 0x52, 0x53,
+ 0x50, 0x51, 0x52, 0x53 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x7bf0, 0x7bf1, 0x7bf2, 0x7bf3 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xd0, 0xd1, 0xd2, 0xd3,
+ 0xd4, 0xd5, 0xd6, 0xd7,
+ 0xd8, 0xd9, 0xda, 0xdb,
+ 0xdc, 0xdd, 0xde, 0xdf };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xff60, 0xff61, 0xff62, 0xff63,
+ 0xff64, 0xff65, 0xff66, 0xff67 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfe2ffff0, 0xfe2ffff1,
+ 0xfe2ffff2, 0xfe2ffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x18fff0, 0x18fff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
+ 0x64, 0x65, 0x66, 0x67,
+ 0x60, 0x61, 0x62, 0x63,
+ 0x64, 0x65, 0x66, 0x67 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
+ 0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1bfffff0, 0x1bfffff1,
+ 0x1bfffff2, 0x1bfffff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x7ffffffffffff0, 0x7ffffffffffff1 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x60, 0x61, 0x62, 0x63,
+ 0x64, 0x65, 0x66, 0x67,
+ 0x60, 0x61, 0x62, 0x63,
+ 0x64, 0x65, 0x66, 0x67 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3ff0, 0x3ff1, 0x3ff2, 0x3ff3,
+ 0x3ff4, 0x3ff5, 0x3ff6, 0x3ff7 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* Expected results with max shift amount. */
+VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0x7ff0, 0x7ff1,
+ 0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0x7ffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0x7ff0, 0x7ff1,
+ 0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0x7ffffff0, 0x7ffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0x7ffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77 };
+VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0x7ff0, 0x7ff1,
+ 0x7ff2, 0x7ff3 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77,
+ 0x78, 0x79, 0x7a, 0x7b,
+ 0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3,
+ 0x7ff4, 0x7ff5, 0x7ff6, 0x7ff7 };
+VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0x7ffffff0, 0x7ffffff1,
+ 0x7ffffff2, 0x7ffffff3 };
+VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0x7ffffffffffffff0,
+ 0x7ffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77,
+ 0x78, 0x79, 0x7a, 0x7b,
+ 0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0x70, 0x71, 0x72, 0x73,
+ 0x74, 0x75, 0x76, 0x77,
+ 0x78, 0x79, 0x7a, 0x7b,
+ 0x7c, 0x7d, 0x7e, 0x7f };
+VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vsXi_n.inc"
+
+void vsli_extra(void)
+{
+ /* Test cases with maximum shift amount (this amount is different
+ * from vsri. */
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Fill input vector2 with arbitrary values. */
+ VDUP(vector2, , int, s, 8, 8, 2);
+ VDUP(vector2, , int, s, 16, 4, -4);
+ VDUP(vector2, , int, s, 32, 2, 3);
+ VDUP(vector2, , int, s, 64, 1, 100);
+ VDUP(vector2, , uint, u, 8, 8, 20);
+ VDUP(vector2, , uint, u, 16, 4, 30);
+ VDUP(vector2, , uint, u, 32, 2, 40);
+ VDUP(vector2, , uint, u, 64, 1, 2);
+ VDUP(vector2, , poly, p, 8, 8, 20);
+ VDUP(vector2, , poly, p, 16, 4, 30);
+ VDUP(vector2, q, int, s, 8, 16, -10);
+ VDUP(vector2, q, int, s, 16, 8, -20);
+ VDUP(vector2, q, int, s, 32, 4, -30);
+ VDUP(vector2, q, int, s, 64, 2, 24);
+ VDUP(vector2, q, uint, u, 8, 16, 12);
+ VDUP(vector2, q, uint, u, 16, 8, 3);
+ VDUP(vector2, q, uint, u, 32, 4, 55);
+ VDUP(vector2, q, uint, u, 64, 2, 3);
+ VDUP(vector2, q, poly, p, 8, 16, 12);
+ VDUP(vector2, q, poly, p, 16, 8, 3);
+
+ /* Use maximum allowed shift amount. */
+ TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 7);
+ TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 15);
+ TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 31);
+ TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 63);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 7);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 15);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 31);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 63);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 7);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 15);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 7);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 15);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 31);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 63);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 7);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 15);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 31);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 63);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 7);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 15);
+
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
new file mode 100644
index 0000000..fd85331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsri_n.c
@@ -0,0 +1,164 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsri
+#define TEST_MSG "VSRI_N"
+
+/* Extra tests for functions requiring corner cases tests. */
+void vsri_extra(void);
+#define EXTRA_TESTS vsri_extra
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf0, 0xf0, 0xf0, 0xf0 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0xffff, 0xffff };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x80000001, 0x80000001 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffff00000000 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
+ 0xc5, 0xc5, 0xc5, 0xc5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xe000000000000000 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xc5, 0xc5, 0xc5, 0xc5,
+ 0xc5, 0xc5, 0xc5, 0xc5 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xffc0, 0xffc0, 0xffc0, 0xffc0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf7, 0xf7, 0xf7, 0xf7,
+ 0xf7, 0xf7, 0xf7, 0xf7,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+ 0xfffd, 0xfffd, 0xfffd, 0xfffd };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffff000000000000,
+ 0xffff000000000000 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffe00, 0xfffffe00,
+ 0xfffffe00, 0xfffffe00 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffff800,
+ 0xfffffffffffff800 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1,
+ 0xe1, 0xe1, 0xe1, 0xe1 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 0xfff0, 0xfff0, 0xfff0, 0xfff0 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* Expected results with max shift amount. */
+VECT_VAR_DECL(expected_max_shift,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,int,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,uint,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_max_shift,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected_max_shift,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_max_shift,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_max_shift,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_max_shift,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected_max_shift,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected_max_shift,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vsXi_n.inc"
+
+void vsri_extra(void)
+{
+ /* Test cases with maximum shift amount (this amount is different
+ * from vsli. */
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+
+ /* Fill input vector2 with arbitrary values. */
+ VDUP(vector2, , int, s, 8, 8, 2);
+ VDUP(vector2, , int, s, 16, 4, -4);
+ VDUP(vector2, , int, s, 32, 2, 3);
+ VDUP(vector2, , int, s, 64, 1, 100);
+ VDUP(vector2, , uint, u, 8, 8, 20);
+ VDUP(vector2, , uint, u, 16, 4, 30);
+ VDUP(vector2, , uint, u, 32, 2, 40);
+ VDUP(vector2, , uint, u, 64, 1, 2);
+ VDUP(vector2, , poly, p, 8, 8, 20);
+ VDUP(vector2, , poly, p, 16, 4, 30);
+ VDUP(vector2, q, int, s, 8, 16, -10);
+ VDUP(vector2, q, int, s, 16, 8, -20);
+ VDUP(vector2, q, int, s, 32, 4, -30);
+ VDUP(vector2, q, int, s, 64, 2, 24);
+ VDUP(vector2, q, uint, u, 8, 16, 12);
+ VDUP(vector2, q, uint, u, 16, 8, 3);
+ VDUP(vector2, q, uint, u, 32, 4, 55);
+ VDUP(vector2, q, uint, u, 64, 2, 3);
+ VDUP(vector2, q, poly, p, 8, 16, 12);
+ VDUP(vector2, q, poly, p, 16, 8, 3);
+
+ /* Use maximum allowed shift amount. */
+ TEST_VSXI_N(INSN_NAME, , int, s, 8, 8, 8);
+ TEST_VSXI_N(INSN_NAME, , int, s, 16, 4, 16);
+ TEST_VSXI_N(INSN_NAME, , int, s, 32, 2, 32);
+ TEST_VSXI_N(INSN_NAME, , int, s, 64, 1, 64);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 8, 8, 8);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 16, 4, 16);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 32, 2, 32);
+ TEST_VSXI_N(INSN_NAME, , uint, u, 64, 1, 64);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 8, 8, 8);
+ TEST_VSXI_N(INSN_NAME, , poly, p, 16, 4, 16);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 8, 16, 8);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 16, 8, 16);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 32, 4, 32);
+ TEST_VSXI_N(INSN_NAME, q, int, s, 64, 2, 64);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 8, 16, 8);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 16, 8, 16);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 32, 4, 32);
+ TEST_VSXI_N(INSN_NAME, q, uint, u, 64, 2, 64);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 8, 16, 8);
+ TEST_VSXI_N(INSN_NAME, q, poly, p, 16, 8, 16);
+
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_max_shift, "(max shift amount)");
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (23 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
` (11 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
new file mode 100644
index 0000000..df28a94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
@@ -0,0 +1,61 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x11000, 0x11000, 0x11000, 0x11000 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x22000, 0x22000 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33000, 0x33000, 0x33000, 0x33000 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x44000, 0x44000 };
+
+#define INSN_NAME vmull
+#define TEST_MSG "VMULL_N"
+void exec_vmull_n (void)
+{
+ int i;
+
+ /* vector_res = vmull_n(vector,val), then store the result. */
+#define TEST_VMULL_N1(INSN, T1, T2, W, W2, N, L) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ L); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+#define TEST_VMULL_N(INSN, T1, T2, W, W2, N, L) \
+ TEST_VMULL_N1(INSN, T1, T2, W, W2, N, L)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize vector. */
+ VDUP(vector, , int, s, 16, 4, 0x1000);
+ VDUP(vector, , int, s, 32, 2, 0x1000);
+ VDUP(vector, , uint, u, 16, 4, 0x1000);
+ VDUP(vector, , uint, u, 32, 2, 0x1000);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMULL_N(INSN_NAME, int, s, 16, 32, 4, 0x11);
+ TEST_VMULL_N(INSN_NAME, int, s, 32, 64, 2, 0x22);
+ TEST_VMULL_N(INSN_NAME, uint, u, 16, 32, 4, 0x33);
+ TEST_VMULL_N(INSN_NAME, uint, u, 32, 64, 2, 0x44);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vmull_n ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (28 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
` (6 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
Add trace.
(CHECK_FP): Likewise.
(CHECK_CUMULATIVE_SAT): Likewise.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 6464c66..2730a66 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -79,6 +79,7 @@ extern size_t strlen(const char *);
abort(); \
} \
} \
+ fprintf(stderr, "CHECKED %s\n", MSG); \
}
/* Floating-point variant. */
@@ -107,6 +108,7 @@ extern size_t strlen(const char *);
abort(); \
} \
} \
+ fprintf(stderr, "CHECKED %s\n", MSG); \
}
/* Clean buffer with a non-zero pattern to help diagnose buffer
@@ -323,6 +325,7 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
strlen(COMMENT) > 0 ? " " COMMENT : ""); \
abort(); \
} \
+ fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG); \
}
#define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment) \
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (8 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 15:35 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
` (26 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
new file mode 100644
index 0000000..53cd8f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
@@ -0,0 +1,671 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+
+/* vld2_dup/chunk 0. */
+VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld2_dup/chunk 1. */
+VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
+ 0xf0, 0xf1, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld3_dup/chunk 0. */
+VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
+ 0xf1, 0xf2, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld3_0,int,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff0 };
+VECT_VAR_DECL(expected_vld3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld3_0,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld3_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
+ 0xf1, 0xf2, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld3_0,uint,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff0 };
+VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
+ 0xf1, 0xf2, 0xf0, 0xf1 };
+VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff0 };
+VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld3_dup/chunk 1. */
+VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
+ 0xf0, 0xf1, 0xf2, 0xf0 };
+VECT_VAR_DECL(expected_vld3_1,int,16,4) [] = { 0xfff1, 0xfff2,
+ 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld3_1,int,32,2) [] = { 0xfffffff2, 0xfffffff0 };
+VECT_VAR_DECL(expected_vld3_1,int,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld3_1,uint,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
+ 0xf0, 0xf1, 0xf2, 0xf0 };
+VECT_VAR_DECL(expected_vld3_1,uint,16,4) [] = { 0xfff1, 0xfff2,
+ 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff0 };
+VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
+ 0xf0, 0xf1, 0xf2, 0xf0 };
+VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2,
+ 0xfff0, 0xfff1 };
+VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 };
+VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld3_dup/chunk 2. */
+VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
+ 0xf2, 0xf0, 0xf1, 0xf2 };
+VECT_VAR_DECL(expected_vld3_2,int,16,4) [] = { 0xfff2, 0xfff0,
+ 0xfff1, 0xfff2 };
+VECT_VAR_DECL(expected_vld3_2,int,32,2) [] = { 0xfffffff1, 0xfffffff2 };
+VECT_VAR_DECL(expected_vld3_2,int,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(expected_vld3_2,uint,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
+ 0xf2, 0xf0, 0xf1, 0xf2 };
+VECT_VAR_DECL(expected_vld3_2,uint,16,4) [] = { 0xfff2, 0xfff0,
+ 0xfff1, 0xfff2 };
+VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 };
+VECT_VAR_DECL(expected_vld3_2,uint,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
+ 0xf2, 0xf0, 0xf1, 0xf2 };
+VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0,
+ 0xfff1, 0xfff2 };
+VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 };
+VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld4_dup/chunk 0. */
+VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_0,int,16,4) [] = { 0xfff0, 0xfff1,
+ 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld4_0,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld4_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld4_dup/chunk 1. */
+VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_vld4_1,int,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld4_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
+VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld4_dup/chunk 2. */
+VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_2,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_2,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld4_2,int,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(expected_vld4_2,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_2,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 };
+VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
+VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+/* vld4_dup/chunk3. */
+VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_3,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_3,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_vld4_3,int,64,1) [] = { 0xfffffffffffffff3 };
+VECT_VAR_DECL(expected_vld4_3,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_3,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 };
+VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf0, 0xf1, 0xf2, 0xf3 };
+VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
+VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333,
+ 0x3333333333333333 };
+VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+void exec_vldX_dup (void)
+{
+ /* In this case, input variables are arrays of vectors. */
+#define DECL_VLDX_DUP(T1, W, N, X) \
+ VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
+ VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
+
+ /* We need to use a temporary result buffer (result_bis), because
+ the one used for other tests is not large enough. A subset of the
+ result data is moved from result_bis to result, and it is this
+ subset which is used to check the actual behaviour. The next
+ macro enables to move another chunk of data from result_bis to
+ result. */
+#define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \
+ VECT_ARRAY_VAR(vector, T1, W, N, X) = \
+ vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \
+ \
+ vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
+ VECT_ARRAY_VAR(vector, T1, W, N, X)); \
+ memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+
+ /* Overwrite "result" with the contents of "result_bis"[Y]. */
+#define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \
+ memcpy(VECT_VAR(result, T1, W, N), \
+ &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
+ sizeof(VECT_VAR(result, T1, W, N)));
+
+#define DECL_ALL_VLDX_DUP(X) \
+ DECL_VLDX_DUP(int, 8, 8, X); \
+ DECL_VLDX_DUP(int, 16, 4, X); \
+ DECL_VLDX_DUP(int, 32, 2, X); \
+ DECL_VLDX_DUP(int, 64, 1, X); \
+ DECL_VLDX_DUP(uint, 8, 8, X); \
+ DECL_VLDX_DUP(uint, 16, 4, X); \
+ DECL_VLDX_DUP(uint, 32, 2, X); \
+ DECL_VLDX_DUP(uint, 64, 1, X); \
+ DECL_VLDX_DUP(poly, 8, 8, X); \
+ DECL_VLDX_DUP(poly, 16, 4, X); \
+ DECL_VLDX_DUP(float, 32, 2, X)
+
+#define TEST_ALL_VLDX_DUP(X) \
+ TEST_VLDX_DUP(, int, s, 8, 8, X); \
+ TEST_VLDX_DUP(, int, s, 16, 4, X); \
+ TEST_VLDX_DUP(, int, s, 32, 2, X); \
+ TEST_VLDX_DUP(, int, s, 64, 1, X); \
+ TEST_VLDX_DUP(, uint, u, 8, 8, X); \
+ TEST_VLDX_DUP(, uint, u, 16, 4, X); \
+ TEST_VLDX_DUP(, uint, u, 32, 2, X); \
+ TEST_VLDX_DUP(, uint, u, 64, 1, X); \
+ TEST_VLDX_DUP(, poly, p, 8, 8, X); \
+ TEST_VLDX_DUP(, poly, p, 16, 4, X); \
+ TEST_VLDX_DUP(, float, f, 32, 2, X)
+
+#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
+ TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
+ TEST_EXTRA_CHUNK(int, 64, 1, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
+ TEST_EXTRA_CHUNK(uint, 64, 1, X, Y); \
+ TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
+ TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
+ TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
+
+
+ DECL_ALL_VLDX_DUP(2);
+ DECL_ALL_VLDX_DUP(3);
+ DECL_ALL_VLDX_DUP(4);
+
+ /* Special input buffers of suitable size are needed for vld2/vld3/vld4. */
+ /* Input buffers for vld2, 1 of each size */
+ VECT_ARRAY_INIT2(buffer_vld2, int, 8, 8);
+ PAD(buffer_vld2_pad, int, 8, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 16, 4);
+ PAD(buffer_vld2_pad, int, 16, 4);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 32, 2);
+ PAD(buffer_vld2_pad, int, 32, 2);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 64, 1);
+ PAD(buffer_vld2_pad, int, 64, 1);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 8);
+ PAD(buffer_vld2_pad, uint, 8, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 4);
+ PAD(buffer_vld2_pad, uint, 16, 4);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 2);
+ PAD(buffer_vld2_pad, uint, 32, 2);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 1);
+ PAD(buffer_vld2_pad, uint, 64, 1);
+ VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 8);
+ PAD(buffer_vld2_pad, poly, 8, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4);
+ PAD(buffer_vld2_pad, poly, 16, 4);
+ VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2);
+ PAD(buffer_vld2_pad, float, 32, 2);
+
+ VECT_ARRAY_INIT2(buffer_vld2, int, 8, 16);
+ PAD(buffer_vld2_pad, int, 8, 16);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 16, 8);
+ PAD(buffer_vld2_pad, int, 16, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 32, 4);
+ PAD(buffer_vld2_pad, int, 32, 4);
+ VECT_ARRAY_INIT2(buffer_vld2, int, 64, 2);
+ PAD(buffer_vld2_pad, int, 64, 2);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 16);
+ PAD(buffer_vld2_pad, uint, 8, 16);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 8);
+ PAD(buffer_vld2_pad, uint, 16, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 4);
+ PAD(buffer_vld2_pad, uint, 32, 4);
+ VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 2);
+ PAD(buffer_vld2_pad, uint, 64, 2);
+ VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 16);
+ PAD(buffer_vld2_pad, poly, 8, 16);
+ VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8);
+ PAD(buffer_vld2_pad, poly, 16, 8);
+ VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4);
+ PAD(buffer_vld2_pad, float, 32, 4);
+
+ /* Input buffers for vld3, 1 of each size */
+ VECT_ARRAY_INIT3(buffer_vld3, int, 8, 8);
+ PAD(buffer_vld3_pad, int, 8, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 16, 4);
+ PAD(buffer_vld3_pad, int, 16, 4);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 32, 2);
+ PAD(buffer_vld3_pad, int, 32, 2);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 64, 1);
+ PAD(buffer_vld3_pad, int, 64, 1);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 8);
+ PAD(buffer_vld3_pad, uint, 8, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 4);
+ PAD(buffer_vld3_pad, uint, 16, 4);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 2);
+ PAD(buffer_vld3_pad, uint, 32, 2);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 1);
+ PAD(buffer_vld3_pad, uint, 64, 1);
+ VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 8);
+ PAD(buffer_vld3_pad, poly, 8, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4);
+ PAD(buffer_vld3_pad, poly, 16, 4);
+ VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2);
+ PAD(buffer_vld3_pad, float, 32, 2);
+
+ VECT_ARRAY_INIT3(buffer_vld3, int, 8, 16);
+ PAD(buffer_vld3_pad, int, 8, 16);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 16, 8);
+ PAD(buffer_vld3_pad, int, 16, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 32, 4);
+ PAD(buffer_vld3_pad, int, 32, 4);
+ VECT_ARRAY_INIT3(buffer_vld3, int, 64, 2);
+ PAD(buffer_vld3_pad, int, 64, 2);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 16);
+ PAD(buffer_vld3_pad, uint, 8, 16);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 8);
+ PAD(buffer_vld3_pad, uint, 16, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 4);
+ PAD(buffer_vld3_pad, uint, 32, 4);
+ VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 2);
+ PAD(buffer_vld3_pad, uint, 64, 2);
+ VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 16);
+ PAD(buffer_vld3_pad, poly, 8, 16);
+ VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8);
+ PAD(buffer_vld3_pad, poly, 16, 8);
+ VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4);
+ PAD(buffer_vld3_pad, float, 32, 4);
+
+ /* Input buffers for vld4, 1 of each size */
+ VECT_ARRAY_INIT4(buffer_vld4, int, 8, 8);
+ PAD(buffer_vld4_pad, int, 8, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 16, 4);
+ PAD(buffer_vld4_pad, int, 16, 4);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 32, 2);
+ PAD(buffer_vld4_pad, int, 32, 2);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 64, 1);
+ PAD(buffer_vld4_pad, int, 64, 1);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 8);
+ PAD(buffer_vld4_pad, uint, 8, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 4);
+ PAD(buffer_vld4_pad, uint, 16, 4);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 2);
+ PAD(buffer_vld4_pad, uint, 32, 2);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 1);
+ PAD(buffer_vld4_pad, uint, 64, 1);
+ VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 8);
+ PAD(buffer_vld4_pad, poly, 8, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4);
+ PAD(buffer_vld4_pad, poly, 16, 4);
+ VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2);
+ PAD(buffer_vld4_pad, float, 32, 2);
+
+ VECT_ARRAY_INIT4(buffer_vld4, int, 8, 16);
+ PAD(buffer_vld4_pad, int, 8, 16);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 16, 8);
+ PAD(buffer_vld4_pad, int, 16, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 32, 4);
+ PAD(buffer_vld4_pad, int, 32, 4);
+ VECT_ARRAY_INIT4(buffer_vld4, int, 64, 2);
+ PAD(buffer_vld4_pad, int, 64, 2);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 16);
+ PAD(buffer_vld4_pad, uint, 8, 16);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 8);
+ PAD(buffer_vld4_pad, uint, 16, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 4);
+ PAD(buffer_vld4_pad, uint, 32, 4);
+ VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 2);
+ PAD(buffer_vld4_pad, uint, 64, 2);
+ VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 16);
+ PAD(buffer_vld4_pad, poly, 8, 16);
+ VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8);
+ PAD(buffer_vld4_pad, poly, 16, 8);
+ VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4);
+ PAD(buffer_vld4_pad, float, 32, 4);
+
+ /* Check vld2_dup/vld2q_dup. */
+ clean_results ();
+#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
+ TEST_ALL_VLDX_DUP(2);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0");
+
+ TEST_ALL_EXTRA_CHUNKS(2, 1);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1");
+
+ /* Check vld3_dup/vld3q_dup. */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
+ TEST_ALL_VLDX_DUP(3);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0");
+
+ TEST_ALL_EXTRA_CHUNKS(3, 1);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1");
+
+ TEST_ALL_EXTRA_CHUNKS(3, 2);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2");
+
+ /* Check vld4_dup/vld4q_dup */
+ clean_results ();
+#undef TEST_MSG
+#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
+ TEST_ALL_VLDX_DUP(4);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0");
+
+ TEST_ALL_EXTRA_CHUNKS(4, 1);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1");
+
+ TEST_ALL_EXTRA_CHUNKS(4, 2);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2");
+
+ TEST_ALL_EXTRA_CHUNKS(4, 3);
+ CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3");
+}
+
+int main (void)
+{
+ exec_vldX_dup ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC).
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (18 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
` (16 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
__set_neon_cumulative_sat() modifies the contents on the QC flag, and
some intrinsics do so too: this patch adds the explicit dependency on
the asm statement, to avoid code reordering or removal.
When writing QC, the asm statement now has a fake input dependency,
which is the output of the intrinsic being tested. Modifying the
__set_neon_cumulative_sat macro is necessary, to be able to accept all
the possible input types.
Update the generic code in unary_sat_op.inc and binary_sat_op.inc
accordingly.
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(Set_Neon_Cumulative_Sat): Add parameter.
(__set_neon_cumulative_sat): Support new parameter.
* gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
(TEST_BINARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
argument.
* gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
(TEST_UNARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
argument.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 8ea1f26..6464c66 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -255,7 +255,11 @@ typedef union {
#endif /* __ORDER_BIG_ENDIAN__ */
#define Neon_Cumulative_Sat __read_neon_cumulative_sat()
-#define Set_Neon_Cumulative_Sat(x) __set_neon_cumulative_sat((x))
+/* We need a fake dependency to ensure correct ordering of asm
+ statements to preset the QC flag value, and Neon operators writing
+ to QC. */
+#define Set_Neon_Cumulative_Sat(x, depend) \
+ __set_neon_cumulative_sat((x), (depend))
#if defined(__aarch64__)
static volatile int __read_neon_cumulative_sat (void) {
@@ -263,13 +267,12 @@ static volatile int __read_neon_cumulative_sat (void) {
asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc));
return _afpscr_for_qc.b.QC;
}
-static void __set_neon_cumulative_sat (int x) {
- _ARM_FPSCR _afpscr_for_qc;
- asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc));
- _afpscr_for_qc.b.QC = x;
- asm volatile ("msr fpsr,%0" : : "r" (_afpscr_for_qc));
- return;
-}
+#define __set_neon_cumulative_sat(x, depend) { \
+ _ARM_FPSCR _afpscr_for_qc; \
+ asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc)); \
+ _afpscr_for_qc.b.QC = x; \
+ asm volatile ("msr fpsr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \
+ }
#else
static volatile int __read_neon_cumulative_sat (void) {
_ARM_FPSCR _afpscr_for_qc;
@@ -277,13 +280,12 @@ static volatile int __read_neon_cumulative_sat (void) {
return _afpscr_for_qc.b.QC;
}
-static void __set_neon_cumulative_sat (int x) {
- _ARM_FPSCR _afpscr_for_qc;
- asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc));
- _afpscr_for_qc.b.QC = x;
- asm volatile ("vmsr fpscr,%0" : : "r" (_afpscr_for_qc));
- return;
-}
+#define __set_neon_cumulative_sat(x, depend) { \
+ _ARM_FPSCR _afpscr_for_qc; \
+ asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc)); \
+ _afpscr_for_qc.b.QC = x; \
+ asm volatile ("vmsr fpscr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \
+ }
#endif
/* Declare expected cumulative saturation results, one for each
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
index 35d7701..c09a468 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
@@ -18,7 +18,7 @@ void FNNAME (INSN_NAME) (void)
/* vector_res = OP(vector1,vector2), then store the result. */
#define TEST_BINARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
- Set_Neon_Cumulative_Sat(0); \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
VECT_VAR(vector_res, T1, W, N) = \
INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
VECT_VAR(vector2, T1, W, N)); \
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
index 3f6d984..0da1426 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
@@ -17,7 +17,7 @@ void FNNAME (INSN_NAME) (void)
{
/* y=OP(x), then store the result. */
#define TEST_UNARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
- Set_Neon_Cumulative_Sat(0); \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
VECT_VAR(vector_res, T1, W, N) = \
INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (24 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 18:48 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
` (10 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vpaddl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
new file mode 100644
index 0000000..779cc77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
@@ -0,0 +1,129 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe5 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffe1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1e1, 0x1e5, 0x1e9, 0x1ed };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1ffe1, 0x1ffe5 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffe1 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
+ 0xfff1, 0xfff5, 0xfff9, 0xfffd };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe1, 0xffffffe5,
+ 0xffffffe9, 0xffffffed };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe1,
+ 0xffffffffffffffe5 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1e1, 0x1e5, 0x1e9, 0x1ed,
+ 0x1f1, 0x1f5, 0x1f9, 0x1fd };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1ffe1, 0x1ffe5, 0x1ffe9, 0x1ffed };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x1ffffffe1, 0x1ffffffe5 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#define INSN_NAME vpaddl
+#define TEST_MSG "VPADDL/VPADDLQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
+ TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, int, 8, 16);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, uint, 8, 16);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 1);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 1);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 8, 16);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 8, 16);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
+ TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
+ TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
+ TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
+ TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
+ TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
+ TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
+ TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
+ TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vpaddl ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (22 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
` (12 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
new file mode 100644
index 0000000..fd885dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
@@ -0,0 +1,59 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = vqdmlxl_n(vector, vector3, val),
+ then store the result. */
+#define TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector3, T1, W2, N), \
+ V); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMLXL_N(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+
+ VDUP(vector3, , int, s, 16, 4, 0x55);
+ VDUP(vector3, , int, s, 32, 2, 0x55);
+
+ /* Choose val arbitrarily. */
+ TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x22, expected_cumulative_sat, "");
+ TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x33, expected_cumulative_sat, "");
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+
+#define TEST_MSG2 "(check mul cumulative saturation)"
+ VDUP(vector3, , int, s, 16, 4, 0x8000);
+ VDUP(vector3, , int, s, 32, 2, 0x80000000);
+
+ TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c
new file mode 100644
index 0000000..b84bca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c
@@ -0,0 +1,27 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlal_n
+#define TEST_MSG "VQDMLAL_N"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x1684, 0x1685, 0x1686, 0x1687 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x21ce, 0x21cf };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0,
+ 0x7ffffff1, 0x7ffffff2 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef,
+ 0x7ffffffffffffff0 };
+
+#include "vqdmlXl_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c
new file mode 100644
index 0000000..ff8d9d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c
@@ -0,0 +1,29 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vqdmlsl_n
+#define TEST_MSG "VQDMLSL_N"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffe95c, 0xffffe95d,
+ 0xffffe95e, 0xffffe95f };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffde12,
+ 0xffffffffffffde13 };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000,
+ 0x8000000000000000 };
+
+#include "vqdmlXl_n.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (15 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
@ 2015-01-13 15:19 ` Christophe Lyon
2015-01-16 14:31 ` Tejas Belagod
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
` (19 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:19 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
new file mode 100644
index 0000000..168cf5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
@@ -0,0 +1,129 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xf0, 0xaa };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xf0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+ 0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+ 0xfffffff0, 0xaaaaaaaa };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
+ 0xfffffffffffffff0 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xf0, 0xaa, 0xaa, 0xaa };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+ 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+ 0xfffffff0, 0xaaaaaaaa };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
+ 0xaaaaaaaaaaaaaaaa };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xf0, 0xaa, 0xaa, 0xaa };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
+ 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
+ 0xc1800000, 0xaaaaaaaa };
+
+#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
+void exec_vld1_lane (void)
+{
+ /* Fill vector_src with 0xAA, then load 1 lane. */
+#define TEST_VLD1_LANE(Q, T1, T2, W, N, L) \
+ memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N); \
+ VECT_VAR(vector_src, T1, W, N) = \
+ vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N)); \
+ VECT_VAR(vector, T1, W, N) = \
+ vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N), \
+ VECT_VAR(vector_src, T1, W, N), L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W, N))
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector_src);
+
+ ARRAY(buffer_src, int, 8, 8);
+ ARRAY(buffer_src, int, 16, 4);
+ ARRAY(buffer_src, int, 32, 2);
+ ARRAY(buffer_src, int, 64, 1);
+ ARRAY(buffer_src, uint, 8, 8);
+ ARRAY(buffer_src, uint, 16, 4);
+ ARRAY(buffer_src, uint, 32, 2);
+ ARRAY(buffer_src, uint, 64, 1);
+ ARRAY(buffer_src, poly, 8, 8);
+ ARRAY(buffer_src, poly, 16, 4);
+ ARRAY(buffer_src, float, 32, 2);
+
+ ARRAY(buffer_src, int, 8, 16);
+ ARRAY(buffer_src, int, 16, 8);
+ ARRAY(buffer_src, int, 32, 4);
+ ARRAY(buffer_src, int, 64, 2);
+ ARRAY(buffer_src, uint, 8, 16);
+ ARRAY(buffer_src, uint, 16, 8);
+ ARRAY(buffer_src, uint, 32, 4);
+ ARRAY(buffer_src, uint, 64, 2);
+ ARRAY(buffer_src, poly, 8, 16);
+ ARRAY(buffer_src, poly, 16, 8);
+ ARRAY(buffer_src, float, 32, 4);
+
+ clean_results ();
+
+ /* Choose lane arbitrarily. */
+ TEST_VLD1_LANE(, int, s, 8, 8, 6);
+ TEST_VLD1_LANE(, int, s, 16, 4, 3);
+ TEST_VLD1_LANE(, int, s, 32, 2, 1);
+ TEST_VLD1_LANE(, int, s, 64, 1, 0);
+ TEST_VLD1_LANE(, uint, u, 8, 8, 7);
+ TEST_VLD1_LANE(, uint, u, 16, 4, 3);
+ TEST_VLD1_LANE(, uint, u, 32, 2, 1);
+ TEST_VLD1_LANE(, uint, u, 64, 1, 0);
+ TEST_VLD1_LANE(, poly, p, 8, 8, 7);
+ TEST_VLD1_LANE(, poly, p, 16, 4, 3);
+ TEST_VLD1_LANE(, float, f, 32, 2, 1);
+
+ TEST_VLD1_LANE(q, int, s, 8, 16, 15);
+ TEST_VLD1_LANE(q, int, s, 16, 8, 5);
+ TEST_VLD1_LANE(q, int, s, 32, 4, 2);
+ TEST_VLD1_LANE(q, int, s, 64, 2, 1);
+ TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
+ TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
+ TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
+ TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
+ TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
+ TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
+ TEST_VLD1_LANE(q, float, f, 32, 4, 2);
+
+#ifndef __CC_ARM
+ /* Check runtime assertions. With RVCT, the check is performed at
+ compile-time */
+ // TEST_VLD1_LANE(, int, s, 64, 1, 1);
+#endif
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ exec_vld1_lane ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (30 preceding siblings ...)
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
@ 2015-01-13 15:20 ` Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
` (4 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:20 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
new file mode 100644
index 0000000..1e6bab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
@@ -0,0 +1,89 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* vector_res = OP(vector, vector3, vector4),
+ then store the result. */
+#define TEST_VMLXL1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector3, T1, W2, N), \
+ VECT_VAR(vector4, T1, W2, N)); \
+ vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLXL(INSN, T1, T2, W, W2, N) \
+ TEST_VMLXL1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector3, int, 8, 8);
+ DECL_VARIABLE(vector4, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector4, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector4, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector3, uint, 8, 8);
+ DECL_VARIABLE(vector4, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector3, uint, 16, 4);
+ DECL_VARIABLE(vector4, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+
+ DECL_VARIABLE(vector, uint, 64, 2);
+ DECL_VARIABLE(vector3, uint, 32, 2);
+ DECL_VARIABLE(vector4, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ VDUP(vector3, , int, s, 8, 8, 0x55);
+ VDUP(vector4, , int, s, 8, 8, 0xBB);
+ VDUP(vector3, , int, s, 16, 4, 0x55);
+ VDUP(vector4, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0x55);
+ VDUP(vector4, , int, s, 32, 2, 0xBB);
+ VDUP(vector3, , uint, u, 8, 8, 0x55);
+ VDUP(vector4, , uint, u, 8, 8, 0xBB);
+ VDUP(vector3, , uint, u, 16, 4, 0x55);
+ VDUP(vector4, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0x55);
+ VDUP(vector4, , uint, u, 32, 2, 0xBB);
+
+ TEST_VMLXL(INSN_NAME, int, s, 16, 8, 8);
+ TEST_VMLXL(INSN_NAME, int, s, 32, 16, 4);
+ TEST_VMLXL(INSN_NAME, int, s, 64, 32, 2);
+ TEST_VMLXL(INSN_NAME, uint, u, 16, 8, 8);
+ TEST_VMLXL(INSN_NAME, uint, u, 32, 16, 4);
+ TEST_VMLXL(INSN_NAME, uint, u, 64, 32, 2);
+
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
new file mode 100644
index 0000000..c147f31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
@@ -0,0 +1,18 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlal
+#define TEST_MSG "VMLAL"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe907, 0xe908, 0xe909, 0xe90a,
+ 0xe90b, 0xe90c, 0xe90d, 0xe90e };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
+
+#include "vmlXl.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
new file mode 100644
index 0000000..6c984ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
@@ -0,0 +1,22 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmlsl
+#define TEST_MSG "VMLSL"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x16d9, 0x16da, 0x16db, 0x16dc,
+ 0x16dd, 0x16de, 0x16df, 0x16e0 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
+ 0xffffffffffffc1da };
+
+#include "vmlXl.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (32 preceding siblings ...)
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
@ 2015-01-13 15:20 ` Christophe Lyon
2015-01-16 17:54 ` Tejas Belagod
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
` (2 subsequent siblings)
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:20 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
new file mode 100644
index 0000000..7ac2ed4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
@@ -0,0 +1,67 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADD1(INSN, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VPADD(INSN, T1, T2, W, N) \
+ TEST_VPADD1(INSN, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADD(INSN_NAME, int, s, 8, 8);
+ TEST_VPADD(INSN_NAME, int, s, 16, 4);
+ TEST_VPADD(INSN_NAME, int, s, 32, 2);
+ TEST_VPADD(INSN_NAME, uint, u, 8, 8);
+ TEST_VPADD(INSN_NAME, uint, u, 16, 4);
+ TEST_VPADD(INSN_NAME, uint, u, 32, 2);
+ TEST_VPADD(INSN_NAME, float, f, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
new file mode 100644
index 0000000..5ddfd3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
@@ -0,0 +1,19 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vpadd
+#define TEST_MSG "VPADD"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
new file mode 100644
index 0000000..f27a9a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmax
+#define TEST_MSG "VPMAX"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
new file mode 100644
index 0000000..a7cb696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmin
+#define TEST_MSG "VPMIN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+
+#include "vpXXX.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (31 preceding siblings ...)
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
@ 2015-01-13 15:20 ` Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
` (3 subsequent siblings)
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:20 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
vXXXl.inc.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc
new file mode 100644
index 0000000..bd4c8fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc
@@ -0,0 +1,70 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=vaddl(x1,x2), then store the result. */
+#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
+
+#define TEST_VADDL(INSN, T1, T2, W, W2, N) \
+ TEST_VADDL1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+
+ DECL_VARIABLE(vector2, int, 8, 8);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 8, 8);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+
+ /* Choose init value arbitrarily. */
+ VDUP(vector2, , int, s, 8, 8, -13);
+ VDUP(vector2, , int, s, 16, 4, -14);
+ VDUP(vector2, , int, s, 32, 2, -16);
+ VDUP(vector2, , uint, u, 8, 8, 0xf3);
+ VDUP(vector2, , uint, u, 16, 4, 0xfff1);
+ VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
+
+ /* Execute the tests. */
+ TEST_VADDL(INSN_NAME, int, s, 8, 16, 8);
+ TEST_VADDL(INSN_NAME, int, s, 16, 32, 4);
+ TEST_VADDL(INSN_NAME, int, s, 32, 64, 2);
+ TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8);
+ TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4);
+ TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2);
+
+ CHECK_RESULTS (TEST_MSG, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
index 030785d..020d9f8 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
@@ -2,6 +2,9 @@
#include "arm-neon-ref.h"
#include "compute-ref-data.h"
+#define INSN_NAME vaddl
+#define TEST_MSG "VADDL"
+
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
0x33, 0x33, 0x33, 0x33 };
@@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
0x33333333, 0x33333333 };
-#define INSN_NAME vaddl
-#define TEST_MSG "VADDL"
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* Basic test: y=vaddl(x1,x2), then store the result. */
-#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \
- VECT_VAR(vector_res, T1, W2, N) = \
- INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
-
-#define TEST_VADDL(INSN, T1, T2, W, W2, N) \
- TEST_VADDL1(INSN, T1, T2, W, W2, N)
-
- DECL_VARIABLE(vector, int, 8, 8);
- DECL_VARIABLE(vector, int, 16, 4);
- DECL_VARIABLE(vector, int, 32, 2);
- DECL_VARIABLE(vector, uint, 8, 8);
- DECL_VARIABLE(vector, uint, 16, 4);
- DECL_VARIABLE(vector, uint, 32, 2);
-
- DECL_VARIABLE(vector2, int, 8, 8);
- DECL_VARIABLE(vector2, int, 16, 4);
- DECL_VARIABLE(vector2, int, 32, 2);
- DECL_VARIABLE(vector2, uint, 8, 8);
- DECL_VARIABLE(vector2, uint, 16, 4);
- DECL_VARIABLE(vector2, uint, 32, 2);
-
- DECL_VARIABLE(vector_res, int, 16, 8);
- DECL_VARIABLE(vector_res, int, 32, 4);
- DECL_VARIABLE(vector_res, int, 64, 2);
- DECL_VARIABLE(vector_res, uint, 16, 8);
- DECL_VARIABLE(vector_res, uint, 32, 4);
- DECL_VARIABLE(vector_res, uint, 64, 2);
-
- clean_results ();
-
- /* Initialize input "vector" from "buffer". */
- VLOAD(vector, buffer, , int, s, 8, 8);
- VLOAD(vector, buffer, , int, s, 16, 4);
- VLOAD(vector, buffer, , int, s, 32, 2);
- VLOAD(vector, buffer, , uint, u, 8, 8);
- VLOAD(vector, buffer, , uint, u, 16, 4);
- VLOAD(vector, buffer, , uint, u, 32, 2);
-
- /* Choose init value arbitrarily. */
- VDUP(vector2, , int, s, 8, 8, -13);
- VDUP(vector2, , int, s, 16, 4, -14);
- VDUP(vector2, , int, s, 32, 2, -16);
- VDUP(vector2, , uint, u, 8, 8, 0xf3);
- VDUP(vector2, , uint, u, 16, 4, 0xfff1);
- VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
-
- /* Execute the tests. */
- TEST_VADDL(INSN_NAME, int, s, 8, 16, 8);
- TEST_VADDL(INSN_NAME, int, s, 16, 32, 4);
- TEST_VADDL(INSN_NAME, int, s, 32, 64, 2);
- TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8);
- TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4);
- TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2);
-
- CHECK_RESULTS (TEST_MSG, "");
-}
-
-int main (void)
-{
- FNNAME (INSN_NAME) ();
- return 0;
-}
+#include "vXXXl.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c
new file mode 100644
index 0000000..b765b2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c
@@ -0,0 +1,48 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vsubl
+#define TEST_MSG "VSUBL"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
+ 0x1, 0x2, 0x3, 0x4 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
+ 0x1, 0x2, 0x3, 0x4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x1, 0x2 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
+ 0x3333, 0x3333, 0x3333, 0x3333 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
+ 0x33333333, 0x33333333 };
+
+#include "vXXXl.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (33 preceding siblings ...)
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
@ 2015-01-13 15:21 ` Christophe Lyon
2015-01-19 16:54 ` Marcus Shawcroft
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
36 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:21 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c
new file mode 100644
index 0000000..12f2a6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c
@@ -0,0 +1,94 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x8000, 0x8000, 0x8000, 0x8000 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0x4000, 0x4000 };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffff,
+ 0x7fffffffffffffff };
+
+#define INSN_NAME vqdmull
+#define TEST_MSG "VQDMULL_LANE"
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ int i;
+
+ /* vector_res = vqdmull_lane(vector,vector2,lane), then store the result. */
+#define TEST_VQDMULL_LANE2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ L); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), \
+ VECT_VAR(vector_res, T1, W2, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULL_LANE1(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL_LANE2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULL_LANE(T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL_LANE1(INSN_NAME, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ /* Initialize vector. */
+ VDUP(vector, , int, s, 16, 4, 0x1000);
+ VDUP(vector, , int, s, 32, 2, 0x1000);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x4);
+ VDUP(vector2, , int, s, 32, 2, 0x2);
+
+ /* Choose lane arbitrarily. */
+ TEST_VQDMULL_LANE(int, s, 16, 32, 4, 2, expected_cumulative_sat, "");
+ TEST_VQDMULL_LANE(int, s, 32, 64, 2, 1, expected_cumulative_sat, "");
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector2, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+ VDUP(vector2, , int, s, 32, 2, 0x80000000);
+
+#define TEST_MSG2 "with saturation"
+ TEST_VQDMULL_LANE(int, s, 16, 32, 4, 2, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULL_LANE(int, s, 32, 64, 2, 1, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (34 preceding siblings ...)
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
@ 2015-01-13 15:22 ` Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
2015-01-19 17:16 ` Marcus Shawcroft
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
36 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-13 15:22 UTC (permalink / raw)
To: gcc-patches
* gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
new file mode 100644
index 0000000..9e73009
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
@@ -0,0 +1,92 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected values of cumulative_saturation flag. */
+int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
+int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x44000, 0x44000,
+ 0x44000, 0x44000 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xaa000, 0xaa000 };
+
+/* Expected values of cumulative_saturation flag when saturation
+ occurs. */
+int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
+int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
+
+/* Expected results when saturation occurs. */
+VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff };
+VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffff,
+ 0x7fffffffffffffff };
+
+#define INSN_NAME vqdmull
+#define TEST_MSG "VQDMULL_N"
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ int i;
+
+ /* vector_res = vqdmull_n(vector,val), then store the result. */
+#define TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
+ VECT_VAR(vector_res, T1, W2, N) = \
+ INSN##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ L); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), \
+ VECT_VAR(vector_res, T1, W2, N)); \
+ CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ /* Two auxliary macros are necessary to expand INSN. */
+#define TEST_VQDMULL_N1(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+#define TEST_VQDMULL_N(T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
+ TEST_VQDMULL_N1(INSN_NAME, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+
+ clean_results ();
+
+ /* Initialize vector. */
+ VDUP(vector, , int, s, 16, 4, 0x1000);
+ VDUP(vector, , int, s, 32, 2, 0x1000);
+
+ /* Initialize vector2. */
+ VDUP(vector2, , int, s, 16, 4, 0x4);
+ VDUP(vector2, , int, s, 32, 2, 0x2);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VQDMULL_N(int, s, 16, 32, 4, 0x22, expected_cumulative_sat, "");
+ TEST_VQDMULL_N(int, s, 32, 64, 2, 0x55, expected_cumulative_sat, "");
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+
+ VDUP(vector, , int, s, 16, 4, 0x8000);
+ VDUP(vector, , int, s, 32, 2, 0x80000000);
+
+#define TEST_MSG2 "with saturation"
+ TEST_VQDMULL_N(int, s, 16, 32, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2);
+ TEST_VQDMULL_N(int, s, 32, 64, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
+
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC).
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
@ 2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 13:43 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:17, Christophe Lyon wrote:
> __set_neon_cumulative_sat() modifies the contents on the QC flag, and
> some intrinsics do so too: this patch adds the explicit dependency on
> the asm statement, to avoid code reordering or removal.
>
> When writing QC, the asm statement now has a fake input dependency,
> which is the output of the intrinsic being tested. Modifying the
> __set_neon_cumulative_sat macro is necessary, to be able to accept all
> the possible input types.
>
> Update the generic code in unary_sat_op.inc and binary_sat_op.inc
> accordingly.
>
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> (Set_Neon_Cumulative_Sat): Add parameter.
> (__set_neon_cumulative_sat): Support new parameter.
> * gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
> (TEST_BINARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
> argument.
> * gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
> (TEST_UNARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
> argument.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> index 8ea1f26..6464c66 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> @@ -255,7 +255,11 @@ typedef union {
> #endif /* __ORDER_BIG_ENDIAN__ */
>
> #define Neon_Cumulative_Sat __read_neon_cumulative_sat()
> -#define Set_Neon_Cumulative_Sat(x) __set_neon_cumulative_sat((x))
> +/* We need a fake dependency to ensure correct ordering of asm
> + statements to preset the QC flag value, and Neon operators writing
> + to QC. */
> +#define Set_Neon_Cumulative_Sat(x, depend) \
> + __set_neon_cumulative_sat((x), (depend))
>
> #if defined(__aarch64__)
> static volatile int __read_neon_cumulative_sat (void) {
> @@ -263,13 +267,12 @@ static volatile int __read_neon_cumulative_sat (void) {
> asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc));
> return _afpscr_for_qc.b.QC;
> }
> -static void __set_neon_cumulative_sat (int x) {
> - _ARM_FPSCR _afpscr_for_qc;
> - asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc));
> - _afpscr_for_qc.b.QC = x;
> - asm volatile ("msr fpsr,%0" : : "r" (_afpscr_for_qc));
> - return;
> -}
> +#define __set_neon_cumulative_sat(x, depend) { \
> + _ARM_FPSCR _afpscr_for_qc; \
> + asm volatile ("mrs %0,fpsr" : "=r" (_afpscr_for_qc)); \
> + _afpscr_for_qc.b.QC = x; \
> + asm volatile ("msr fpsr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \
> + }
> #else
> static volatile int __read_neon_cumulative_sat (void) {
> _ARM_FPSCR _afpscr_for_qc;
> @@ -277,13 +280,12 @@ static volatile int __read_neon_cumulative_sat (void) {
> return _afpscr_for_qc.b.QC;
> }
>
> -static void __set_neon_cumulative_sat (int x) {
> - _ARM_FPSCR _afpscr_for_qc;
> - asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc));
> - _afpscr_for_qc.b.QC = x;
> - asm volatile ("vmsr fpscr,%0" : : "r" (_afpscr_for_qc));
> - return;
> -}
> +#define __set_neon_cumulative_sat(x, depend) { \
> + _ARM_FPSCR _afpscr_for_qc; \
> + asm volatile ("vmrs %0,fpscr" : "=r" (_afpscr_for_qc)); \
> + _afpscr_for_qc.b.QC = x; \
> + asm volatile ("vmsr fpscr,%1" : "=X" (depend) : "r" (_afpscr_for_qc)); \
> + }
> #endif
>
> /* Declare expected cumulative saturation results, one for each
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
> index 35d7701..c09a468 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
> @@ -18,7 +18,7 @@ void FNNAME (INSN_NAME) (void)
> /* vector_res = OP(vector1,vector2), then store the result. */
>
> #define TEST_BINARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
> - Set_Neon_Cumulative_Sat(0); \
> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
> VECT_VAR(vector_res, T1, W, N) = \
> INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
> VECT_VAR(vector2, T1, W, N)); \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
> index 3f6d984..0da1426 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
> @@ -17,7 +17,7 @@ void FNNAME (INSN_NAME) (void)
> {
> /* y=OP(x), then store the result. */
> #define TEST_UNARY_SAT_OP1(INSN, Q, T1, T2, W, N, EXPECTED_CUMULATIVE_SAT, CMT) \
> - Set_Neon_Cumulative_Sat(0); \
> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
> VECT_VAR(vector_res, T1, W, N) = \
> INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
> vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
>
Looks OK to me(but I can't approve it).
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
@ 2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 13:46 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
> Add trace.
> (CHECK_FP): Likewise.
> (CHECK_CUMULATIVE_SAT): Likewise.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> index 6464c66..2730a66 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> @@ -79,6 +79,7 @@ extern size_t strlen(const char *);
> abort(); \
> } \
> } \
> + fprintf(stderr, "CHECKED %s\n", MSG); \
> }
>
> /* Floating-point variant. */
> @@ -107,6 +108,7 @@ extern size_t strlen(const char *);
> abort(); \
> } \
> } \
> + fprintf(stderr, "CHECKED %s\n", MSG); \
> }
>
> /* Clean buffer with a non-zero pattern to help diagnose buffer
> @@ -323,6 +325,7 @@ extern int VECT_VAR(expected_cumulative_sat, uint, 64, 2);
> strlen(COMMENT) > 0 ? " " COMMENT : ""); \
> abort(); \
> } \
> + fprintf(stderr, "CHECKED CUMULATIVE SAT %s\n", MSG); \
> }
>
> #define CHECK_CUMULATIVE_SAT_NAMED(test_name,EXPECTED,comment) \
>
Looks OK to me(but I can't approve it).
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
@ 2015-01-16 14:08 ` Tejas Belagod
2015-01-16 16:23 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 14:08 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +#ifndef NO_FLOAT_VARIANT
> + VLOAD(vector, buffer, , float, f, 32, 2);
> + VLOAD(vector, buffer, q, float, f, 32, 4);
> +#endif
>
....
> +#ifndef NO_FLOAT_VARIANT
> + VDUP(vector2, , float, f, 32, 2, -15.5f);
> + VDUP(vector2, q, float, f, 32, 4, -14.5f);
> +#endif
> +
> +#ifndef NO_FLOAT_VARIANT
> +#define FLOAT_VARIANT(MACRO, VAR) \
> + MACRO(VAR, , float, f, 32, 2); \
> + MACRO(VAR, q, float, f, 32, 4)
> +#else
> +#define FLOAT_VARIANT(MACRO, VAR)
> +#endif
Double negative! :-) Probably easier on the reader to avoid it, but your
call.
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
> new file mode 100644
> index 0000000..2591b16
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
> @@ -0,0 +1,64 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmax
> +#define TEST_MSG "VMAX/VMAXQ"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
> + 0xf4, 0xf5, 0xf6, 0xf7,
> + 0xf8, 0xf9, 0xfa, 0xfb,
> + 0xfc, 0xfd, 0xfe, 0xff };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
> + 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf9, 0xf9, 0xf9, 0xf9,
> + 0xf9, 0xf9, 0xf9, 0xf9,
> + 0xf9, 0xf9, 0xfa, 0xfb,
> + 0xfc, 0xfd, 0xfe, 0xff };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
> + 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
> + 0xc1600000, 0xc1500000 };
> +
> +/* Expected results with special FP values. */
> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
> + 0x7fc00000, 0x7fc00000 };
> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
> + 0x7fc00000, 0x7fc00000 };
> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
> + 0x7f800000, 0x7f800000 };
> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
> + 0x3f800000, 0x3f800000 };
> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
> +
> +#include "binary_op_no64.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
> new file mode 100644
> index 0000000..2b5e87c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
> @@ -0,0 +1,66 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmin
> +#define TEST_MSG "VMIN/VMINQ"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf3, 0xf3, 0xf3, 0xf3 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf3, 0xf3, 0xf3, 0xf3 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf4, 0xf4, 0xf4, 0xf4,
> + 0xf4, 0xf4, 0xf4, 0xf4,
> + 0xf4, 0xf4, 0xf4, 0xf4 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
> + 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
> + 0xfffffff1, 0xfffffff1 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7,
> + 0xf8, 0xf9, 0xf9, 0xf9,
> + 0xf9, 0xf9, 0xf9, 0xf9 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
> + 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
> + 0xfffffff1, 0xfffffff1 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
> + 0xc1680000, 0xc1680000 };
> +/* Expected results with special FP values. */
> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
> + 0x7fc00000, 0x7fc00000 };
> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
> + 0x7fc00000, 0x7fc00000 };
> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
> + 0x3f800000, 0x3f800000 };
> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0xff800000, 0xff800000,
> + 0xff800000, 0xff800000 };
> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x80000000, 0x80000000,
> + 0x80000000, 0x80000000 };
> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x80000000, 0x80000000,
> + 0x80000000, 0x80000000 };
> +
> +#include "binary_op_no64.inc"
vmax and vmin do have v<maxmin>_f64 and v<maxmin>q_f64 variants.
Otherwise, they look good to me(but I can't approve it).
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
@ 2015-01-16 14:31 ` Tejas Belagod
2015-01-16 16:31 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 14:31 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
> new file mode 100644
> index 0000000..168cf5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
> @@ -0,0 +1,129 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xf0, 0xaa };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xf0 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> + 0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> + 0xfffffff0, 0xaaaaaaaa };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
> + 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xf0, 0xaa, 0xaa, 0xaa };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> + 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> + 0xfffffff0, 0xaaaaaaaa };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
> + 0xaaaaaaaaaaaaaaaa };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xf0, 0xaa, 0xaa, 0xaa };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
> + 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
> + 0xc1800000, 0xaaaaaaaa };
> +
> +#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
> +void exec_vld1_lane (void)
> +{
> + /* Fill vector_src with 0xAA, then load 1 lane. */
> +#define TEST_VLD1_LANE(Q, T1, T2, W, N, L) \
> + memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N); \
> + VECT_VAR(vector_src, T1, W, N) = \
> + vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N)); \
> + VECT_VAR(vector, T1, W, N) = \
> + vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N), \
> + VECT_VAR(vector_src, T1, W, N), L); \
> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W, N))
> +
> + DECL_VARIABLE_ALL_VARIANTS(vector);
> + DECL_VARIABLE_ALL_VARIANTS(vector_src);
> +
> + ARRAY(buffer_src, int, 8, 8);
> + ARRAY(buffer_src, int, 16, 4);
> + ARRAY(buffer_src, int, 32, 2);
> + ARRAY(buffer_src, int, 64, 1);
> + ARRAY(buffer_src, uint, 8, 8);
> + ARRAY(buffer_src, uint, 16, 4);
> + ARRAY(buffer_src, uint, 32, 2);
> + ARRAY(buffer_src, uint, 64, 1);
> + ARRAY(buffer_src, poly, 8, 8);
> + ARRAY(buffer_src, poly, 16, 4);
> + ARRAY(buffer_src, float, 32, 2);
> +
> + ARRAY(buffer_src, int, 8, 16);
> + ARRAY(buffer_src, int, 16, 8);
> + ARRAY(buffer_src, int, 32, 4);
> + ARRAY(buffer_src, int, 64, 2);
> + ARRAY(buffer_src, uint, 8, 16);
> + ARRAY(buffer_src, uint, 16, 8);
> + ARRAY(buffer_src, uint, 32, 4);
> + ARRAY(buffer_src, uint, 64, 2);
> + ARRAY(buffer_src, poly, 8, 16);
> + ARRAY(buffer_src, poly, 16, 8);
> + ARRAY(buffer_src, float, 32, 4);
> +
> + clean_results ();
> +
> + /* Choose lane arbitrarily. */
> + TEST_VLD1_LANE(, int, s, 8, 8, 6);
> + TEST_VLD1_LANE(, int, s, 16, 4, 3);
> + TEST_VLD1_LANE(, int, s, 32, 2, 1);
> + TEST_VLD1_LANE(, int, s, 64, 1, 0);
> + TEST_VLD1_LANE(, uint, u, 8, 8, 7);
> + TEST_VLD1_LANE(, uint, u, 16, 4, 3);
> + TEST_VLD1_LANE(, uint, u, 32, 2, 1);
> + TEST_VLD1_LANE(, uint, u, 64, 1, 0);
> + TEST_VLD1_LANE(, poly, p, 8, 8, 7);
> + TEST_VLD1_LANE(, poly, p, 16, 4, 3);
> + TEST_VLD1_LANE(, float, f, 32, 2, 1);
> +
> + TEST_VLD1_LANE(q, int, s, 8, 16, 15);
> + TEST_VLD1_LANE(q, int, s, 16, 8, 5);
> + TEST_VLD1_LANE(q, int, s, 32, 4, 2);
> + TEST_VLD1_LANE(q, int, s, 64, 2, 1);
> + TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
> + TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
> + TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
> + TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
> + TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
> + TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
> + TEST_VLD1_LANE(q, float, f, 32, 4, 2);
> +
Hmm.. again, I don't see vld1<q>_lane_f64?
> +#ifndef __CC_ARM
> + /* Check runtime assertions. With RVCT, the check is performed at
> + compile-time */
> + // TEST_VLD1_LANE(, int, s, 64, 1, 1);
> +#endif
> +
Does this belong in this patch?
Otherwise, it looks good to me(I cannot approve though).
Thanks,
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
@ 2015-01-16 15:35 ` Tejas Belagod
2015-01-16 18:17 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 15:35 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
> new file mode 100644
> index 0000000..53cd8f3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
> @@ -0,0 +1,671 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +
> +/* vld2_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld2_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
> + 0xf0, 0xf1, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,int,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld3_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld3_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,uint,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
> + 0xf1, 0xf2, 0xf0, 0xf1 };
> +VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff0 };
> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,int,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,int,32,2) [] = { 0xfffffff2, 0xfffffff0 };
> +VECT_VAR_DECL(expected_vld3_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld3_1,uint,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,uint,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff0 };
> +VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
> + 0xf0, 0xf1, 0xf2, 0xf0 };
> +VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2,
> + 0xfff0, 0xfff1 };
> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 };
> +VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld3_dup/chunk 2. */
> +VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,int,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,int,32,2) [] = { 0xfffffff1, 0xfffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,int,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,uint,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
> + 0xf2, 0xf0, 0xf1, 0xf2 };
> +VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0,
> + 0xfff1, 0xfff2 };
> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 };
> +VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 0. */
> +VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,int,16,4) [] = { 0xfff0, 0xfff1,
> + 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_0,int,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld4_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 };
> +VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 1. */
> +VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_1,int,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld4_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
> +VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk 2. */
> +VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_2,int,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld4_2,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 };
> +VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +/* vld4_dup/chunk3. */
> +VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,int,64,1) [] = { 0xfffffffffffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 };
> +VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf0, 0xf1, 0xf2, 0xf3 };
> +VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 };
> +VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333, 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +void exec_vldX_dup (void)
> +{
> + /* In this case, input variables are arrays of vectors. */
> +#define DECL_VLDX_DUP(T1, W, N, X) \
> + VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
> + VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
> +
> + /* We need to use a temporary result buffer (result_bis), because
> + the one used for other tests is not large enough. A subset of the
> + result data is moved from result_bis to result, and it is this
> + subset which is used to check the actual behaviour. The next
> + macro enables to move another chunk of data from result_bis to
> + result. */
> +#define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \
> + VECT_ARRAY_VAR(vector, T1, W, N, X) = \
> + vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \
> + \
> + vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
> + VECT_ARRAY_VAR(vector, T1, W, N, X)); \
> + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> +
> + /* Overwrite "result" with the contents of "result_bis"[Y]. */
> +#define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \
> + memcpy(VECT_VAR(result, T1, W, N), \
> + &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> +#define DECL_ALL_VLDX_DUP(X) \
> + DECL_VLDX_DUP(int, 8, 8, X); \
> + DECL_VLDX_DUP(int, 16, 4, X); \
> + DECL_VLDX_DUP(int, 32, 2, X); \
> + DECL_VLDX_DUP(int, 64, 1, X); \
> + DECL_VLDX_DUP(uint, 8, 8, X); \
> + DECL_VLDX_DUP(uint, 16, 4, X); \
> + DECL_VLDX_DUP(uint, 32, 2, X); \
> + DECL_VLDX_DUP(uint, 64, 1, X); \
> + DECL_VLDX_DUP(poly, 8, 8, X); \
> + DECL_VLDX_DUP(poly, 16, 4, X); \
> + DECL_VLDX_DUP(float, 32, 2, X)
> +
> +#define TEST_ALL_VLDX_DUP(X) \
> + TEST_VLDX_DUP(, int, s, 8, 8, X); \
> + TEST_VLDX_DUP(, int, s, 16, 4, X); \
> + TEST_VLDX_DUP(, int, s, 32, 2, X); \
> + TEST_VLDX_DUP(, int, s, 64, 1, X); \
> + TEST_VLDX_DUP(, uint, u, 8, 8, X); \
> + TEST_VLDX_DUP(, uint, u, 16, 4, X); \
> + TEST_VLDX_DUP(, uint, u, 32, 2, X); \
> + TEST_VLDX_DUP(, uint, u, 64, 1, X); \
> + TEST_VLDX_DUP(, poly, p, 8, 8, X); \
> + TEST_VLDX_DUP(, poly, p, 16, 4, X); \
> + TEST_VLDX_DUP(, float, f, 32, 2, X)
> +
> +#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
> + TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
> + TEST_EXTRA_CHUNK(int, 64, 1, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
> + TEST_EXTRA_CHUNK(uint, 64, 1, X, Y); \
> + TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
> + TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
> + TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
> +
> +
> + DECL_ALL_VLDX_DUP(2);
> + DECL_ALL_VLDX_DUP(3);
> + DECL_ALL_VLDX_DUP(4);
> +
> + /* Special input buffers of suitable size are needed for vld2/vld3/vld4. */
> + /* Input buffers for vld2, 1 of each size */
> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 8);
> + PAD(buffer_vld2_pad, int, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 4);
> + PAD(buffer_vld2_pad, int, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 2);
> + PAD(buffer_vld2_pad, int, 32, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 1);
> + PAD(buffer_vld2_pad, int, 64, 1);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 8);
> + PAD(buffer_vld2_pad, uint, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 4);
> + PAD(buffer_vld2_pad, uint, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 2);
> + PAD(buffer_vld2_pad, uint, 32, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 1);
> + PAD(buffer_vld2_pad, uint, 64, 1);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 8);
> + PAD(buffer_vld2_pad, poly, 8, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4);
> + PAD(buffer_vld2_pad, poly, 16, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2);
> + PAD(buffer_vld2_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 16);
> + PAD(buffer_vld2_pad, int, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 8);
> + PAD(buffer_vld2_pad, int, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 4);
> + PAD(buffer_vld2_pad, int, 32, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 2);
> + PAD(buffer_vld2_pad, int, 64, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 16);
> + PAD(buffer_vld2_pad, uint, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 8);
> + PAD(buffer_vld2_pad, uint, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 4);
> + PAD(buffer_vld2_pad, uint, 32, 4);
> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 2);
> + PAD(buffer_vld2_pad, uint, 64, 2);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 16);
> + PAD(buffer_vld2_pad, poly, 8, 16);
> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8);
> + PAD(buffer_vld2_pad, poly, 16, 8);
> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4);
> + PAD(buffer_vld2_pad, float, 32, 4);
> +
> + /* Input buffers for vld3, 1 of each size */
> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 8);
> + PAD(buffer_vld3_pad, int, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 4);
> + PAD(buffer_vld3_pad, int, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 2);
> + PAD(buffer_vld3_pad, int, 32, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 1);
> + PAD(buffer_vld3_pad, int, 64, 1);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 8);
> + PAD(buffer_vld3_pad, uint, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 4);
> + PAD(buffer_vld3_pad, uint, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 2);
> + PAD(buffer_vld3_pad, uint, 32, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 1);
> + PAD(buffer_vld3_pad, uint, 64, 1);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 8);
> + PAD(buffer_vld3_pad, poly, 8, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4);
> + PAD(buffer_vld3_pad, poly, 16, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2);
> + PAD(buffer_vld3_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 16);
> + PAD(buffer_vld3_pad, int, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 8);
> + PAD(buffer_vld3_pad, int, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 4);
> + PAD(buffer_vld3_pad, int, 32, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 2);
> + PAD(buffer_vld3_pad, int, 64, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 16);
> + PAD(buffer_vld3_pad, uint, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 8);
> + PAD(buffer_vld3_pad, uint, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 4);
> + PAD(buffer_vld3_pad, uint, 32, 4);
> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 2);
> + PAD(buffer_vld3_pad, uint, 64, 2);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 16);
> + PAD(buffer_vld3_pad, poly, 8, 16);
> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8);
> + PAD(buffer_vld3_pad, poly, 16, 8);
> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4);
> + PAD(buffer_vld3_pad, float, 32, 4);
> +
> + /* Input buffers for vld4, 1 of each size */
> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 8);
> + PAD(buffer_vld4_pad, int, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 4);
> + PAD(buffer_vld4_pad, int, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 2);
> + PAD(buffer_vld4_pad, int, 32, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 1);
> + PAD(buffer_vld4_pad, int, 64, 1);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 8);
> + PAD(buffer_vld4_pad, uint, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 4);
> + PAD(buffer_vld4_pad, uint, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 2);
> + PAD(buffer_vld4_pad, uint, 32, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 1);
> + PAD(buffer_vld4_pad, uint, 64, 1);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 8);
> + PAD(buffer_vld4_pad, poly, 8, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4);
> + PAD(buffer_vld4_pad, poly, 16, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2);
> + PAD(buffer_vld4_pad, float, 32, 2);
> +
> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 16);
> + PAD(buffer_vld4_pad, int, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 8);
> + PAD(buffer_vld4_pad, int, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 4);
> + PAD(buffer_vld4_pad, int, 32, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 2);
> + PAD(buffer_vld4_pad, int, 64, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 16);
> + PAD(buffer_vld4_pad, uint, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 8);
> + PAD(buffer_vld4_pad, uint, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 4);
> + PAD(buffer_vld4_pad, uint, 32, 4);
> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 2);
> + PAD(buffer_vld4_pad, uint, 64, 2);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 16);
> + PAD(buffer_vld4_pad, poly, 8, 16);
> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8);
> + PAD(buffer_vld4_pad, poly, 16, 8);
> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4);
> + PAD(buffer_vld4_pad, float, 32, 4);
> +
> + /* Check vld2_dup/vld2q_dup. */
> + clean_results ();
> +#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
> + TEST_ALL_VLDX_DUP(2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(2, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1");
> +
> + /* Check vld3_dup/vld3q_dup. */
> + clean_results ();
> +#undef TEST_MSG
> +#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
> + TEST_ALL_VLDX_DUP(3);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(3, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1");
> +
> + TEST_ALL_EXTRA_CHUNKS(3, 2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2");
> +
> + /* Check vld4_dup/vld4q_dup */
> + clean_results ();
> +#undef TEST_MSG
> +#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
> + TEST_ALL_VLDX_DUP(4);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 1);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 2);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2");
> +
> + TEST_ALL_EXTRA_CHUNKS(4, 3);
> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3");
> +}
> +
> +int main (void)
> +{
> + exec_vldX_dup ();
> + return 0;
> +}
> --
> 2.1.0
>
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
@ 2015-01-16 15:52 ` Tejas Belagod
2015-01-16 16:32 ` Christophe Lyon
2015-01-19 13:42 ` Marcus Shawcroft
1 sibling, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 15:52 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
No poly ops for vmlx.
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x45f0ae15, 0x45f0b615,
> + 0x45f0be15, 0x45f0c615 };
> +
These expected results are calculated using chained(as opposed to fused)
float MACs, right?
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
@ 2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 15:57 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
No poly ops for vmlx_lane.
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
@ 2015-01-16 16:06 ` Tejas Belagod
2015-01-16 18:12 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:06 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
> vshuffle.inc.
> * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
> vshuffle.inc.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
> new file mode 100644
> index 0000000..928f338
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
> @@ -0,0 +1,139 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* In this case, output variables are arrays of vectors. */
> +#define DECL_VSHUFFLE(T1, W, N) \
> + VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
> + VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
> +
> + /* We need to use a temporary result buffer (result_bis), because
> + the one used for other tests is not large enough. A subset of the
> + result data is moved from result_bis to result, and it is this
> + subset which is used to check the actual behaviour. The next
> + macro enables to move another chunk of data from result_bis to
> + result. */
> +#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N) \
> + VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
> + INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
> + VECT_VAR(vector2, T1, W, N)); \
> + vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
> + VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
> + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> + /* Overwrite "result" with the contents of "result_bis"[X]. */
> +#define TEST_EXTRA_CHUNK(T1, W, N, X) \
> + memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
> + sizeof(VECT_VAR(result, T1, W, N)));
> +
> + DECL_VARIABLE_ALL_VARIANTS(vector1);
> + DECL_VARIABLE_ALL_VARIANTS(vector2);
> +
> + /* We don't need 64 bits variants. */
> +#define DECL_ALL_VSHUFFLE() \
> + DECL_VSHUFFLE(int, 8, 8); \
> + DECL_VSHUFFLE(int, 16, 4); \
> + DECL_VSHUFFLE(int, 32, 2); \
> + DECL_VSHUFFLE(uint, 8, 8); \
> + DECL_VSHUFFLE(uint, 16, 4); \
> + DECL_VSHUFFLE(uint, 32, 2); \
> + DECL_VSHUFFLE(poly, 8, 8); \
> + DECL_VSHUFFLE(poly, 16, 4); \
> + DECL_VSHUFFLE(float, 32, 2); \
> + DECL_VSHUFFLE(int, 8, 16); \
> + DECL_VSHUFFLE(int, 16, 8); \
> + DECL_VSHUFFLE(int, 32, 4); \
> + DECL_VSHUFFLE(uint, 8, 16); \
> + DECL_VSHUFFLE(uint, 16, 8); \
> + DECL_VSHUFFLE(uint, 32, 4); \
> + DECL_VSHUFFLE(poly, 8, 16); \
> + DECL_VSHUFFLE(poly, 16, 8); \
> + DECL_VSHUFFLE(float, 32, 4)
> +
> + DECL_ALL_VSHUFFLE();
> +
> + /* Initialize input "vector" from "buffer". */
> + TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
> + VLOAD(vector1, buffer, , float, f, 32, 2);
> + VLOAD(vector1, buffer, q, float, f, 32, 4);
> +
> + /* Choose arbitrary initialization values. */
> + VDUP(vector2, , int, s, 8, 8, 0x11);
> + VDUP(vector2, , int, s, 16, 4, 0x22);
> + VDUP(vector2, , int, s, 32, 2, 0x33);
> + VDUP(vector2, , uint, u, 8, 8, 0x55);
> + VDUP(vector2, , uint, u, 16, 4, 0x66);
> + VDUP(vector2, , uint, u, 32, 2, 0x77);
> + VDUP(vector2, , poly, p, 8, 8, 0x55);
> + VDUP(vector2, , poly, p, 16, 4, 0x66);
> + VDUP(vector2, , float, f, 32, 2, 33.6f);
> +
> + VDUP(vector2, q, int, s, 8, 16, 0x11);
> + VDUP(vector2, q, int, s, 16, 8, 0x22);
> + VDUP(vector2, q, int, s, 32, 4, 0x33);
> + VDUP(vector2, q, uint, u, 8, 16, 0x55);
> + VDUP(vector2, q, uint, u, 16, 8, 0x66);
> + VDUP(vector2, q, uint, u, 32, 4, 0x77);
> + VDUP(vector2, q, poly, p, 8, 16, 0x55);
> + VDUP(vector2, q, poly, p, 16, 8, 0x66);
> + VDUP(vector2, q, float, f, 32, 4, 33.8f);
> +
> +#define TEST_ALL_VSHUFFLE(INSN) \
> + TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
> + TEST_VSHUFFLE(INSN, , int, s, 16, 4); \
> + TEST_VSHUFFLE(INSN, , int, s, 32, 2); \
> + TEST_VSHUFFLE(INSN, , uint, u, 8, 8); \
> + TEST_VSHUFFLE(INSN, , uint, u, 16, 4); \
> + TEST_VSHUFFLE(INSN, , uint, u, 32, 2); \
> + TEST_VSHUFFLE(INSN, , poly, p, 8, 8); \
> + TEST_VSHUFFLE(INSN, , poly, p, 16, 4); \
> + TEST_VSHUFFLE(INSN, , float, f, 32, 2); \
> + TEST_VSHUFFLE(INSN, q, int, s, 8, 16); \
> + TEST_VSHUFFLE(INSN, q, int, s, 16, 8); \
> + TEST_VSHUFFLE(INSN, q, int, s, 32, 4); \
> + TEST_VSHUFFLE(INSN, q, uint, u, 8, 16); \
> + TEST_VSHUFFLE(INSN, q, uint, u, 16, 8); \
> + TEST_VSHUFFLE(INSN, q, uint, u, 32, 4); \
> + TEST_VSHUFFLE(INSN, q, poly, p, 8, 16); \
> + TEST_VSHUFFLE(INSN, q, poly, p, 16, 8); \
> + TEST_VSHUFFLE(INSN, q, float, f, 32, 4)
> +
> +#define TEST_ALL_EXTRA_CHUNKS() \
> + TEST_EXTRA_CHUNK(int, 8, 8, 1); \
> + TEST_EXTRA_CHUNK(int, 16, 4, 1); \
> + TEST_EXTRA_CHUNK(int, 32, 2, 1); \
> + TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
> + TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
> + TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
> + TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
> + TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
> + TEST_EXTRA_CHUNK(float, 32, 2, 1); \
> + TEST_EXTRA_CHUNK(int, 8, 16, 1); \
> + TEST_EXTRA_CHUNK(int, 16, 8, 1); \
> + TEST_EXTRA_CHUNK(int, 32, 4, 1); \
> + TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
> + TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
> + TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
> + TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
> + TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
> + TEST_EXTRA_CHUNK(float, 32, 4, 1)
> +
> + clean_results ();
> +
> + /* Execute the tests. */
> + TEST_ALL_VSHUFFLE(INSN_NAME);
> +
> + CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
> +
> + TEST_ALL_EXTRA_CHUNKS();
> + CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> +
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
> new file mode 100644
> index 0000000..be18c0f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
> @@ -0,0 +1,93 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results splitted in several chunks. */
> +/* Chunk 0. */
> +VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11,
> + 0xf2, 0xf3, 0x11, 0x11 };
> +VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 };
> +VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
> + 0xf2, 0xf3, 0x55, 0x55 };
> +VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
> +VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
> + 0xf2, 0xf3, 0x55, 0x55 };
> +VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
> +VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
> +VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
> + 0xf2, 0xf3, 0x11, 0x11,
> + 0xf4, 0xf5, 0x11, 0x11,
> + 0xf6, 0xf7, 0x11, 0x11 };
> +VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22,
> + 0xfff2, 0xfff3, 0x22, 0x22 };
> +VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x33, 0x33 };
> +VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
> + 0xf2, 0xf3, 0x55, 0x55,
> + 0xf4, 0xf5, 0x55, 0x55,
> + 0xf6, 0xf7, 0x55, 0x55 };
> +VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
> + 0xfff2, 0xfff3, 0x66, 0x66 };
> +VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x77, 0x77 };
> +VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
> + 0xf2, 0xf3, 0x55, 0x55,
> + 0xf4, 0xf5, 0x55, 0x55,
> + 0xf6, 0xf7, 0x55, 0x55 };
> +VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
> + 0xfff2, 0xfff3, 0x66, 0x66 };
> +VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
> + 0x42073333, 0x42073333 };
> +
> +/* Chunk 1. */
> +VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf4, 0xf5, 0x11, 0x11,
> + 0xf6, 0xf7, 0x11, 0x11 };
> +VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff2, 0xfff3, 0x22, 0x22 };
> +VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
> +VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
> + 0xf6, 0xf7, 0x55, 0x55 };
> +VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
> +VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
> +VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
> + 0xf6, 0xf7, 0x55, 0x55 };
> +VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
> +VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
> +VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
> + 0xfa, 0xfb, 0x11, 0x11,
> + 0xfc, 0xfd, 0x11, 0x11,
> + 0xfe, 0xff, 0x11, 0x11 };
> +VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff4, 0xfff5, 0x22, 0x22,
> + 0xfff6, 0xfff7, 0x22, 0x22 };
> +VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x33, 0x33 };
> +VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
> + 0xfa, 0xfb, 0x55, 0x55,
> + 0xfc, 0xfd, 0x55, 0x55,
> + 0xfe, 0xff, 0x55, 0x55 };
> +VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
> + 0xfff6, 0xfff7, 0x66, 0x66 };
> +VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x77, 0x77 };
> +VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333,
> + 0x3333333333333333 };
> +VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
> + 0xfa, 0xfb, 0x55, 0x55,
> + 0xfc, 0xfd, 0x55, 0x55,
> + 0xfe, 0xff, 0x55, 0x55 };
> +VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
> + 0xfff6, 0xfff7, 0x66, 0x66 };
> +VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
> + 0x42073333, 0x42073333 };
> +
> +#define INSN_NAME vtrn
> +#define TEST_MSG "VTRN/VTRNQ"
> +
> +#include "vshuffle.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
> index 53f875e..ec9ded3 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
> @@ -99,147 +99,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66, 0x66, 0x66,
> VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
> 0x42073333, 0x42073333 };
>
> -#ifndef INSN_NAME
> #define INSN_NAME vuzp
> #define TEST_MSG "VUZP/VUZPQ"
> -#endif
>
> -#define FNNAME1(NAME) exec_ ## NAME
> -#define FNNAME(NAME) FNNAME1(NAME)
> -
> -void FNNAME (INSN_NAME) (void)
> -{
> - /* In this case, output variables are arrays of vectors. */
> -#define DECL_VUZP(T1, W, N) \
> - VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
> - VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
> -
> - /* We need to use a temporary result buffer (result_bis), because
> - the one used for other tests is not large enough. A subset of the
> - result data is moved from result_bis to result, and it is this
> - subset which is used to check the actual behaviour. The next
> - macro enables to move another chunk of data from result_bis to
> - result. */
> -#define TEST_VUZP(INSN, Q, T1, T2, W, N) \
> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
> - INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
> - VECT_VAR(vector2, T1, W, N)); \
> - vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
> - memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
> - sizeof(VECT_VAR(result, T1, W, N)));
> -
> - /* Overwrite "result" with the contents of "result_bis"[X]. */
> -#define TEST_EXTRA_CHUNK(T1, W, N, X) \
> - memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
> - sizeof(VECT_VAR(result, T1, W, N)));
> -
> - DECL_VARIABLE_ALL_VARIANTS(vector1);
> - DECL_VARIABLE_ALL_VARIANTS(vector2);
> -
> - /* We don't need 64 bits variants. */
> -#define DECL_ALL_VUZP() \
> - DECL_VUZP(int, 8, 8); \
> - DECL_VUZP(int, 16, 4); \
> - DECL_VUZP(int, 32, 2); \
> - DECL_VUZP(uint, 8, 8); \
> - DECL_VUZP(uint, 16, 4); \
> - DECL_VUZP(uint, 32, 2); \
> - DECL_VUZP(poly, 8, 8); \
> - DECL_VUZP(poly, 16, 4); \
> - DECL_VUZP(float, 32, 2); \
> - DECL_VUZP(int, 8, 16); \
> - DECL_VUZP(int, 16, 8); \
> - DECL_VUZP(int, 32, 4); \
> - DECL_VUZP(uint, 8, 16); \
> - DECL_VUZP(uint, 16, 8); \
> - DECL_VUZP(uint, 32, 4); \
> - DECL_VUZP(poly, 8, 16); \
> - DECL_VUZP(poly, 16, 8); \
> - DECL_VUZP(float, 32, 4)
> -
> - DECL_ALL_VUZP();
> -
> - /* Initialize input "vector" from "buffer". */
> - TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
> - VLOAD(vector1, buffer, , float, f, 32, 2);
> - VLOAD(vector1, buffer, q, float, f, 32, 4);
> -
> - /* Choose arbitrary initialization values. */
> - VDUP(vector2, , int, s, 8, 8, 0x11);
> - VDUP(vector2, , int, s, 16, 4, 0x22);
> - VDUP(vector2, , int, s, 32, 2, 0x33);
> - VDUP(vector2, , uint, u, 8, 8, 0x55);
> - VDUP(vector2, , uint, u, 16, 4, 0x66);
> - VDUP(vector2, , uint, u, 32, 2, 0x77);
> - VDUP(vector2, , poly, p, 8, 8, 0x55);
> - VDUP(vector2, , poly, p, 16, 4, 0x66);
> - VDUP(vector2, , float, f, 32, 2, 33.6f);
> -
> - VDUP(vector2, q, int, s, 8, 16, 0x11);
> - VDUP(vector2, q, int, s, 16, 8, 0x22);
> - VDUP(vector2, q, int, s, 32, 4, 0x33);
> - VDUP(vector2, q, uint, u, 8, 16, 0x55);
> - VDUP(vector2, q, uint, u, 16, 8, 0x66);
> - VDUP(vector2, q, uint, u, 32, 4, 0x77);
> - VDUP(vector2, q, poly, p, 8, 16, 0x55);
> - VDUP(vector2, q, poly, p, 16, 8, 0x66);
> - VDUP(vector2, q, float, f, 32, 4, 33.8f);
> -
> -#define TEST_ALL_VUZP(INSN) \
> - TEST_VUZP(INSN, , int, s, 8, 8); \
> - TEST_VUZP(INSN, , int, s, 16, 4); \
> - TEST_VUZP(INSN, , int, s, 32, 2); \
> - TEST_VUZP(INSN, , uint, u, 8, 8); \
> - TEST_VUZP(INSN, , uint, u, 16, 4); \
> - TEST_VUZP(INSN, , uint, u, 32, 2); \
> - TEST_VUZP(INSN, , poly, p, 8, 8); \
> - TEST_VUZP(INSN, , poly, p, 16, 4); \
> - TEST_VUZP(INSN, , float, f, 32, 2); \
> - TEST_VUZP(INSN, q, int, s, 8, 16); \
> - TEST_VUZP(INSN, q, int, s, 16, 8); \
> - TEST_VUZP(INSN, q, int, s, 32, 4); \
> - TEST_VUZP(INSN, q, uint, u, 8, 16); \
> - TEST_VUZP(INSN, q, uint, u, 16, 8); \
> - TEST_VUZP(INSN, q, uint, u, 32, 4); \
> - TEST_VUZP(INSN, q, poly, p, 8, 16); \
> - TEST_VUZP(INSN, q, poly, p, 16, 8); \
> - TEST_VUZP(INSN, q, float, f, 32, 4)
> -
> -#define TEST_ALL_EXTRA_CHUNKS() \
> - TEST_EXTRA_CHUNK(int, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(int, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(int, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(float, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(int, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(int, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(int, 32, 4, 1); \
> - TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
> - TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(float, 32, 4, 1)
> -
> - clean_results ();
> -
> - /* Execute the tests. */
> - TEST_ALL_VUZP(INSN_NAME);
> -
> - CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
> -
> - TEST_ALL_EXTRA_CHUNKS();
> - CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
> -}
> -
> -int main (void)
> -{
> - FNNAME (INSN_NAME) ();
> -
> - return 0;
> -}
> +#include "vshuffle.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
> index a1f1eee..05faa8a 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
> @@ -97,147 +97,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2, 0xfff6, 0x66, 0x66,
> VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
> 0x42073333, 0x42073333 };
>
> -#ifndef INSN_NAME
> #define INSN_NAME vzip
> #define TEST_MSG "VZIP/VZIPQ"
> -#endif
>
> -#define FNNAME1(NAME) exec_ ## NAME
> -#define FNNAME(NAME) FNNAME1(NAME)
> -
> -void FNNAME (INSN_NAME) (void)
> -{
> - /* In this case, output variables are arrays of vectors. */
> -#define DECL_VZIP(T1, W, N) \
> - VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2); \
> - VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
> -
> - /* We need to use a temporary result buffer (result_bis), because
> - the one used for other tests is not large enough. A subset of the
> - result data is moved from result_bis to result, and it is this
> - subset which is used to check the actual behaviour. The next
> - macro enables to move another chunk of data from result_bis to
> - result. */
> -#define TEST_VZIP(INSN, Q, T1, T2, W, N) \
> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
> - INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
> - VECT_VAR(vector2, T1, W, N)); \
> - vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
> - memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
> - sizeof(VECT_VAR(result, T1, W, N)));
> -
> - /* Overwrite "result" with the contents of "result_bis"[X]. */
> -#define TEST_EXTRA_CHUNK(T1, W, N, X) \
> - memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W, N)[X*N]), \
> - sizeof(VECT_VAR(result, T1, W, N)));
> -
> - DECL_VARIABLE_ALL_VARIANTS(vector1);
> - DECL_VARIABLE_ALL_VARIANTS(vector2);
> -
> - /* We don't need 64 bits variants. */
> -#define DECL_ALL_VZIP() \
> - DECL_VZIP(int, 8, 8); \
> - DECL_VZIP(int, 16, 4); \
> - DECL_VZIP(int, 32, 2); \
> - DECL_VZIP(uint, 8, 8); \
> - DECL_VZIP(uint, 16, 4); \
> - DECL_VZIP(uint, 32, 2); \
> - DECL_VZIP(poly, 8, 8); \
> - DECL_VZIP(poly, 16, 4); \
> - DECL_VZIP(float, 32, 2); \
> - DECL_VZIP(int, 8, 16); \
> - DECL_VZIP(int, 16, 8); \
> - DECL_VZIP(int, 32, 4); \
> - DECL_VZIP(uint, 8, 16); \
> - DECL_VZIP(uint, 16, 8); \
> - DECL_VZIP(uint, 32, 4); \
> - DECL_VZIP(poly, 8, 16); \
> - DECL_VZIP(poly, 16, 8); \
> - DECL_VZIP(float, 32, 4)
> -
> - DECL_ALL_VZIP();
> -
> - /* Initialize input "vector" from "buffer". */
> - TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
> - VLOAD(vector1, buffer, , float, f, 32, 2);
> - VLOAD(vector1, buffer, q, float, f, 32, 4);
> -
> - /* Choose arbitrary initialization values. */
> - VDUP(vector2, , int, s, 8, 8, 0x11);
> - VDUP(vector2, , int, s, 16, 4, 0x22);
> - VDUP(vector2, , int, s, 32, 2, 0x33);
> - VDUP(vector2, , uint, u, 8, 8, 0x55);
> - VDUP(vector2, , uint, u, 16, 4, 0x66);
> - VDUP(vector2, , uint, u, 32, 2, 0x77);
> - VDUP(vector2, , poly, p, 8, 8, 0x55);
> - VDUP(vector2, , poly, p, 16, 4, 0x66);
> - VDUP(vector2, , float, f, 32, 2, 33.6f);
> -
> - VDUP(vector2, q, int, s, 8, 16, 0x11);
> - VDUP(vector2, q, int, s, 16, 8, 0x22);
> - VDUP(vector2, q, int, s, 32, 4, 0x33);
> - VDUP(vector2, q, uint, u, 8, 16, 0x55);
> - VDUP(vector2, q, uint, u, 16, 8, 0x66);
> - VDUP(vector2, q, uint, u, 32, 4, 0x77);
> - VDUP(vector2, q, poly, p, 8, 16, 0x55);
> - VDUP(vector2, q, poly, p, 16, 8, 0x66);
> - VDUP(vector2, q, float, f, 32, 4, 33.8f);
> -
> -#define TEST_ALL_VZIP(INSN) \
> - TEST_VZIP(INSN, , int, s, 8, 8); \
> - TEST_VZIP(INSN, , int, s, 16, 4); \
> - TEST_VZIP(INSN, , int, s, 32, 2); \
> - TEST_VZIP(INSN, , uint, u, 8, 8); \
> - TEST_VZIP(INSN, , uint, u, 16, 4); \
> - TEST_VZIP(INSN, , uint, u, 32, 2); \
> - TEST_VZIP(INSN, , poly, p, 8, 8); \
> - TEST_VZIP(INSN, , poly, p, 16, 4); \
> - TEST_VZIP(INSN, , float, f, 32, 2); \
> - TEST_VZIP(INSN, q, int, s, 8, 16); \
> - TEST_VZIP(INSN, q, int, s, 16, 8); \
> - TEST_VZIP(INSN, q, int, s, 32, 4); \
> - TEST_VZIP(INSN, q, uint, u, 8, 16); \
> - TEST_VZIP(INSN, q, uint, u, 16, 8); \
> - TEST_VZIP(INSN, q, uint, u, 32, 4); \
> - TEST_VZIP(INSN, q, poly, p, 8, 16); \
> - TEST_VZIP(INSN, q, poly, p, 16, 8); \
> - TEST_VZIP(INSN, q, float, f, 32, 4)
> -
> -#define TEST_ALL_EXTRA_CHUNKS() \
> - TEST_EXTRA_CHUNK(int, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(int, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(int, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
> - TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
> - TEST_EXTRA_CHUNK(float, 32, 2, 1); \
> - TEST_EXTRA_CHUNK(int, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(int, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(int, 32, 4, 1); \
> - TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
> - TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
> - TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
> - TEST_EXTRA_CHUNK(float, 32, 4, 1)
> -
> - clean_results ();
> -
> - /* Execute the tests. */
> - TEST_ALL_VZIP(INSN_NAME);
> -
> - CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
> -
> - TEST_ALL_EXTRA_CHUNKS();
> - CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
> -}
> -
> -int main (void)
> -{
> - FNNAME (INSN_NAME) ();
> -
> - return 0;
> -}
> +#include "vshuffle.inc"
> --
> 2.1.0
>
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
@ 2015-01-16 16:21 ` Tejas Belagod
2015-01-16 16:35 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:21 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
> vXXXhn.inc.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
> new file mode 100644
> index 0000000..0dbcc92
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
> @@ -0,0 +1,50 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
> +#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
> + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
> + VECT_VAR(vector2, T1, W, N)); \
> + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
> +
> +#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
> + TEST_VADDHN1(INSN, T1, T2, W, W2, N)
> +
Minor nit. If this is a template file, maybe you should name this macro
TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
confusing.
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
Though never used, poly seems to have sneaked in here too.
Otherwise, LGTM.
Thanks,
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests.
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
@ 2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:22 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
> new file mode 100644
> index 0000000..1e6bab3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc
> @@ -0,0 +1,89 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* vector_res = OP(vector, vector3, vector4),
> + then store the result. */
> +#define TEST_VMLXL1(INSN, T1, T2, W, W2, N) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector3, T1, W2, N), \
> + VECT_VAR(vector4, T1, W2, N)); \
> + vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_VMLXL(INSN, T1, T2, W, W2, N) \
> + TEST_VMLXL1(INSN, T1, T2, W, W2, N)
> +
> + DECL_VARIABLE(vector, int, 16, 8);
> + DECL_VARIABLE(vector3, int, 8, 8);
> + DECL_VARIABLE(vector4, int, 8, 8);
> + DECL_VARIABLE(vector_res, int, 16, 8);
> +
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector3, int, 16, 4);
> + DECL_VARIABLE(vector4, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> +
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector3, int, 32, 2);
> + DECL_VARIABLE(vector4, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + DECL_VARIABLE(vector, uint, 16, 8);
> + DECL_VARIABLE(vector3, uint, 8, 8);
> + DECL_VARIABLE(vector4, uint, 8, 8);
> + DECL_VARIABLE(vector_res, uint, 16, 8);
> +
> + DECL_VARIABLE(vector, uint, 32, 4);
> + DECL_VARIABLE(vector3, uint, 16, 4);
> + DECL_VARIABLE(vector4, uint, 16, 4);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> +
> + DECL_VARIABLE(vector, uint, 64, 2);
> + DECL_VARIABLE(vector3, uint, 32, 2);
> + DECL_VARIABLE(vector4, uint, 32, 2);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, q, int, s, 16, 8);
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> + VLOAD(vector, buffer, q, uint, u, 16, 8);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 64, 2);
> +
> + VDUP(vector3, , int, s, 8, 8, 0x55);
> + VDUP(vector4, , int, s, 8, 8, 0xBB);
> + VDUP(vector3, , int, s, 16, 4, 0x55);
> + VDUP(vector4, , int, s, 16, 4, 0xBB);
> + VDUP(vector3, , int, s, 32, 2, 0x55);
> + VDUP(vector4, , int, s, 32, 2, 0xBB);
> + VDUP(vector3, , uint, u, 8, 8, 0x55);
> + VDUP(vector4, , uint, u, 8, 8, 0xBB);
> + VDUP(vector3, , uint, u, 16, 4, 0x55);
> + VDUP(vector4, , uint, u, 16, 4, 0xBB);
> + VDUP(vector3, , uint, u, 32, 2, 0x55);
> + VDUP(vector4, , uint, u, 32, 2, 0xBB);
> +
> + TEST_VMLXL(INSN_NAME, int, s, 16, 8, 8);
> + TEST_VMLXL(INSN_NAME, int, s, 32, 16, 4);
> + TEST_VMLXL(INSN_NAME, int, s, 64, 32, 2);
> + TEST_VMLXL(INSN_NAME, uint, u, 16, 8, 8);
> + TEST_VMLXL(INSN_NAME, uint, u, 32, 16, 4);
> + TEST_VMLXL(INSN_NAME, uint, u, 64, 32, 2);
> +
> + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
> new file mode 100644
> index 0000000..c147f31
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal.c
> @@ -0,0 +1,18 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlal
> +#define TEST_MSG "VMLAL"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xe907, 0xe908, 0xe909, 0xe90a,
> + 0xe90b, 0xe90c, 0xe90d, 0xe90e };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
> + 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
> +
> +#include "vmlXl.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
> new file mode 100644
> index 0000000..6c984ae
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl.c
> @@ -0,0 +1,22 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlsl
> +#define TEST_MSG "VMLSL"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x16d9, 0x16da, 0x16db, 0x16dc,
> + 0x16dd, 0x16de, 0x16df, 0x16e0 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> + 0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
> + 0xffffffffffffc1da };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
> + 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> + 0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
> + 0xffffffffffffc1da };
> +
> +#include "vmlXl.inc"
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-16 14:08 ` Tejas Belagod
@ 2015-01-16 16:23 ` Christophe Lyon
2015-01-16 17:20 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 16:23 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 14:56, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +#ifndef NO_FLOAT_VARIANT
>> + VLOAD(vector, buffer, , float, f, 32, 2);
>> + VLOAD(vector, buffer, q, float, f, 32, 4);
>> +#endif
>>
> ....
>>
>> +#ifndef NO_FLOAT_VARIANT
>> + VDUP(vector2, , float, f, 32, 2, -15.5f);
>> + VDUP(vector2, q, float, f, 32, 4, -14.5f);
>> +#endif
>> +
>> +#ifndef NO_FLOAT_VARIANT
>> +#define FLOAT_VARIANT(MACRO, VAR) \
>> + MACRO(VAR, , float, f, 32, 2); \
>> + MACRO(VAR, q, float, f, 32, 4)
>> +#else
>> +#define FLOAT_VARIANT(MACRO, VAR)
>> +#endif
>
>
> Double negative! :-) Probably easier on the reader to avoid it, but your
> call.
Oh yes... I am importing my existing code, so I try to minimize changes.
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> new file mode 100644
>> index 0000000..2591b16
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
>> @@ -0,0 +1,64 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define INSN_NAME vmax
>> +#define TEST_MSG "VMAX/VMAXQ"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf8, 0xf9, 0xfa, 0xfb,
>> + 0xfc, 0xfd, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf9, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xfa, 0xfb,
>> + 0xfc, 0xfd, 0xfe, 0xff };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
>> + 0xc1600000, 0xc1500000 };
>> +
>> +/* Expected results with special FP values. */
>> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
>> + 0x7f800000, 0x7f800000 };
>> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
>> + 0x3f800000, 0x3f800000 };
>> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
>> +
>> +#include "binary_op_no64.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> new file mode 100644
>> index 0000000..2b5e87c
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
>> @@ -0,0 +1,66 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define INSN_NAME vmin
>> +#define TEST_MSG "VMIN/VMINQ"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf3, 0xf3, 0xf3, 0xf3 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf3, 0xf3, 0xf3, 0xf3 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf4, 0xf4, 0xf4,
>> + 0xf4, 0xf4, 0xf4, 0xf4 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>> + 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7,
>> + 0xf8, 0xf9, 0xf9, 0xf9,
>> + 0xf9, 0xf9, 0xf9, 0xf9 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
>> + 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>> + 0xc1680000, 0xc1680000 };
>> +/* Expected results with special FP values. */
>> +VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
>> + 0x7fc00000, 0x7fc00000 };
>> +VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
>> + 0x3f800000, 0x3f800000 };
>> +VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0xff800000, 0xff800000,
>> + 0xff800000, 0xff800000 };
>> +VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x80000000, 0x80000000,
>> + 0x80000000, 0x80000000 };
>> +VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x80000000, 0x80000000,
>> + 0x80000000, 0x80000000 };
>> +
>> +#include "binary_op_no64.inc"
>
>
> vmax and vmin do have v<maxmin>_f64 and v<maxmin>q_f64 variants.
My existing tests only cover armv7 so far.
I do plan to expand them once they are all in GCC.
> Otherwise, they look good to me(but I can't approve it).
>
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
@ 2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:23 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
> new file mode 100644
> index 0000000..ca45134
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc
> @@ -0,0 +1,70 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* vector_res = vmlxl_lane(vector, vector3, vector4, lane),
> + then store the result. */
> +#define TEST_VMLXL_LANE1(INSN, T1, T2, W, W2, N, V) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector3, T1, W2, N), \
> + VECT_VAR(vector4, T1, W2, N), \
> + V); \
> + vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_VMLXL_LANE(INSN, T1, T2, W, W2, N, V) \
> + TEST_VMLXL_LANE1(INSN, T1, T2, W, W2, N, V)
> +
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector3, int, 16, 4);
> + DECL_VARIABLE(vector4, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> +
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector3, int, 32, 2);
> + DECL_VARIABLE(vector4, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + DECL_VARIABLE(vector, uint, 32, 4);
> + DECL_VARIABLE(vector3, uint, 16, 4);
> + DECL_VARIABLE(vector4, uint, 16, 4);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> +
> + DECL_VARIABLE(vector, uint, 64, 2);
> + DECL_VARIABLE(vector3, uint, 32, 2);
> + DECL_VARIABLE(vector4, uint, 32, 2);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 64, 2);
> +
> + VDUP(vector3, , int, s, 16, 4, 0x55);
> + VDUP(vector4, , int, s, 16, 4, 0xBB);
> + VDUP(vector3, , int, s, 32, 2, 0x55);
> + VDUP(vector4, , int, s, 32, 2, 0xBB);
> + VDUP(vector3, , uint, u, 16, 4, 0x55);
> + VDUP(vector4, , uint, u, 16, 4, 0xBB);
> + VDUP(vector3, , uint, u, 32, 2, 0x55);
> + VDUP(vector4, , uint, u, 32, 2, 0xBB);
> +
> + TEST_VMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 2);
> + TEST_VMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 1);
> + TEST_VMLXL_LANE(INSN_NAME, uint, u, 32, 16, 4, 2);
> + TEST_VMLXL_LANE(INSN_NAME, uint, u, 64, 32, 2, 1);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c
> new file mode 100644
> index 0000000..0a384a2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c
> @@ -0,0 +1,14 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlal_lane
> +#define TEST_MSG "VMLAL_LANE"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x3e07, 0x3e08 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3e07, 0x3e08 };
> +
> +#include "vmlXl_lane.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c
> new file mode 100644
> index 0000000..8b944a0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c
> @@ -0,0 +1,18 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlsl_lane
> +#define TEST_MSG "VMLSL_LANE"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> + 0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffc1d9,
> + 0xffffffffffffc1da };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
> + 0xffffc1db, 0xffffc1dc };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffc1d9,
> + 0xffffffffffffc1da };
> +
> +#include "vmlXl_lane.inc"
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
@ 2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:29 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
> new file mode 100644
> index 0000000..a968584
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc
> @@ -0,0 +1,61 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* vector_res = vmlxl_n(vector, vector2, val),
> + then store the result. */
> +#define TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V) \
> + VECT_VAR(vector_res, T1, W, N) = INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector2, T1, W2, N), \
> + V); \
> + vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_VMLXL_N(INSN, T1, T2, W, W2, N, V) \
> + TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V)
> +
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> +
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + DECL_VARIABLE(vector, uint, 32, 4);
> + DECL_VARIABLE(vector2, uint, 16, 4);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> +
> + DECL_VARIABLE(vector, uint, 64, 2);
> + DECL_VARIABLE(vector2, uint, 32, 2);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 64, 2);
> +
> + VDUP(vector2, , int, s, 16, 4, 0x55);
> + VDUP(vector2, , int, s, 32, 2, 0x55);
> + VDUP(vector2, , uint, u, 16, 4, 0x55);
> + VDUP(vector2, , uint, u, 32, 2, 0x55);
> +
> + /* Choose multiplier arbitrarily. */
> + TEST_VMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x11);
> + TEST_VMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x22);
> + TEST_VMLXL_N(INSN_NAME, uint, u, 32, 16, 4, 0x33);
> + TEST_VMLXL_N(INSN_NAME, uint, u, 64, 32, 2, 0x33);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c
> new file mode 100644
> index 0000000..118068c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c
> @@ -0,0 +1,14 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlal_n
> +#define TEST_MSG "VMLAL_N"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x595, 0x596, 0x597, 0x598 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xb3a, 0xb3b };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x10df, 0x10e0 };
> +
> +#include "vmlXl_n.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c
> new file mode 100644
> index 0000000..a26c69f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c
> @@ -0,0 +1,18 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vmlsl_n
> +#define TEST_MSG "VMLSL_N"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffa4b, 0xfffffa4c,
> + 0xfffffa4d, 0xfffffa4e };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffff4a6,
> + 0xfffffffffffff4a7 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffef01, 0xffffef02,
> + 0xffffef03, 0xffffef04 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffef01,
> + 0xffffffffffffef02 };
> +
> +#include "vmlXl_n.inc"
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
@ 2015-01-16 16:30 ` Tejas Belagod
2015-01-20 15:33 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:30 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
No poly vmlx_n, otherwise LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests.
2015-01-16 14:31 ` Tejas Belagod
@ 2015-01-16 16:31 ` Christophe Lyon
2015-01-16 17:22 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 16:31 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 15:09, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> new file mode 100644
>> index 0000000..168cf5e
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c
>> @@ -0,0 +1,129 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xf0, 0xaa };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xf0 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> + 0xaaaa, 0xfff0, 0xaaaa, 0xaaaa };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> + 0xfffffff0, 0xaaaaaaaa };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaaaaaaaaaaaaaaaa,
>> + 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xf0, 0xaa, 0xaa, 0xaa };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> + 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> + 0xfffffff0, 0xaaaaaaaa };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffffffffffff0,
>> + 0xaaaaaaaaaaaaaaaa };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xaa, 0xaa, 0xaa, 0xaa,
>> + 0xf0, 0xaa, 0xaa, 0xaa };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
>> + 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa,
>> + 0xc1800000, 0xaaaaaaaa };
>> +
>> +#define TEST_MSG "VLD1_LANE/VLD1_LANEQ"
>> +void exec_vld1_lane (void)
>> +{
>> + /* Fill vector_src with 0xAA, then load 1 lane. */
>> +#define TEST_VLD1_LANE(Q, T1, T2, W, N, L) \
>> + memset (VECT_VAR(buffer_src, T1, W, N), 0xAA, W/8*N);
>> \
>> + VECT_VAR(vector_src, T1, W, N) = \
>> + vld1##Q##_##T2##W(VECT_VAR(buffer_src, T1, W, N)); \
>> + VECT_VAR(vector, T1, W, N) = \
>> + vld1##Q##_lane_##T2##W(VECT_VAR(buffer, T1, W, N), \
>> + VECT_VAR(vector_src, T1, W, N), L); \
>> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector, T1, W,
>> N))
>> +
>> + DECL_VARIABLE_ALL_VARIANTS(vector);
>> + DECL_VARIABLE_ALL_VARIANTS(vector_src);
>> +
>> + ARRAY(buffer_src, int, 8, 8);
>> + ARRAY(buffer_src, int, 16, 4);
>> + ARRAY(buffer_src, int, 32, 2);
>> + ARRAY(buffer_src, int, 64, 1);
>> + ARRAY(buffer_src, uint, 8, 8);
>> + ARRAY(buffer_src, uint, 16, 4);
>> + ARRAY(buffer_src, uint, 32, 2);
>> + ARRAY(buffer_src, uint, 64, 1);
>> + ARRAY(buffer_src, poly, 8, 8);
>> + ARRAY(buffer_src, poly, 16, 4);
>> + ARRAY(buffer_src, float, 32, 2);
>> +
>> + ARRAY(buffer_src, int, 8, 16);
>> + ARRAY(buffer_src, int, 16, 8);
>> + ARRAY(buffer_src, int, 32, 4);
>> + ARRAY(buffer_src, int, 64, 2);
>> + ARRAY(buffer_src, uint, 8, 16);
>> + ARRAY(buffer_src, uint, 16, 8);
>> + ARRAY(buffer_src, uint, 32, 4);
>> + ARRAY(buffer_src, uint, 64, 2);
>> + ARRAY(buffer_src, poly, 8, 16);
>> + ARRAY(buffer_src, poly, 16, 8);
>> + ARRAY(buffer_src, float, 32, 4);
>> +
>> + clean_results ();
>> +
>> + /* Choose lane arbitrarily. */
>> + TEST_VLD1_LANE(, int, s, 8, 8, 6);
>> + TEST_VLD1_LANE(, int, s, 16, 4, 3);
>> + TEST_VLD1_LANE(, int, s, 32, 2, 1);
>> + TEST_VLD1_LANE(, int, s, 64, 1, 0);
>> + TEST_VLD1_LANE(, uint, u, 8, 8, 7);
>> + TEST_VLD1_LANE(, uint, u, 16, 4, 3);
>> + TEST_VLD1_LANE(, uint, u, 32, 2, 1);
>> + TEST_VLD1_LANE(, uint, u, 64, 1, 0);
>> + TEST_VLD1_LANE(, poly, p, 8, 8, 7);
>> + TEST_VLD1_LANE(, poly, p, 16, 4, 3);
>> + TEST_VLD1_LANE(, float, f, 32, 2, 1);
>> +
>> + TEST_VLD1_LANE(q, int, s, 8, 16, 15);
>> + TEST_VLD1_LANE(q, int, s, 16, 8, 5);
>> + TEST_VLD1_LANE(q, int, s, 32, 4, 2);
>> + TEST_VLD1_LANE(q, int, s, 64, 2, 1);
>> + TEST_VLD1_LANE(q, uint, u, 8, 16, 12);
>> + TEST_VLD1_LANE(q, uint, u, 16, 8, 6);
>> + TEST_VLD1_LANE(q, uint, u, 32, 4, 2);
>> + TEST_VLD1_LANE(q, uint, u, 64, 2, 0);
>> + TEST_VLD1_LANE(q, poly, p, 8, 16, 12);
>> + TEST_VLD1_LANE(q, poly, p, 16, 8, 6);
>> + TEST_VLD1_LANE(q, float, f, 32, 4, 2);
>> +
>
>
> Hmm.. again, I don't see vld1<q>_lane_f64?
Same answer: unless I am mistaken it isn't supported on armv7, and
indeed the tests need to be expanded.
>> +#ifndef __CC_ARM
>> + /* Check runtime assertions. With RVCT, the check is performed at
>> + compile-time */
>> + // TEST_VLD1_LANE(, int, s, 64, 1, 1);
>> +#endif
>> +
>
> Does this belong in this patch?
Good catch!
The original testsuite uses RVCT features not present in GCC, and I
forgot to remove this chunk.
> Otherwise, it looks good to me(I cannot approve though).
>
> Thanks,
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests.
2015-01-16 15:52 ` Tejas Belagod
@ 2015-01-16 16:32 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 16:32 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 16:35, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>
>
> No poly ops for vmlx.
>
Indeed, it's not used I shall remove it.
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x45f0ae15, 0x45f0b615,
>> + 0x45f0be15, 0x45f0c615 };
>> +
>
> These expected results are calculated using chained(as opposed to fused)
> float MACs, right?
>
IIRC, yes.
> Otherwise, LGTM.
>
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
2015-01-16 16:21 ` Tejas Belagod
@ 2015-01-16 16:35 ` Christophe Lyon
2015-01-20 15:30 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 16:35 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 17:07, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
>> vXXXhn.inc.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>> new file mode 100644
>> index 0000000..0dbcc92
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>> @@ -0,0 +1,50 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> + /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result.
>> */
>> +#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
>> + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W,
>> N), \
>> + VECT_VAR(vector2, T1, W,
>> N)); \
>> + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2,
>> N))
>> +
>> +#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
>> + TEST_VADDHN1(INSN, T1, T2, W, W2, N)
>> +
>
>
> Minor nit. If this is a template file, maybe you should name this macro
> TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
> confusing.
Agreed.
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>
>
> Though never used, poly seems to have sneaked in here too.
Indeed, sorry for that.
I rushed to have as many tests as possible ready before stage 4, but
obviously I missed a few cleanups.
> Otherwise, LGTM.
>
> Thanks,
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
@ 2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:45 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
> new file mode 100644
> index 0000000..cd61fd4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc
> @@ -0,0 +1,63 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* vector_res = OP(vector, vector3, vector4),
> + then store the result. */
> +#define TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector3, T1, W2, N), \
> + VECT_VAR(vector4, T1, W2, N)); \
> + vst1q_##T2##W(VECT_VAR(result, T1, W, N), \
> + VECT_VAR(vector_res, T1, W, N)); \
> + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> +#define TEST_VQDMLXL(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT) \
> + TEST_VQDMLXL1(INSN, T1, T2, W, W2, N, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector3, int, 16, 4);
> + DECL_VARIABLE(vector4, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector3, int, 32, 2);
> + DECL_VARIABLE(vector4, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> +
> + VDUP(vector3, , int, s, 16, 4, 0x55);
> + VDUP(vector4, , int, s, 16, 4, 0xBB);
> + VDUP(vector3, , int, s, 32, 2, 0x55);
> + VDUP(vector4, , int, s, 32, 2, 0xBB);
> +
> + TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat, "");
> + TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat, "");
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> +
> + VDUP(vector3, , int, s, 16, 4, 0x8000);
> + VDUP(vector4, , int, s, 16, 4, 0x8000);
> + VDUP(vector3, , int, s, 32, 2, 0x80000000);
> + VDUP(vector4, , int, s, 32, 2, 0x80000000);
> +
> +#define TEST_MSG2 "with saturation"
> + TEST_VQDMLXL(INSN_NAME, int, s, 32, 16, 4, expected_cumulative_sat2, TEST_MSG2);
> + TEST_VQDMLXL(INSN_NAME, int, s, 64, 32, 2, expected_cumulative_sat2, TEST_MSG2);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c
> new file mode 100644
> index 0000000..c53a90a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c
> @@ -0,0 +1,27 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vqdmlal
> +#define TEST_MSG "VQDMLAL"
> +
> +/* Expected values of cumulative_saturation flag. */
> +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
> +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x7c1e, 0x7c1f, 0x7c20, 0x7c21 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x7c1e, 0x7c1f };
> +
> +/* Expected values of cumulative_saturation flag when saturation
> + occurs. */
> +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
> +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
> +
> +/* Expected results when saturation occurs. */
> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0,
> + 0x7ffffff1, 0x7ffffff2 };
> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef,
> + 0x7ffffffffffffff0 };
> +
> +#include "vqdmlXl.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c
> new file mode 100644
> index 0000000..56e0b61
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c
> @@ -0,0 +1,29 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vqdmlsl
> +#define TEST_MSG "VQDMLSL"
> +
> +/* Expected values of cumulative_saturation flag. */
> +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
> +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffff83c2, 0xffff83c3,
> + 0xffff83c4, 0xffff83c5 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffff83c2,
> + 0xffffffffffff83c3 };
> +
> +/* Expected values of cumulative_saturation flag when saturation
> + occurs. */
> +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
> +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
> +
> +/* Expected results when saturation occurs. */
> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000,
> + 0x80000000, 0x80000000 };
> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000,
> + 0x8000000000000000 };
> +
> +#include "vqdmlXl.inc"
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
@ 2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 16:52 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +
> +/* Expected values of cumulative_saturation flag when multiplication
> + saturates. */
Note: Saturation (and hence QC bit-setting) can also occur with the
accumulation.
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC).
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
@ 2015-01-16 17:15 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-16 17:15 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:17, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> (Set_Neon_Cumulative_Sat): Add parameter.
> (__set_neon_cumulative_sat): Support new parameter.
> * gcc.target/aarch64/advsimd-intrinsics/binary_sat_op.inc
> (TEST_BINARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
> argument.
> * gcc.target/aarch64/advsimd-intrinsics/unary_sat_op.inc
> (TEST_UNARY_SAT_OP1): Call Set_Neon_Cumulative_Sat with new
> argument.
OK, provided no regressions and no new fails for aarch64, aarch64_be and arm.
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
@ 2015-01-16 17:17 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-16 17:17 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h (CHECK):
> Add trace.
> (CHECK_FP): Likewise.
> (CHECK_CUMULATIVE_SAT): Likewise.
OK, provided no regressions and no new fails for aarch64, aarch64_be and arm.
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-16 16:23 ` Christophe Lyon
@ 2015-01-16 17:20 ` Marcus Shawcroft
2015-01-16 17:59 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-16 17:20 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 16 January 2015 at 16:21, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> My existing tests only cover armv7 so far.
> I do plan to expand them once they are all in GCC.
>
>> Otherwise, they look good to me(but I can't approve it).
>>
>> Tejas.
>>
OK provided, as per the previous couple, that we don;t regression or
introduce new fails on aarch64[_be] or aarch32.
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests.
2015-01-16 16:31 ` Christophe Lyon
@ 2015-01-16 17:22 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-16 17:22 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 16 January 2015 at 16:23, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 15:09, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: New file.
>> Hmm.. again, I don't see vld1<q>_lane_f64?
>
> Same answer: unless I am mistaken it isn't supported on armv7, and
> indeed the tests need to be expanded.
>
>>> +#ifndef __CC_ARM
>>> + /* Check runtime assertions. With RVCT, the check is performed at
>>> + compile-time */
>>> + // TEST_VLD1_LANE(, int, s, 64, 1, 1);
>>> +#endif
>>> +
>>
>> Does this belong in this patch?
> Good catch!
> The original testsuite uses RVCT features not present in GCC, and I
> forgot to remove this chunk.
>
>> Otherwise, it looks good to me(I cannot approve though).
OK with that hunk dropped, provided no new fails on aarch64[_be] and arm.
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
@ 2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 17:26 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
> new file mode 100644
> index 0000000..fd885dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc
> @@ -0,0 +1,59 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* vector_res = vqdmlxl_n(vector, vector3, val),
> + then store the result. */
> +#define TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector3, T1, W2, N), \
> + V); \
> + vst1q_##T2##W(VECT_VAR(result, T1, W, N), \
> + VECT_VAR(vector_res, T1, W, N)); \
> + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> +#define TEST_VQDMLXL_N(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \
> + TEST_VQDMLXL_N1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector3, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> +
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector3, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> +
> + VDUP(vector3, , int, s, 16, 4, 0x55);
> + VDUP(vector3, , int, s, 32, 2, 0x55);
> +
> + /* Choose val arbitrarily. */
> + TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x22, expected_cumulative_sat, "");
> + TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x33, expected_cumulative_sat, "");
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> +
> +#define TEST_MSG2 "(check mul cumulative saturation)"
> + VDUP(vector3, , int, s, 16, 4, 0x8000);
> + VDUP(vector3, , int, s, 32, 2, 0x80000000);
> +
> + TEST_VQDMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2);
> + TEST_VQDMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c
> new file mode 100644
> index 0000000..b84bca3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c
> @@ -0,0 +1,27 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vqdmlal_n
> +#define TEST_MSG "VQDMLAL_N"
> +
> +/* Expected values of cumulative_saturation flag. */
> +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
> +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x1684, 0x1685, 0x1686, 0x1687 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x21ce, 0x21cf };
> +
> +/* Expected values of cumulative_saturation flag when saturation
> + occurs. */
> +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
> +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
> +
> +/* Expected results when saturation occurs. */
> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffef, 0x7ffffff0,
> + 0x7ffffff1, 0x7ffffff2 };
> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffef,
> + 0x7ffffffffffffff0 };
> +
> +#include "vqdmlXl_n.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c
> new file mode 100644
> index 0000000..ff8d9d3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c
> @@ -0,0 +1,29 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vqdmlsl_n
> +#define TEST_MSG "VQDMLSL_N"
> +
> +/* Expected values of cumulative_saturation flag. */
> +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0;
> +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0;
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffe95c, 0xffffe95d,
> + 0xffffe95e, 0xffffe95f };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffde12,
> + 0xffffffffffffde13 };
> +
> +/* Expected values of cumulative_saturation flag when saturation
> + occurs. */
> +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 1;
> +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 1;
> +
> +/* Expected results when saturation occurs. */
> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x80000000, 0x80000000,
> + 0x80000000, 0x80000000 };
> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x8000000000000000,
> + 0x8000000000000000 };
> +
> +#include "vqdmlXl_n.inc"
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
@ 2015-01-16 17:54 ` Tejas Belagod
2015-01-16 18:02 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 17:54 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
> new file mode 100644
> index 0000000..7ac2ed4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
> @@ -0,0 +1,67 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* Basic test: y=OP(x), then store the result. */
> +#define TEST_VPADD1(INSN, T1, T2, W, N) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector, T1, W, N)); \
> + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
> + VECT_VAR(vector_res, T1, W, N))
> +
> +#define TEST_VPADD(INSN, T1, T2, W, N) \
> + TEST_VPADD1(INSN, T1, T2, W, N) \
> +
> + /* No need for 64 bits variants. */
> + DECL_VARIABLE(vector, int, 8, 8);
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 8, 8);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> + DECL_VARIABLE(vector, float, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 8, 8);
> + DECL_VARIABLE(vector_res, int, 16, 4);
> + DECL_VARIABLE(vector_res, int, 32, 2);
> + DECL_VARIABLE(vector_res, uint, 8, 8);
> + DECL_VARIABLE(vector_res, uint, 16, 4);
> + DECL_VARIABLE(vector_res, uint, 32, 2);
> + DECL_VARIABLE(vector_res, float, 32, 2);
> +
> + clean_results ();
> +
> + /* Initialize input "vector" from "buffer". */
> + VLOAD(vector, buffer, , int, s, 8, 8);
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, , uint, u, 8, 8);
> + VLOAD(vector, buffer, , uint, u, 16, 4);
> + VLOAD(vector, buffer, , uint, u, 32, 2);
> + VLOAD(vector, buffer, , float, f, 32, 2);
> +
> + /* Apply a unary operator named INSN_NAME. */
Unary op?
> + TEST_VPADD(INSN_NAME, int, s, 8, 8);
> + TEST_VPADD(INSN_NAME, int, s, 16, 4);
> + TEST_VPADD(INSN_NAME, int, s, 32, 2);
> + TEST_VPADD(INSN_NAME, uint, u, 8, 8);
> + TEST_VPADD(INSN_NAME, uint, u, 16, 4);
> + TEST_VPADD(INSN_NAME, uint, u, 32, 2);
> + TEST_VPADD(INSN_NAME, float, f, 32, 2);
> +
> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
> new file mode 100644
> index 0000000..5ddfd3d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
> @@ -0,0 +1,19 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vpadd
> +#define TEST_MSG "VPADD"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
> + 0xe1, 0xe5, 0xe9, 0xed };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
> + 0xe1, 0xe5, 0xe9, 0xed };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
> +
> +#include "vpXXX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
> new file mode 100644
> index 0000000..f27a9a9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
> @@ -0,0 +1,20 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +
> +#define INSN_NAME vpmax
> +#define TEST_MSG "VPMAX"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
> + 0xf1, 0xf3, 0xf5, 0xf7 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
> + 0xf1, 0xf3, 0xf5, 0xf7 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
> +
> +#include "vpXXX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
> new file mode 100644
> index 0000000..a7cb696
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
> @@ -0,0 +1,20 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +
> +#define INSN_NAME vpmin
> +#define TEST_MSG "VPMIN"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
> + 0xf0, 0xf2, 0xf4, 0xf6 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
> + 0xf0, 0xf2, 0xf4, 0xf6 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
> +
> +#include "vpXXX.inc"
>
Otherwise LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-16 17:20 ` Marcus Shawcroft
@ 2015-01-16 17:59 ` Christophe Lyon
2015-01-19 13:34 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 17:59 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: Tejas Belagod, gcc-patches
On 16 January 2015 at 18:14, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 16 January 2015 at 16:21, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
>> My existing tests only cover armv7 so far.
>> I do plan to expand them once they are all in GCC.
>>
>>> Otherwise, they look good to me(but I can't approve it).
>>>
>>> Tejas.
>>>
>
> OK provided, as per the previous couple, that we don;t regression or
> introduce new fails on aarch64[_be] or aarch32.
This patch shows failures on aarch64 and aarch64_be for vmax and vmin
when the input is -NaN.
It's a corner case, and my reading of the ARM ARM is that the result
should the same as on aarch32.
I haven't had time to look at it in more details though.
So, not OK?
> /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
2015-01-16 17:54 ` Tejas Belagod
@ 2015-01-16 18:02 ` Christophe Lyon
2015-01-20 15:34 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 18:02 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 18:52, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>> new file mode 100644
>> index 0000000..7ac2ed4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>> @@ -0,0 +1,67 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> + /* Basic test: y=OP(x), then store the result. */
>> +#define TEST_VPADD1(INSN, T1, T2, W, N)
>> \
>> + VECT_VAR(vector_res, T1, W, N) = \
>> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
>> + VECT_VAR(vector, T1, W, N)); \
>> + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
>> + VECT_VAR(vector_res, T1, W, N))
>> +
>> +#define TEST_VPADD(INSN, T1, T2, W, N) \
>> + TEST_VPADD1(INSN, T1, T2, W, N) \
>> +
>> + /* No need for 64 bits variants. */
>> + DECL_VARIABLE(vector, int, 8, 8);
>> + DECL_VARIABLE(vector, int, 16, 4);
>> + DECL_VARIABLE(vector, int, 32, 2);
>> + DECL_VARIABLE(vector, uint, 8, 8);
>> + DECL_VARIABLE(vector, uint, 16, 4);
>> + DECL_VARIABLE(vector, uint, 32, 2);
>> + DECL_VARIABLE(vector, float, 32, 2);
>> +
>> + DECL_VARIABLE(vector_res, int, 8, 8);
>> + DECL_VARIABLE(vector_res, int, 16, 4);
>> + DECL_VARIABLE(vector_res, int, 32, 2);
>> + DECL_VARIABLE(vector_res, uint, 8, 8);
>> + DECL_VARIABLE(vector_res, uint, 16, 4);
>> + DECL_VARIABLE(vector_res, uint, 32, 2);
>> + DECL_VARIABLE(vector_res, float, 32, 2);
>> +
>> + clean_results ();
>> +
>> + /* Initialize input "vector" from "buffer". */
>> + VLOAD(vector, buffer, , int, s, 8, 8);
>> + VLOAD(vector, buffer, , int, s, 16, 4);
>> + VLOAD(vector, buffer, , int, s, 32, 2);
>> + VLOAD(vector, buffer, , uint, u, 8, 8);
>> + VLOAD(vector, buffer, , uint, u, 16, 4);
>> + VLOAD(vector, buffer, , uint, u, 32, 2);
>> + VLOAD(vector, buffer, , float, f, 32, 2);
>> +
>> + /* Apply a unary operator named INSN_NAME. */
>
>
> Unary op?
>
Hmm cut & paste issue. Thanks
>
>> + TEST_VPADD(INSN_NAME, int, s, 8, 8);
>> + TEST_VPADD(INSN_NAME, int, s, 16, 4);
>> + TEST_VPADD(INSN_NAME, int, s, 32, 2);
>> + TEST_VPADD(INSN_NAME, uint, u, 8, 8);
>> + TEST_VPADD(INSN_NAME, uint, u, 16, 4);
>> + TEST_VPADD(INSN_NAME, uint, u, 32, 2);
>> + TEST_VPADD(INSN_NAME, float, f, 32, 2);
>> +
>> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
>> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
>> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
>> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
>> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
>> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
>> +}
>> +
>> +int main (void)
>> +{
>> + FNNAME (INSN_NAME) ();
>> + return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>> new file mode 100644
>> index 0000000..5ddfd3d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>> @@ -0,0 +1,19 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +#define INSN_NAME vpadd
>> +#define TEST_MSG "VPADD"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>> + 0xe1, 0xe5, 0xe9, 0xed };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>> + 0xe1, 0xe5, 0xe9, 0xed };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
>> +
>> +#include "vpXXX.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>> new file mode 100644
>> index 0000000..f27a9a9
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>> @@ -0,0 +1,20 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +
>> +#define INSN_NAME vpmax
>> +#define TEST_MSG "VPMAX"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
>> +
>> +#include "vpXXX.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>> new file mode 100644
>> index 0000000..a7cb696
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>> @@ -0,0 +1,20 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +
>> +#define INSN_NAME vpmin
>> +#define TEST_MSG "VPMIN"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
>> +
>> +#include "vpXXX.inc"
>>
>
> Otherwise LGTM.
>
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
@ 2015-01-16 18:11 ` Tejas Belagod
2015-01-19 14:15 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:11 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +
> +void vsri_extra(void)
> +{
> + /* Test cases with maximum shift amount (this amount is different
> + * from vsli. */
> +
Nit. Comment Formatting. Similarly, few other places.
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc.
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
@ 2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:12 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
> vXXXl.inc.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc
> new file mode 100644
> index 0000000..bd4c8fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc
> @@ -0,0 +1,70 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* Basic test: y=vaddl(x1,x2), then store the result. */
> +#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector2, T1, W, N)); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> +
> +#define TEST_VADDL(INSN, T1, T2, W, W2, N) \
> + TEST_VADDL1(INSN, T1, T2, W, W2, N)
> +
> + DECL_VARIABLE(vector, int, 8, 8);
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 8, 8);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> +
> + DECL_VARIABLE(vector2, int, 8, 8);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector2, uint, 8, 8);
> + DECL_VARIABLE(vector2, uint, 16, 4);
> + DECL_VARIABLE(vector2, uint, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 16, 8);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> + DECL_VARIABLE(vector_res, uint, 16, 8);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + /* Initialize input "vector" from "buffer". */
> + VLOAD(vector, buffer, , int, s, 8, 8);
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, , uint, u, 8, 8);
> + VLOAD(vector, buffer, , uint, u, 16, 4);
> + VLOAD(vector, buffer, , uint, u, 32, 2);
> +
> + /* Choose init value arbitrarily. */
> + VDUP(vector2, , int, s, 8, 8, -13);
> + VDUP(vector2, , int, s, 16, 4, -14);
> + VDUP(vector2, , int, s, 32, 2, -16);
> + VDUP(vector2, , uint, u, 8, 8, 0xf3);
> + VDUP(vector2, , uint, u, 16, 4, 0xfff1);
> + VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
> +
> + /* Execute the tests. */
> + TEST_VADDL(INSN_NAME, int, s, 8, 16, 8);
> + TEST_VADDL(INSN_NAME, int, s, 16, 32, 4);
> + TEST_VADDL(INSN_NAME, int, s, 32, 64, 2);
> + TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8);
> + TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4);
> + TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2);
> +
> + CHECK_RESULTS (TEST_MSG, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
> index 030785d..020d9f8 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddl.c
> @@ -2,6 +2,9 @@
> #include "arm-neon-ref.h"
> #include "compute-ref-data.h"
>
> +#define INSN_NAME vaddl
> +#define TEST_MSG "VADDL"
> +
> /* Expected results. */
> VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> 0x33, 0x33, 0x33, 0x33 };
> @@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> 0x33333333, 0x33333333 };
>
> -#define INSN_NAME vaddl
> -#define TEST_MSG "VADDL"
> -
> -#define FNNAME1(NAME) exec_ ## NAME
> -#define FNNAME(NAME) FNNAME1(NAME)
> -
> -void FNNAME (INSN_NAME) (void)
> -{
> - /* Basic test: y=vaddl(x1,x2), then store the result. */
> -#define TEST_VADDL1(INSN, T1, T2, W, W2, N) \
> - VECT_VAR(vector_res, T1, W2, N) = \
> - INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
> - VECT_VAR(vector2, T1, W, N)); \
> - vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> -
> -#define TEST_VADDL(INSN, T1, T2, W, W2, N) \
> - TEST_VADDL1(INSN, T1, T2, W, W2, N)
> -
> - DECL_VARIABLE(vector, int, 8, 8);
> - DECL_VARIABLE(vector, int, 16, 4);
> - DECL_VARIABLE(vector, int, 32, 2);
> - DECL_VARIABLE(vector, uint, 8, 8);
> - DECL_VARIABLE(vector, uint, 16, 4);
> - DECL_VARIABLE(vector, uint, 32, 2);
> -
> - DECL_VARIABLE(vector2, int, 8, 8);
> - DECL_VARIABLE(vector2, int, 16, 4);
> - DECL_VARIABLE(vector2, int, 32, 2);
> - DECL_VARIABLE(vector2, uint, 8, 8);
> - DECL_VARIABLE(vector2, uint, 16, 4);
> - DECL_VARIABLE(vector2, uint, 32, 2);
> -
> - DECL_VARIABLE(vector_res, int, 16, 8);
> - DECL_VARIABLE(vector_res, int, 32, 4);
> - DECL_VARIABLE(vector_res, int, 64, 2);
> - DECL_VARIABLE(vector_res, uint, 16, 8);
> - DECL_VARIABLE(vector_res, uint, 32, 4);
> - DECL_VARIABLE(vector_res, uint, 64, 2);
> -
> - clean_results ();
> -
> - /* Initialize input "vector" from "buffer". */
> - VLOAD(vector, buffer, , int, s, 8, 8);
> - VLOAD(vector, buffer, , int, s, 16, 4);
> - VLOAD(vector, buffer, , int, s, 32, 2);
> - VLOAD(vector, buffer, , uint, u, 8, 8);
> - VLOAD(vector, buffer, , uint, u, 16, 4);
> - VLOAD(vector, buffer, , uint, u, 32, 2);
> -
> - /* Choose init value arbitrarily. */
> - VDUP(vector2, , int, s, 8, 8, -13);
> - VDUP(vector2, , int, s, 16, 4, -14);
> - VDUP(vector2, , int, s, 32, 2, -16);
> - VDUP(vector2, , uint, u, 8, 8, 0xf3);
> - VDUP(vector2, , uint, u, 16, 4, 0xfff1);
> - VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
> -
> - /* Execute the tests. */
> - TEST_VADDL(INSN_NAME, int, s, 8, 16, 8);
> - TEST_VADDL(INSN_NAME, int, s, 16, 32, 4);
> - TEST_VADDL(INSN_NAME, int, s, 32, 64, 2);
> - TEST_VADDL(INSN_NAME, uint, u, 8, 16, 8);
> - TEST_VADDL(INSN_NAME, uint, u, 16, 32, 4);
> - TEST_VADDL(INSN_NAME, uint, u, 32, 64, 2);
> -
> - CHECK_RESULTS (TEST_MSG, "");
> -}
> -
> -int main (void)
> -{
> - FNNAME (INSN_NAME) ();
> - return 0;
> -}
> +#include "vXXXl.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c
> new file mode 100644
> index 0000000..b765b2b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubl.c
> @@ -0,0 +1,48 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vsubl
> +#define TEST_MSG "VSUBL"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
> + 0x1, 0x2, 0x3, 0x4 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
> + 0x1, 0x2, 0x3, 0x4 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x1, 0x2 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x0, 0x1 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +#include "vXXXl.inc"
> --
> 2.1.0
>
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.
2015-01-16 16:06 ` Tejas Belagod
@ 2015-01-16 18:12 ` Christophe Lyon
2015-01-19 13:52 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 18:12 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 16:58, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
>> vshuffle.inc.
>> * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
>> vshuffle.inc.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> new file mode 100644
>> index 0000000..928f338
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc
>> @@ -0,0 +1,139 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> + /* In this case, output variables are arrays of vectors. */
>> +#define DECL_VSHUFFLE(T1, W, N)
>> \
>> + VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
>> \
>> + VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
>> +
>> + /* We need to use a temporary result buffer (result_bis), because
>> + the one used for other tests is not large enough. A subset of the
>> + result data is moved from result_bis to result, and it is this
>> + subset which is used to check the actual behaviour. The next
>> + macro enables to move another chunk of data from result_bis to
>> + result. */
>> +#define TEST_VSHUFFLE(INSN, Q, T1, T2, W, N) \
>> + VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
>> + INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
>> + VECT_VAR(vector2, T1, W, N)); \
>> + vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
>> + VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
>> + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
>> + sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> + /* Overwrite "result" with the contents of "result_bis"[X]. */
>> +#define TEST_EXTRA_CHUNK(T1, W, N, X) \
>> + memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W,
>> N)[X*N]), \
>> + sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> + DECL_VARIABLE_ALL_VARIANTS(vector1);
>> + DECL_VARIABLE_ALL_VARIANTS(vector2);
>> +
>> + /* We don't need 64 bits variants. */
>> +#define DECL_ALL_VSHUFFLE() \
>> + DECL_VSHUFFLE(int, 8, 8); \
>> + DECL_VSHUFFLE(int, 16, 4); \
>> + DECL_VSHUFFLE(int, 32, 2); \
>> + DECL_VSHUFFLE(uint, 8, 8); \
>> + DECL_VSHUFFLE(uint, 16, 4); \
>> + DECL_VSHUFFLE(uint, 32, 2); \
>> + DECL_VSHUFFLE(poly, 8, 8); \
>> + DECL_VSHUFFLE(poly, 16, 4); \
>> + DECL_VSHUFFLE(float, 32, 2); \
>> + DECL_VSHUFFLE(int, 8, 16); \
>> + DECL_VSHUFFLE(int, 16, 8); \
>> + DECL_VSHUFFLE(int, 32, 4); \
>> + DECL_VSHUFFLE(uint, 8, 16); \
>> + DECL_VSHUFFLE(uint, 16, 8); \
>> + DECL_VSHUFFLE(uint, 32, 4); \
>> + DECL_VSHUFFLE(poly, 8, 16); \
>> + DECL_VSHUFFLE(poly, 16, 8); \
>> + DECL_VSHUFFLE(float, 32, 4)
>> +
>> + DECL_ALL_VSHUFFLE();
>> +
>> + /* Initialize input "vector" from "buffer". */
>> + TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
>> + VLOAD(vector1, buffer, , float, f, 32, 2);
>> + VLOAD(vector1, buffer, q, float, f, 32, 4);
>> +
>> + /* Choose arbitrary initialization values. */
>> + VDUP(vector2, , int, s, 8, 8, 0x11);
>> + VDUP(vector2, , int, s, 16, 4, 0x22);
>> + VDUP(vector2, , int, s, 32, 2, 0x33);
>> + VDUP(vector2, , uint, u, 8, 8, 0x55);
>> + VDUP(vector2, , uint, u, 16, 4, 0x66);
>> + VDUP(vector2, , uint, u, 32, 2, 0x77);
>> + VDUP(vector2, , poly, p, 8, 8, 0x55);
>> + VDUP(vector2, , poly, p, 16, 4, 0x66);
>> + VDUP(vector2, , float, f, 32, 2, 33.6f);
>> +
>> + VDUP(vector2, q, int, s, 8, 16, 0x11);
>> + VDUP(vector2, q, int, s, 16, 8, 0x22);
>> + VDUP(vector2, q, int, s, 32, 4, 0x33);
>> + VDUP(vector2, q, uint, u, 8, 16, 0x55);
>> + VDUP(vector2, q, uint, u, 16, 8, 0x66);
>> + VDUP(vector2, q, uint, u, 32, 4, 0x77);
>> + VDUP(vector2, q, poly, p, 8, 16, 0x55);
>> + VDUP(vector2, q, poly, p, 16, 8, 0x66);
>> + VDUP(vector2, q, float, f, 32, 4, 33.8f);
>> +
>> +#define TEST_ALL_VSHUFFLE(INSN) \
>> + TEST_VSHUFFLE(INSN, , int, s, 8, 8); \
>> + TEST_VSHUFFLE(INSN, , int, s, 16, 4); \
>> + TEST_VSHUFFLE(INSN, , int, s, 32, 2); \
>> + TEST_VSHUFFLE(INSN, , uint, u, 8, 8); \
>> + TEST_VSHUFFLE(INSN, , uint, u, 16, 4); \
>> + TEST_VSHUFFLE(INSN, , uint, u, 32, 2); \
>> + TEST_VSHUFFLE(INSN, , poly, p, 8, 8); \
>> + TEST_VSHUFFLE(INSN, , poly, p, 16, 4); \
>> + TEST_VSHUFFLE(INSN, , float, f, 32, 2); \
>> + TEST_VSHUFFLE(INSN, q, int, s, 8, 16); \
>> + TEST_VSHUFFLE(INSN, q, int, s, 16, 8); \
>> + TEST_VSHUFFLE(INSN, q, int, s, 32, 4); \
>> + TEST_VSHUFFLE(INSN, q, uint, u, 8, 16); \
>> + TEST_VSHUFFLE(INSN, q, uint, u, 16, 8); \
>> + TEST_VSHUFFLE(INSN, q, uint, u, 32, 4); \
>> + TEST_VSHUFFLE(INSN, q, poly, p, 8, 16); \
>> + TEST_VSHUFFLE(INSN, q, poly, p, 16, 8); \
>> + TEST_VSHUFFLE(INSN, q, float, f, 32, 4)
>> +
>> +#define TEST_ALL_EXTRA_CHUNKS() \
>> + TEST_EXTRA_CHUNK(int, 8, 8, 1); \
>> + TEST_EXTRA_CHUNK(int, 16, 4, 1); \
>> + TEST_EXTRA_CHUNK(int, 32, 2, 1); \
>> + TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
>> + TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
>> + TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
>> + TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
>> + TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
>> + TEST_EXTRA_CHUNK(float, 32, 2, 1); \
>> + TEST_EXTRA_CHUNK(int, 8, 16, 1); \
>> + TEST_EXTRA_CHUNK(int, 16, 8, 1); \
>> + TEST_EXTRA_CHUNK(int, 32, 4, 1); \
>> + TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
>> + TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
>> + TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
>> + TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
>> + TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
>> + TEST_EXTRA_CHUNK(float, 32, 4, 1)
>> +
>> + clean_results ();
>> +
>> + /* Execute the tests. */
>> + TEST_ALL_VSHUFFLE(INSN_NAME);
>> +
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
>> +
>> + TEST_ALL_EXTRA_CHUNKS();
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
>> +}
>> +
>> +int main (void)
>> +{
>> + FNNAME (INSN_NAME) ();
>> +
>> + return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
>> new file mode 100644
>> index 0000000..be18c0f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn.c
>> @@ -0,0 +1,93 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results splitted in several chunks. */
>> +/* Chunk 0. */
>> +VECT_VAR_DECL(expected0,int,8,8) [] = { 0xf0, 0xf1, 0x11, 0x11,
>> + 0xf2, 0xf3, 0x11, 0x11 };
>> +VECT_VAR_DECL(expected0,int,16,4) [] = { 0xfff0, 0xfff1, 0x22, 0x22 };
>> +VECT_VAR_DECL(expected0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected0,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected0,uint,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
>> + 0xf2, 0xf3, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected0,uint,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected0,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf1, 0x55, 0x55,
>> + 0xf2, 0xf3, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 };
>> +VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf1, 0x11, 0x11,
>> + 0xf2, 0xf3, 0x11, 0x11,
>> + 0xf4, 0xf5, 0x11, 0x11,
>> + 0xf6, 0xf7, 0x11, 0x11 };
>> +VECT_VAR_DECL(expected0,int,16,8) [] = { 0xfff0, 0xfff1, 0x22, 0x22,
>> + 0xfff2, 0xfff3, 0x22, 0x22 };
>> +VECT_VAR_DECL(expected0,int,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x33,
>> 0x33 };
>> +VECT_VAR_DECL(expected0,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected0,uint,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
>> + 0xf2, 0xf3, 0x55, 0x55,
>> + 0xf4, 0xf5, 0x55, 0x55,
>> + 0xf6, 0xf7, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected0,uint,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
>> + 0xfff2, 0xfff3, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0x77,
>> 0x77 };
>> +VECT_VAR_DECL(expected0,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf1, 0x55, 0x55,
>> + 0xf2, 0xf3, 0x55, 0x55,
>> + 0xf4, 0xf5, 0x55, 0x55,
>> + 0xf6, 0xf7, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff1, 0x66, 0x66,
>> + 0xfff2, 0xfff3, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
>> + 0x42073333, 0x42073333 };
>> +
>> +/* Chunk 1. */
>> +VECT_VAR_DECL(expected1,int,8,8) [] = { 0xf4, 0xf5, 0x11, 0x11,
>> + 0xf6, 0xf7, 0x11, 0x11 };
>> +VECT_VAR_DECL(expected1,int,16,4) [] = { 0xfff2, 0xfff3, 0x22, 0x22 };
>> +VECT_VAR_DECL(expected1,int,32,2) [] = { 0x33, 0x33 };
>> +VECT_VAR_DECL(expected1,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected1,uint,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
>> + 0xf6, 0xf7, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected1,uint,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected1,uint,32,2) [] = { 0x77, 0x77 };
>> +VECT_VAR_DECL(expected1,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf4, 0xf5, 0x55, 0x55,
>> + 0xf6, 0xf7, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff2, 0xfff3, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0x42066666, 0x42066666 };
>> +VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf8, 0xf9, 0x11, 0x11,
>> + 0xfa, 0xfb, 0x11, 0x11,
>> + 0xfc, 0xfd, 0x11, 0x11,
>> + 0xfe, 0xff, 0x11, 0x11 };
>> +VECT_VAR_DECL(expected1,int,16,8) [] = { 0xfff4, 0xfff5, 0x22, 0x22,
>> + 0xfff6, 0xfff7, 0x22, 0x22 };
>> +VECT_VAR_DECL(expected1,int,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x33,
>> 0x33 };
>> +VECT_VAR_DECL(expected1,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected1,uint,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
>> + 0xfa, 0xfb, 0x55, 0x55,
>> + 0xfc, 0xfd, 0x55, 0x55,
>> + 0xfe, 0xff, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected1,uint,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
>> + 0xfff6, 0xfff7, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected1,uint,32,4) [] = { 0xfffffff2, 0xfffffff3, 0x77,
>> 0x77 };
>> +VECT_VAR_DECL(expected1,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf8, 0xf9, 0x55, 0x55,
>> + 0xfa, 0xfb, 0x55, 0x55,
>> + 0xfc, 0xfd, 0x55, 0x55,
>> + 0xfe, 0xff, 0x55, 0x55 };
>> +VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff4, 0xfff5, 0x66, 0x66,
>> + 0xfff6, 0xfff7, 0x66, 0x66 };
>> +VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1600000, 0xc1500000,
>> + 0x42073333, 0x42073333 };
>> +
>> +#define INSN_NAME vtrn
>> +#define TEST_MSG "VTRN/VTRNQ"
>> +
>> +#include "vshuffle.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
>> index 53f875e..ec9ded3 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp.c
>> @@ -99,147 +99,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0x66, 0x66,
>> 0x66, 0x66,
>> VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0x42073333, 0x42073333,
>> 0x42073333, 0x42073333 };
>>
>> -#ifndef INSN_NAME
>> #define INSN_NAME vuzp
>> #define TEST_MSG "VUZP/VUZPQ"
>> -#endif
>>
>> -#define FNNAME1(NAME) exec_ ## NAME
>> -#define FNNAME(NAME) FNNAME1(NAME)
>> -
>> -void FNNAME (INSN_NAME) (void)
>> -{
>> - /* In this case, output variables are arrays of vectors. */
>> -#define DECL_VUZP(T1, W, N) \
>> - VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
>> \
>> - VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
>> -
>> - /* We need to use a temporary result buffer (result_bis), because
>> - the one used for other tests is not large enough. A subset of the
>> - result data is moved from result_bis to result, and it is this
>> - subset which is used to check the actual behaviour. The next
>> - macro enables to move another chunk of data from result_bis to
>> - result. */
>> -#define TEST_VUZP(INSN, Q, T1, T2, W, N) \
>> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
>> - INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
>> - VECT_VAR(vector2, T1, W, N)); \
>> - vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
>> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
>> - memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
>> - sizeof(VECT_VAR(result, T1, W, N)));
>> -
>> - /* Overwrite "result" with the contents of "result_bis"[X]. */
>> -#define TEST_EXTRA_CHUNK(T1, W, N, X) \
>> - memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W,
>> N)[X*N]), \
>> - sizeof(VECT_VAR(result, T1, W, N)));
>> -
>> - DECL_VARIABLE_ALL_VARIANTS(vector1);
>> - DECL_VARIABLE_ALL_VARIANTS(vector2);
>> -
>> - /* We don't need 64 bits variants. */
>> -#define DECL_ALL_VUZP() \
>> - DECL_VUZP(int, 8, 8); \
>> - DECL_VUZP(int, 16, 4); \
>> - DECL_VUZP(int, 32, 2); \
>> - DECL_VUZP(uint, 8, 8); \
>> - DECL_VUZP(uint, 16, 4); \
>> - DECL_VUZP(uint, 32, 2); \
>> - DECL_VUZP(poly, 8, 8); \
>> - DECL_VUZP(poly, 16, 4); \
>> - DECL_VUZP(float, 32, 2); \
>> - DECL_VUZP(int, 8, 16); \
>> - DECL_VUZP(int, 16, 8); \
>> - DECL_VUZP(int, 32, 4); \
>> - DECL_VUZP(uint, 8, 16); \
>> - DECL_VUZP(uint, 16, 8); \
>> - DECL_VUZP(uint, 32, 4); \
>> - DECL_VUZP(poly, 8, 16); \
>> - DECL_VUZP(poly, 16, 8); \
>> - DECL_VUZP(float, 32, 4)
>> -
>> - DECL_ALL_VUZP();
>> -
>> - /* Initialize input "vector" from "buffer". */
>> - TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
>> - VLOAD(vector1, buffer, , float, f, 32, 2);
>> - VLOAD(vector1, buffer, q, float, f, 32, 4);
>> -
>> - /* Choose arbitrary initialization values. */
>> - VDUP(vector2, , int, s, 8, 8, 0x11);
>> - VDUP(vector2, , int, s, 16, 4, 0x22);
>> - VDUP(vector2, , int, s, 32, 2, 0x33);
>> - VDUP(vector2, , uint, u, 8, 8, 0x55);
>> - VDUP(vector2, , uint, u, 16, 4, 0x66);
>> - VDUP(vector2, , uint, u, 32, 2, 0x77);
>> - VDUP(vector2, , poly, p, 8, 8, 0x55);
>> - VDUP(vector2, , poly, p, 16, 4, 0x66);
>> - VDUP(vector2, , float, f, 32, 2, 33.6f);
>> -
>> - VDUP(vector2, q, int, s, 8, 16, 0x11);
>> - VDUP(vector2, q, int, s, 16, 8, 0x22);
>> - VDUP(vector2, q, int, s, 32, 4, 0x33);
>> - VDUP(vector2, q, uint, u, 8, 16, 0x55);
>> - VDUP(vector2, q, uint, u, 16, 8, 0x66);
>> - VDUP(vector2, q, uint, u, 32, 4, 0x77);
>> - VDUP(vector2, q, poly, p, 8, 16, 0x55);
>> - VDUP(vector2, q, poly, p, 16, 8, 0x66);
>> - VDUP(vector2, q, float, f, 32, 4, 33.8f);
>> -
>> -#define TEST_ALL_VUZP(INSN) \
>> - TEST_VUZP(INSN, , int, s, 8, 8); \
>> - TEST_VUZP(INSN, , int, s, 16, 4); \
>> - TEST_VUZP(INSN, , int, s, 32, 2); \
>> - TEST_VUZP(INSN, , uint, u, 8, 8); \
>> - TEST_VUZP(INSN, , uint, u, 16, 4); \
>> - TEST_VUZP(INSN, , uint, u, 32, 2); \
>> - TEST_VUZP(INSN, , poly, p, 8, 8); \
>> - TEST_VUZP(INSN, , poly, p, 16, 4); \
>> - TEST_VUZP(INSN, , float, f, 32, 2); \
>> - TEST_VUZP(INSN, q, int, s, 8, 16); \
>> - TEST_VUZP(INSN, q, int, s, 16, 8); \
>> - TEST_VUZP(INSN, q, int, s, 32, 4); \
>> - TEST_VUZP(INSN, q, uint, u, 8, 16); \
>> - TEST_VUZP(INSN, q, uint, u, 16, 8); \
>> - TEST_VUZP(INSN, q, uint, u, 32, 4); \
>> - TEST_VUZP(INSN, q, poly, p, 8, 16); \
>> - TEST_VUZP(INSN, q, poly, p, 16, 8); \
>> - TEST_VUZP(INSN, q, float, f, 32, 4)
>> -
>> -#define TEST_ALL_EXTRA_CHUNKS() \
>> - TEST_EXTRA_CHUNK(int, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(int, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(int, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(float, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(int, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(int, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(int, 32, 4, 1); \
>> - TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
>> - TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(float, 32, 4, 1)
>> -
>> - clean_results ();
>> -
>> - /* Execute the tests. */
>> - TEST_ALL_VUZP(INSN_NAME);
>> -
>> - CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
>> -
>> - TEST_ALL_EXTRA_CHUNKS();
>> - CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
>> -}
>> -
>> -int main (void)
>> -{
>> - FNNAME (INSN_NAME) ();
>> -
>> - return 0;
>> -}
>> +#include "vshuffle.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
>> index a1f1eee..05faa8a 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip.c
>> @@ -97,147 +97,7 @@ VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff2,
>> 0xfff6, 0x66, 0x66,
>> VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1500000,
>> 0x42073333, 0x42073333 };
>>
>> -#ifndef INSN_NAME
>> #define INSN_NAME vzip
>> #define TEST_MSG "VZIP/VZIPQ"
>> -#endif
>>
>> -#define FNNAME1(NAME) exec_ ## NAME
>> -#define FNNAME(NAME) FNNAME1(NAME)
>> -
>> -void FNNAME (INSN_NAME) (void)
>> -{
>> - /* In this case, output variables are arrays of vectors. */
>> -#define DECL_VZIP(T1, W, N) \
>> - VECT_ARRAY_TYPE(T1, W, N, 2) VECT_ARRAY_VAR(result_vec, T1, W, N, 2);
>> \
>> - VECT_VAR_DECL(result_bis, T1, W, N)[2 * N]
>> -
>> - /* We need to use a temporary result buffer (result_bis), because
>> - the one used for other tests is not large enough. A subset of the
>> - result data is moved from result_bis to result, and it is this
>> - subset which is used to check the actual behaviour. The next
>> - macro enables to move another chunk of data from result_bis to
>> - result. */
>> -#define TEST_VZIP(INSN, Q, T1, T2, W, N) \
>> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2) = \
>> - INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
>> - VECT_VAR(vector2, T1, W, N)); \
>> - vst2##Q##_##T2##W(VECT_VAR(result_bis, T1, W, N), \
>> - VECT_ARRAY_VAR(result_vec, T1, W, N, 2)); \
>> - memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis, T1, W, N), \
>> - sizeof(VECT_VAR(result, T1, W, N)));
>> -
>> - /* Overwrite "result" with the contents of "result_bis"[X]. */
>> -#define TEST_EXTRA_CHUNK(T1, W, N, X) \
>> - memcpy(VECT_VAR(result, T1, W, N), &(VECT_VAR(result_bis, T1, W,
>> N)[X*N]), \
>> - sizeof(VECT_VAR(result, T1, W, N)));
>> -
>> - DECL_VARIABLE_ALL_VARIANTS(vector1);
>> - DECL_VARIABLE_ALL_VARIANTS(vector2);
>> -
>> - /* We don't need 64 bits variants. */
>> -#define DECL_ALL_VZIP() \
>> - DECL_VZIP(int, 8, 8); \
>> - DECL_VZIP(int, 16, 4); \
>> - DECL_VZIP(int, 32, 2); \
>> - DECL_VZIP(uint, 8, 8); \
>> - DECL_VZIP(uint, 16, 4); \
>> - DECL_VZIP(uint, 32, 2); \
>> - DECL_VZIP(poly, 8, 8); \
>> - DECL_VZIP(poly, 16, 4); \
>> - DECL_VZIP(float, 32, 2); \
>> - DECL_VZIP(int, 8, 16); \
>> - DECL_VZIP(int, 16, 8); \
>> - DECL_VZIP(int, 32, 4); \
>> - DECL_VZIP(uint, 8, 16); \
>> - DECL_VZIP(uint, 16, 8); \
>> - DECL_VZIP(uint, 32, 4); \
>> - DECL_VZIP(poly, 8, 16); \
>> - DECL_VZIP(poly, 16, 8); \
>> - DECL_VZIP(float, 32, 4)
>> -
>> - DECL_ALL_VZIP();
>> -
>> - /* Initialize input "vector" from "buffer". */
>> - TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector1, buffer);
>> - VLOAD(vector1, buffer, , float, f, 32, 2);
>> - VLOAD(vector1, buffer, q, float, f, 32, 4);
>> -
>> - /* Choose arbitrary initialization values. */
>> - VDUP(vector2, , int, s, 8, 8, 0x11);
>> - VDUP(vector2, , int, s, 16, 4, 0x22);
>> - VDUP(vector2, , int, s, 32, 2, 0x33);
>> - VDUP(vector2, , uint, u, 8, 8, 0x55);
>> - VDUP(vector2, , uint, u, 16, 4, 0x66);
>> - VDUP(vector2, , uint, u, 32, 2, 0x77);
>> - VDUP(vector2, , poly, p, 8, 8, 0x55);
>> - VDUP(vector2, , poly, p, 16, 4, 0x66);
>> - VDUP(vector2, , float, f, 32, 2, 33.6f);
>> -
>> - VDUP(vector2, q, int, s, 8, 16, 0x11);
>> - VDUP(vector2, q, int, s, 16, 8, 0x22);
>> - VDUP(vector2, q, int, s, 32, 4, 0x33);
>> - VDUP(vector2, q, uint, u, 8, 16, 0x55);
>> - VDUP(vector2, q, uint, u, 16, 8, 0x66);
>> - VDUP(vector2, q, uint, u, 32, 4, 0x77);
>> - VDUP(vector2, q, poly, p, 8, 16, 0x55);
>> - VDUP(vector2, q, poly, p, 16, 8, 0x66);
>> - VDUP(vector2, q, float, f, 32, 4, 33.8f);
>> -
>> -#define TEST_ALL_VZIP(INSN) \
>> - TEST_VZIP(INSN, , int, s, 8, 8); \
>> - TEST_VZIP(INSN, , int, s, 16, 4); \
>> - TEST_VZIP(INSN, , int, s, 32, 2); \
>> - TEST_VZIP(INSN, , uint, u, 8, 8); \
>> - TEST_VZIP(INSN, , uint, u, 16, 4); \
>> - TEST_VZIP(INSN, , uint, u, 32, 2); \
>> - TEST_VZIP(INSN, , poly, p, 8, 8); \
>> - TEST_VZIP(INSN, , poly, p, 16, 4); \
>> - TEST_VZIP(INSN, , float, f, 32, 2); \
>> - TEST_VZIP(INSN, q, int, s, 8, 16); \
>> - TEST_VZIP(INSN, q, int, s, 16, 8); \
>> - TEST_VZIP(INSN, q, int, s, 32, 4); \
>> - TEST_VZIP(INSN, q, uint, u, 8, 16); \
>> - TEST_VZIP(INSN, q, uint, u, 16, 8); \
>> - TEST_VZIP(INSN, q, uint, u, 32, 4); \
>> - TEST_VZIP(INSN, q, poly, p, 8, 16); \
>> - TEST_VZIP(INSN, q, poly, p, 16, 8); \
>> - TEST_VZIP(INSN, q, float, f, 32, 4)
>> -
>> -#define TEST_ALL_EXTRA_CHUNKS() \
>> - TEST_EXTRA_CHUNK(int, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(int, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(int, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(uint, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(uint, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(uint, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(poly, 8, 8, 1); \
>> - TEST_EXTRA_CHUNK(poly, 16, 4, 1); \
>> - TEST_EXTRA_CHUNK(float, 32, 2, 1); \
>> - TEST_EXTRA_CHUNK(int, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(int, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(int, 32, 4, 1); \
>> - TEST_EXTRA_CHUNK(uint, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(uint, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(uint, 32, 4, 1); \
>> - TEST_EXTRA_CHUNK(poly, 8, 16, 1); \
>> - TEST_EXTRA_CHUNK(poly, 16, 8, 1); \
>> - TEST_EXTRA_CHUNK(float, 32, 4, 1)
>> -
>> - clean_results ();
>> -
>> - /* Execute the tests. */
>> - TEST_ALL_VZIP(INSN_NAME);
>> -
>> - CHECK_RESULTS_NAMED (TEST_MSG, expected0, "(chunk 0)");
>> -
>> - TEST_ALL_EXTRA_CHUNKS();
>> - CHECK_RESULTS_NAMED (TEST_MSG, expected1, "(chunk 1)");
>> -}
>> -
>> -int main (void)
>> -{
>> - FNNAME (INSN_NAME) ();
>> -
>> - return 0;
>> -}
>> +#include "vshuffle.inc"
>> --
>> 2.1.0
>>
>>
>
> LGTM.
>
Thanks, I should mention that the new vtrn test fails on aarch64_be
(like vzip and vuzp), because of pending Alan's patches to fix
aarch64_be load/stores.
So strictly speaking this patch show new fails.
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
@ 2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:16 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
> vXXXw.inc.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc
> new file mode 100644
> index 0000000..c535557
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc
> @@ -0,0 +1,70 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + /* Basic test: y=vaddw(x1,x2), then store the result. */
> +#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
> + VECT_VAR(vector2, T1, W, N)); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> +
> +#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
> + TEST_VADDW1(INSN, T1, T2, W, W2, N)
> +
> + DECL_VARIABLE(vector, int, 16, 8);
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector, int, 64, 2);
> + DECL_VARIABLE(vector, uint, 16, 8);
> + DECL_VARIABLE(vector, uint, 32, 4);
> + DECL_VARIABLE(vector, uint, 64, 2);
> +
> + DECL_VARIABLE(vector2, int, 8, 8);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector2, uint, 8, 8);
> + DECL_VARIABLE(vector2, uint, 16, 4);
> + DECL_VARIABLE(vector2, uint, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 16, 8);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> + DECL_VARIABLE(vector_res, uint, 16, 8);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + /* Initialize input "vector" from "buffer". */
> + VLOAD(vector, buffer, q, int, s, 16, 8);
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, int, s, 64, 2);
> + VLOAD(vector, buffer, q, uint, u, 16, 8);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 64, 2);
> +
> + /* Choose init value arbitrarily. */
> + VDUP(vector2, , int, s, 8, 8, -13);
> + VDUP(vector2, , int, s, 16, 4, -14);
> + VDUP(vector2, , int, s, 32, 2, -16);
> + VDUP(vector2, , uint, u, 8, 8, 0xf3);
> + VDUP(vector2, , uint, u, 16, 4, 0xfff1);
> + VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
> +
> + /* Execute the tests. */
> + TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
> + TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
> + TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
> + TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
> + TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
> + TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
> +
> + CHECK_RESULTS (TEST_MSG, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
> index 95cbb31..27f54f6 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddw.c
> @@ -2,6 +2,9 @@
> #include "arm-neon-ref.h"
> #include "compute-ref-data.h"
>
> +#define INSN_NAME vaddw
> +#define TEST_MSG "VADDW"
> +
> /* Expected results. */
> VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> 0x33, 0x33, 0x33, 0x33 };
> @@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> 0x33333333, 0x33333333 };
>
> -#define INSN_NAME vaddw
> -#define TEST_MSG "VADDW"
> -
> -#define FNNAME1(NAME) exec_ ## NAME
> -#define FNNAME(NAME) FNNAME1(NAME)
> -
> -void FNNAME (INSN_NAME) (void)
> -{
> - /* Basic test: y=vaddw(x1,x2), then store the result. */
> -#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
> - VECT_VAR(vector_res, T1, W2, N) = \
> - INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
> - VECT_VAR(vector2, T1, W, N)); \
> - vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> -
> -#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
> - TEST_VADDW1(INSN, T1, T2, W, W2, N)
> -
> - DECL_VARIABLE(vector, int, 16, 8);
> - DECL_VARIABLE(vector, int, 32, 4);
> - DECL_VARIABLE(vector, int, 64, 2);
> - DECL_VARIABLE(vector, uint, 16, 8);
> - DECL_VARIABLE(vector, uint, 32, 4);
> - DECL_VARIABLE(vector, uint, 64, 2);
> -
> - DECL_VARIABLE(vector2, int, 8, 8);
> - DECL_VARIABLE(vector2, int, 16, 4);
> - DECL_VARIABLE(vector2, int, 32, 2);
> - DECL_VARIABLE(vector2, uint, 8, 8);
> - DECL_VARIABLE(vector2, uint, 16, 4);
> - DECL_VARIABLE(vector2, uint, 32, 2);
> -
> - DECL_VARIABLE(vector_res, int, 16, 8);
> - DECL_VARIABLE(vector_res, int, 32, 4);
> - DECL_VARIABLE(vector_res, int, 64, 2);
> - DECL_VARIABLE(vector_res, uint, 16, 8);
> - DECL_VARIABLE(vector_res, uint, 32, 4);
> - DECL_VARIABLE(vector_res, uint, 64, 2);
> -
> - clean_results ();
> -
> - /* Initialize input "vector" from "buffer". */
> - VLOAD(vector, buffer, q, int, s, 16, 8);
> - VLOAD(vector, buffer, q, int, s, 32, 4);
> - VLOAD(vector, buffer, q, int, s, 64, 2);
> - VLOAD(vector, buffer, q, uint, u, 16, 8);
> - VLOAD(vector, buffer, q, uint, u, 32, 4);
> - VLOAD(vector, buffer, q, uint, u, 64, 2);
> -
> - /* Choose init value arbitrarily. */
> - VDUP(vector2, , int, s, 8, 8, -13);
> - VDUP(vector2, , int, s, 16, 4, -14);
> - VDUP(vector2, , int, s, 32, 2, -16);
> - VDUP(vector2, , uint, u, 8, 8, 0xf3);
> - VDUP(vector2, , uint, u, 16, 4, 0xfff1);
> - VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
> -
> - /* Execute the tests. */
> - TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
> - TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
> - TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
> - TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
> - TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
> - TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
> -
> - CHECK_RESULTS (TEST_MSG, "");
> -}
> -
> -int main (void)
> -{
> - FNNAME (INSN_NAME) ();
> - return 0;
> -}
> +#include "vXXXw.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
> new file mode 100644
> index 0000000..3e8bc98
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
> @@ -0,0 +1,50 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +#define INSN_NAME vsubw
> +#define TEST_MSG "VSUBW"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
> + 0x1, 0x2, 0x3, 0x4 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfefd, 0xfefe, 0xfeff, 0xff00,
> + 0xff01, 0xff02, 0xff03, 0xff04 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffeffff, 0xffff0000,
> + 0xffff0001, 0xffff0002 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffff00000000,
> + 0xffffffff00000001 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
> +#include "vXXXw.inc"
> --
> 2.1.0
>
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-16 15:35 ` Tejas Belagod
@ 2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
0 siblings, 2 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 18:17 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 16:20, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
>> new file mode 100644
>> index 0000000..53cd8f3
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c
>> @@ -0,0 +1,671 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results. */
>> +
>> +/* vld2_dup/chunk 0. */
>> +VECT_VAR_DECL(expected_vld2_0,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_0,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
>> 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld2_0,int,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
>> 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
>> 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000
>> };
>> +VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_0,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld2_0,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld2_0,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>> +/* vld2_dup/chunk 1. */
>> +VECT_VAR_DECL(expected_vld2_1,int,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
>> 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_1,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld2_1,int,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff0,
>> 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1,
>> + 0xf0, 0xf1, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1,
>> + 0xfff0, 0xfff1 };
>> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000
>> };
>> +VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_1,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld2_1,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld2_1,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld3_dup/chunk 0. */
>> +VECT_VAR_DECL(expected_vld3_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
>> + 0xf1, 0xf2, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld3_0,int,16,4) [] = { 0xfff0, 0xfff1,
>> + 0xfff2, 0xfff0 };
>> +VECT_VAR_DECL(expected_vld3_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld3_0,int,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
>> + 0xf1, 0xf2, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,16,4) [] = { 0xfff0, 0xfff1,
>> + 0xfff2, 0xfff0 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0,
>> + 0xf1, 0xf2, 0xf0, 0xf1 };
>> +VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1,
>> + 0xfff2, 0xfff0 };
>> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000
>> };
>> +VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_0,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_0,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_0,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld3_dup/chunk 1. */
>> +VECT_VAR_DECL(expected_vld3_1,int,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
>> + 0xf0, 0xf1, 0xf2, 0xf0 };
>> +VECT_VAR_DECL(expected_vld3_1,int,16,4) [] = { 0xfff1, 0xfff2,
>> + 0xfff0, 0xfff1 };
>> +VECT_VAR_DECL(expected_vld3_1,int,32,2) [] = { 0xfffffff2, 0xfffffff0 };
>> +VECT_VAR_DECL(expected_vld3_1,int,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
>> + 0xf0, 0xf1, 0xf2, 0xf0 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,16,4) [] = { 0xfff1, 0xfff2,
>> + 0xfff0, 0xfff1 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff0 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2,
>> + 0xf0, 0xf1, 0xf2, 0xf0 };
>> +VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2,
>> + 0xfff0, 0xfff1 };
>> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000
>> };
>> +VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_1,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_1,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_1,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld3_dup/chunk 2. */
>> +VECT_VAR_DECL(expected_vld3_2,int,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
>> + 0xf2, 0xf0, 0xf1, 0xf2 };
>> +VECT_VAR_DECL(expected_vld3_2,int,16,4) [] = { 0xfff2, 0xfff0,
>> + 0xfff1, 0xfff2 };
>> +VECT_VAR_DECL(expected_vld3_2,int,32,2) [] = { 0xfffffff1, 0xfffffff2 };
>> +VECT_VAR_DECL(expected_vld3_2,int,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
>> + 0xf2, 0xf0, 0xf1, 0xf2 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,16,4) [] = { 0xfff2, 0xfff0,
>> + 0xfff1, 0xfff2 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1,
>> + 0xf2, 0xf0, 0xf1, 0xf2 };
>> +VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0,
>> + 0xfff1, 0xfff2 };
>> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000
>> };
>> +VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_2,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_2,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld3_2,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld4_dup/chunk 0. */
>> +VECT_VAR_DECL(expected_vld4_0,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_0,int,16,4) [] = { 0xfff0, 0xfff1,
>> + 0xfff2, 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_0,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld4_0,int,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 };
>> +VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000
>> };
>> +VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_0,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_0,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_0,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld4_dup/chunk 1. */
>> +VECT_VAR_DECL(expected_vld4_1,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_1,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_1,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected_vld4_1,int,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000
>> };
>> +VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_1,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_1,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_1,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld4_dup/chunk 2. */
>> +VECT_VAR_DECL(expected_vld4_2,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_2,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_2,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld4_2,int,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 };
>> +VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000
>> };
>> +VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_2,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_2,int,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_2,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +/* vld4_dup/chunk3. */
>> +VECT_VAR_DECL(expected_vld4_3,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_3,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_3,int,32,2) [] = { 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected_vld4_3,int,64,1) [] = { 0xfffffffffffffff3 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 };
>> +VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf0, 0xf1, 0xf2, 0xf3 };
>> +VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2,
>> 0xfff3 };
>> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000
>> };
>> +VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_3,int,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_3,int,64,2) [] = { 0x3333333333333333,
>> 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected_vld4_3,uint,64,2) [] = { 0x3333333333333333,
>> + 0x3333333333333333 };
>> +VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x3333, 0x3333, 0x3333,
>> 0x3333,
>> + 0x3333, 0x3333, 0x3333,
>> 0x3333 };
>> +VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333
>> };
>> +
>> +void exec_vldX_dup (void)
>> +{
>> + /* In this case, input variables are arrays of vectors. */
>> +#define DECL_VLDX_DUP(T1, W, N, X) \
>> + VECT_ARRAY_TYPE(T1, W, N, X) VECT_ARRAY_VAR(vector, T1, W, N, X); \
>> + VECT_VAR_DECL(result_bis_##X, T1, W, N)[X * N]
>> +
>> + /* We need to use a temporary result buffer (result_bis), because
>> + the one used for other tests is not large enough. A subset of the
>> + result data is moved from result_bis to result, and it is this
>> + subset which is used to check the actual behaviour. The next
>> + macro enables to move another chunk of data from result_bis to
>> + result. */
>> +#define TEST_VLDX_DUP(Q, T1, T2, W, N, X) \
>> + VECT_ARRAY_VAR(vector, T1, W, N, X) =
>> \
>> + vld##X##Q##_dup_##T2##W(&VECT_VAR(buffer_dup, T1, W, N)[0]); \
>> + \
>> + vst##X##Q##_##T2##W(VECT_VAR(result_bis_##X, T1, W, N), \
>> + VECT_ARRAY_VAR(vector, T1, W, N, X)); \
>> + memcpy(VECT_VAR(result, T1, W, N), VECT_VAR(result_bis_##X, T1, W, N),
>> \
>> + sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> +
>> + /* Overwrite "result" with the contents of "result_bis"[Y]. */
>> +#define TEST_EXTRA_CHUNK(T1, W, N, X,Y) \
>> + memcpy(VECT_VAR(result, T1, W, N), \
>> + &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \
>> + sizeof(VECT_VAR(result, T1, W, N)));
>> +
>> +#define DECL_ALL_VLDX_DUP(X) \
>> + DECL_VLDX_DUP(int, 8, 8, X); \
>> + DECL_VLDX_DUP(int, 16, 4, X); \
>> + DECL_VLDX_DUP(int, 32, 2, X); \
>> + DECL_VLDX_DUP(int, 64, 1, X); \
>> + DECL_VLDX_DUP(uint, 8, 8, X); \
>> + DECL_VLDX_DUP(uint, 16, 4, X); \
>> + DECL_VLDX_DUP(uint, 32, 2, X); \
>> + DECL_VLDX_DUP(uint, 64, 1, X); \
>> + DECL_VLDX_DUP(poly, 8, 8, X); \
>> + DECL_VLDX_DUP(poly, 16, 4, X); \
>> + DECL_VLDX_DUP(float, 32, 2, X)
>> +
>> +#define TEST_ALL_VLDX_DUP(X) \
>> + TEST_VLDX_DUP(, int, s, 8, 8, X); \
>> + TEST_VLDX_DUP(, int, s, 16, 4, X); \
>> + TEST_VLDX_DUP(, int, s, 32, 2, X); \
>> + TEST_VLDX_DUP(, int, s, 64, 1, X); \
>> + TEST_VLDX_DUP(, uint, u, 8, 8, X); \
>> + TEST_VLDX_DUP(, uint, u, 16, 4, X); \
>> + TEST_VLDX_DUP(, uint, u, 32, 2, X); \
>> + TEST_VLDX_DUP(, uint, u, 64, 1, X); \
>> + TEST_VLDX_DUP(, poly, p, 8, 8, X); \
>> + TEST_VLDX_DUP(, poly, p, 16, 4, X); \
>> + TEST_VLDX_DUP(, float, f, 32, 2, X)
>> +
>> +#define TEST_ALL_EXTRA_CHUNKS(X, Y) \
>> + TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \
>> + TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \
>> + TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \
>> + TEST_EXTRA_CHUNK(int, 64, 1, X, Y); \
>> + TEST_EXTRA_CHUNK(uint, 8, 8, X, Y); \
>> + TEST_EXTRA_CHUNK(uint, 16, 4, X, Y); \
>> + TEST_EXTRA_CHUNK(uint, 32, 2, X, Y); \
>> + TEST_EXTRA_CHUNK(uint, 64, 1, X, Y); \
>> + TEST_EXTRA_CHUNK(poly, 8, 8, X, Y); \
>> + TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \
>> + TEST_EXTRA_CHUNK(float, 32, 2, X, Y)
>> +
>> +
>> + DECL_ALL_VLDX_DUP(2);
>> + DECL_ALL_VLDX_DUP(3);
>> + DECL_ALL_VLDX_DUP(4);
>> +
>> + /* Special input buffers of suitable size are needed for
>> vld2/vld3/vld4. */
>> + /* Input buffers for vld2, 1 of each size */
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 8);
>> + PAD(buffer_vld2_pad, int, 8, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 4);
>> + PAD(buffer_vld2_pad, int, 16, 4);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 2);
>> + PAD(buffer_vld2_pad, int, 32, 2);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 1);
>> + PAD(buffer_vld2_pad, int, 64, 1);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 8);
>> + PAD(buffer_vld2_pad, uint, 8, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 4);
>> + PAD(buffer_vld2_pad, uint, 16, 4);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 2);
>> + PAD(buffer_vld2_pad, uint, 32, 2);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 1);
>> + PAD(buffer_vld2_pad, uint, 64, 1);
>> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 8);
>> + PAD(buffer_vld2_pad, poly, 8, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4);
>> + PAD(buffer_vld2_pad, poly, 16, 4);
>> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2);
>> + PAD(buffer_vld2_pad, float, 32, 2);
>> +
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 8, 16);
>> + PAD(buffer_vld2_pad, int, 8, 16);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 16, 8);
>> + PAD(buffer_vld2_pad, int, 16, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 32, 4);
>> + PAD(buffer_vld2_pad, int, 32, 4);
>> + VECT_ARRAY_INIT2(buffer_vld2, int, 64, 2);
>> + PAD(buffer_vld2_pad, int, 64, 2);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 8, 16);
>> + PAD(buffer_vld2_pad, uint, 8, 16);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 16, 8);
>> + PAD(buffer_vld2_pad, uint, 16, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 32, 4);
>> + PAD(buffer_vld2_pad, uint, 32, 4);
>> + VECT_ARRAY_INIT2(buffer_vld2, uint, 64, 2);
>> + PAD(buffer_vld2_pad, uint, 64, 2);
>> + VECT_ARRAY_INIT2(buffer_vld2, poly, 8, 16);
>> + PAD(buffer_vld2_pad, poly, 8, 16);
>> + VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8);
>> + PAD(buffer_vld2_pad, poly, 16, 8);
>> + VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4);
>> + PAD(buffer_vld2_pad, float, 32, 4);
>> +
>> + /* Input buffers for vld3, 1 of each size */
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 8);
>> + PAD(buffer_vld3_pad, int, 8, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 4);
>> + PAD(buffer_vld3_pad, int, 16, 4);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 2);
>> + PAD(buffer_vld3_pad, int, 32, 2);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 1);
>> + PAD(buffer_vld3_pad, int, 64, 1);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 8);
>> + PAD(buffer_vld3_pad, uint, 8, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 4);
>> + PAD(buffer_vld3_pad, uint, 16, 4);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 2);
>> + PAD(buffer_vld3_pad, uint, 32, 2);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 1);
>> + PAD(buffer_vld3_pad, uint, 64, 1);
>> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 8);
>> + PAD(buffer_vld3_pad, poly, 8, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4);
>> + PAD(buffer_vld3_pad, poly, 16, 4);
>> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2);
>> + PAD(buffer_vld3_pad, float, 32, 2);
>> +
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 8, 16);
>> + PAD(buffer_vld3_pad, int, 8, 16);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 16, 8);
>> + PAD(buffer_vld3_pad, int, 16, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 32, 4);
>> + PAD(buffer_vld3_pad, int, 32, 4);
>> + VECT_ARRAY_INIT3(buffer_vld3, int, 64, 2);
>> + PAD(buffer_vld3_pad, int, 64, 2);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 8, 16);
>> + PAD(buffer_vld3_pad, uint, 8, 16);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 16, 8);
>> + PAD(buffer_vld3_pad, uint, 16, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 32, 4);
>> + PAD(buffer_vld3_pad, uint, 32, 4);
>> + VECT_ARRAY_INIT3(buffer_vld3, uint, 64, 2);
>> + PAD(buffer_vld3_pad, uint, 64, 2);
>> + VECT_ARRAY_INIT3(buffer_vld3, poly, 8, 16);
>> + PAD(buffer_vld3_pad, poly, 8, 16);
>> + VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8);
>> + PAD(buffer_vld3_pad, poly, 16, 8);
>> + VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4);
>> + PAD(buffer_vld3_pad, float, 32, 4);
>> +
>> + /* Input buffers for vld4, 1 of each size */
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 8);
>> + PAD(buffer_vld4_pad, int, 8, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 4);
>> + PAD(buffer_vld4_pad, int, 16, 4);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 2);
>> + PAD(buffer_vld4_pad, int, 32, 2);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 1);
>> + PAD(buffer_vld4_pad, int, 64, 1);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 8);
>> + PAD(buffer_vld4_pad, uint, 8, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 4);
>> + PAD(buffer_vld4_pad, uint, 16, 4);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 2);
>> + PAD(buffer_vld4_pad, uint, 32, 2);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 1);
>> + PAD(buffer_vld4_pad, uint, 64, 1);
>> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 8);
>> + PAD(buffer_vld4_pad, poly, 8, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4);
>> + PAD(buffer_vld4_pad, poly, 16, 4);
>> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2);
>> + PAD(buffer_vld4_pad, float, 32, 2);
>> +
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 8, 16);
>> + PAD(buffer_vld4_pad, int, 8, 16);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 16, 8);
>> + PAD(buffer_vld4_pad, int, 16, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 32, 4);
>> + PAD(buffer_vld4_pad, int, 32, 4);
>> + VECT_ARRAY_INIT4(buffer_vld4, int, 64, 2);
>> + PAD(buffer_vld4_pad, int, 64, 2);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 8, 16);
>> + PAD(buffer_vld4_pad, uint, 8, 16);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 16, 8);
>> + PAD(buffer_vld4_pad, uint, 16, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 32, 4);
>> + PAD(buffer_vld4_pad, uint, 32, 4);
>> + VECT_ARRAY_INIT4(buffer_vld4, uint, 64, 2);
>> + PAD(buffer_vld4_pad, uint, 64, 2);
>> + VECT_ARRAY_INIT4(buffer_vld4, poly, 8, 16);
>> + PAD(buffer_vld4_pad, poly, 8, 16);
>> + VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8);
>> + PAD(buffer_vld4_pad, poly, 16, 8);
>> + VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4);
>> + PAD(buffer_vld4_pad, float, 32, 4);
>> +
>> + /* Check vld2_dup/vld2q_dup. */
>> + clean_results ();
>> +#define TEST_MSG "VLD2_DUP/VLD2Q_DUP"
>> + TEST_ALL_VLDX_DUP(2);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_0, "chunk 0");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(2, 1);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld2_1, "chunk 1");
>> +
>> + /* Check vld3_dup/vld3q_dup. */
>> + clean_results ();
>> +#undef TEST_MSG
>> +#define TEST_MSG "VLD3_DUP/VLD3Q_DUP"
>> + TEST_ALL_VLDX_DUP(3);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_0, "chunk 0");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(3, 1);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_1, "chunk 1");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(3, 2);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld3_2, "chunk 2");
>> +
>> + /* Check vld4_dup/vld4q_dup */
>> + clean_results ();
>> +#undef TEST_MSG
>> +#define TEST_MSG "VLD4_DUP/VLD4Q_DUP"
>> + TEST_ALL_VLDX_DUP(4);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_0, "chunk 0");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(4, 1);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_1, "chunk 1");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(4, 2);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_2, "chunk 2");
>> +
>> + TEST_ALL_EXTRA_CHUNKS(4, 3);
>> + CHECK_RESULTS_NAMED (TEST_MSG, expected_vld4_3, "chunk 3");
>> +}
>> +
>> +int main (void)
>> +{
>> + exec_vldX_dup ();
>> + return 0;
>> +}
>> --
>> 2.1.0
>>
>>
>
> LGTM.
>
Thanks, I should mention that this test fails on aarch64_be, because
of pending Alan's patches.
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
@ 2015-01-16 18:18 ` Tejas Belagod
2015-01-20 15:35 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:18 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
> new file mode 100644
> index 0000000..427c9ba
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
> @@ -0,0 +1,77 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
> + 0xfffffff2, 0xfffffff3 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
> + 0xfffffffffffffff1 };
> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
No poly or float for vmovl.
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 22/36] Add vmovn tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
@ 2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:21 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
> new file mode 100644
> index 0000000..bc2c2ca
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn.c
> @@ -0,0 +1,50 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7 };
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
> + 0xf4, 0xf5, 0xf6, 0xf7 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
> +
> +#define TEST_MSG "VMOVN"
> +void exec_vmovn (void)
> +{
> + /* Basic test: vec64=vmovn(vec128), then store the result. */
> +#define TEST_VMOVN(T1, T2, W, W2, N) \
> + VECT_VAR(vector64, T1, W2, N) = \
> + vmovn_##T2##W(VECT_VAR(vector128, T1, W, N)); \
> + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
> +
> + DECL_VARIABLE_64BITS_VARIANTS(vector64);
> + DECL_VARIABLE_128BITS_VARIANTS(vector128);
> +
> + TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer);
> +
> + clean_results ();
> +
> + TEST_VMOVN(int, s, 16, 8, 8);
> + TEST_VMOVN(int, s, 32, 16, 4);
> + TEST_VMOVN(int, s, 64, 32, 2);
> + TEST_VMOVN(uint, u, 16, 8, 8);
> + TEST_VMOVN(uint, u, 32, 16, 4);
> + TEST_VMOVN(uint, u, 64, 32, 2);
> +
> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
> +}
> +
> +int main (void)
> +{
> + exec_vmovn ();
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
@ 2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:23 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
> new file mode 100644
> index 0000000..978cd9b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c
> @@ -0,0 +1,104 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffface0, 0xffffb212 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b66666, 0xc3ab0000 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xffc0, 0xffc4, 0xffc8, 0xffcc,
> + 0xffd0, 0xffd4, 0xffd8, 0xffdc };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffde0, 0xfffffe02,
> + 0xfffffe24, 0xfffffe46 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xbbc0, 0xc004, 0xc448, 0xc88c,
> + 0xccd0, 0xd114, 0xd558, 0xd99c };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffface0, 0xffffb212,
> + 0xffffb744, 0xffffbc76 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc3b66666, 0xc3ab0000,
> + 0xc39f9999, 0xc3943333 };
> +
> +#define TEST_MSG "VMUL_LANE"
> +void exec_vmul_lane (void)
> +{
> +#define DECL_VMUL(VAR) \
> + DECL_VARIABLE(VAR, int, 16, 4); \
> + DECL_VARIABLE(VAR, int, 32, 2); \
> + DECL_VARIABLE(VAR, uint, 16, 4); \
> + DECL_VARIABLE(VAR, uint, 32, 2); \
> + DECL_VARIABLE(VAR, float, 32, 2); \
> + DECL_VARIABLE(VAR, int, 16, 8); \
> + DECL_VARIABLE(VAR, int, 32, 4); \
> + DECL_VARIABLE(VAR, uint, 16, 8); \
> + DECL_VARIABLE(VAR, uint, 32, 4); \
> + DECL_VARIABLE(VAR, float, 32, 4)
> +
> + /* vector_res = vmul_lane(vector,vector2,lane), then store the result. */
> +#define TEST_VMUL_LANE(Q, T1, T2, W, N, N2, L) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + vmul##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector2, T1, W, N2), \
> + L); \
> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
> + VECT_VAR(vector_res, T1, W, N))
> +
> + DECL_VMUL(vector);
> + DECL_VMUL(vector_res);
> +
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector2, uint, 16, 4);
> + DECL_VARIABLE(vector2, uint, 32, 2);
> + DECL_VARIABLE(vector2, float, 32, 2);
> +
> + clean_results ();
> +
> + /* Initialize vector from pre-initialized values. */
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, , uint, u, 16, 4);
> + VLOAD(vector, buffer, , uint, u, 32, 2);
> + VLOAD(vector, buffer, , float, f, 32, 2);
> + VLOAD(vector, buffer, q, int, s, 16, 8);
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 16, 8);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, float, f, 32, 4);
> +
> + /* Initialize vector2. */
> + VDUP(vector2, , int, s, 16, 4, 0x4);
> + VDUP(vector2, , int, s, 32, 2, 0x22);
> + VDUP(vector2, , uint, u, 16, 4, 0x444);
> + VDUP(vector2, , uint, u, 32, 2, 0x532);
> + VDUP(vector2, , float, f, 32, 2, 22.8f);
> +
> + /* Choose lane arbitrarily. */
> + TEST_VMUL_LANE(, int, s, 16, 4, 4, 2);
> + TEST_VMUL_LANE(, int, s, 32, 2, 2, 1);
> + TEST_VMUL_LANE(, uint, u, 16, 4, 4, 2);
> + TEST_VMUL_LANE(, uint, u, 32, 2, 2, 1);
> + TEST_VMUL_LANE(, float, f, 32, 2, 2, 1);
> + TEST_VMUL_LANE(q, int, s, 16, 8, 4, 2);
> + TEST_VMUL_LANE(q, int, s, 32, 4, 2, 0);
> + TEST_VMUL_LANE(q, uint, u, 16, 8, 4, 2);
> + TEST_VMUL_LANE(q, uint, u, 32, 4, 2, 1);
> + TEST_VMUL_LANE(q, float, f, 32, 4, 2, 0);
> +
> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int main (void)
> +{
> + exec_vmul_lane ();
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
@ 2015-01-16 18:24 ` Tejas Belagod
2015-01-19 15:23 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:24 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
> new file mode 100644
> index 0000000..be0ee65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c
> @@ -0,0 +1,96 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfef0, 0xff01, 0xff12, 0xff23 };
> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffde0, 0xfffffe02 };
> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfcd0, 0xfd03, 0xfd36, 0xfd69 };
> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffbc0, 0xfffffc04 };
> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b26666, 0xc3a74000 };
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfab0, 0xfb05, 0xfb5a, 0xfbaf,
> + 0xfc04, 0xfc59, 0xfcae, 0xfd03 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffff9a0, 0xfffffa06,
> + 0xfffffa6c, 0xfffffad2 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf890, 0xf907, 0xf97e, 0xf9f5,
> + 0xfa6c, 0xfae3, 0xfb5a, 0xfbd1 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffff780, 0xfffff808,
> + 0xfffff890, 0xfffff918 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4b1cccd, 0xc4a6b000,
> + 0xc49b9333, 0xc4907667 };
> +
> +#define INSN_NAME vmul_n
> +#define TEST_MSG "VMUL_N"
> +
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> +#define DECL_VMUL(VAR) \
> + DECL_VARIABLE(VAR, int, 16, 4); \
> + DECL_VARIABLE(VAR, int, 32, 2); \
> + DECL_VARIABLE(VAR, uint, 16, 4); \
> + DECL_VARIABLE(VAR, uint, 32, 2); \
> + DECL_VARIABLE(VAR, float, 32, 2); \
> + DECL_VARIABLE(VAR, int, 16, 8); \
> + DECL_VARIABLE(VAR, int, 32, 4); \
> + DECL_VARIABLE(VAR, uint, 16, 8); \
> + DECL_VARIABLE(VAR, uint, 32, 4); \
> + DECL_VARIABLE(VAR, float, 32, 4)
> +
> + /* vector_res = vmul_n(vector,val), then store the result. */
> +#define TEST_VMUL_N(Q, T1, T2, W, N, L) \
> + VECT_VAR(vector_res, T1, W, N) = \
> + vmul##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
> + L); \
> + vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
> + VECT_VAR(vector_res, T1, W, N))
> +
> + DECL_VMUL(vector);
> + DECL_VMUL(vector_res);
> +
> + clean_results ();
> +
> + /* Initialize vector from pre-initialized values. */
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, , uint, u, 16, 4);
> + VLOAD(vector, buffer, , uint, u, 32, 2);
> + VLOAD(vector, buffer, , float, f, 32, 2);
> + VLOAD(vector, buffer, q, int, s, 16, 8);
> + VLOAD(vector, buffer, q, int, s, 32, 4);
> + VLOAD(vector, buffer, q, uint, u, 16, 8);
> + VLOAD(vector, buffer, q, uint, u, 32, 4);
> + VLOAD(vector, buffer, q, float, f, 32, 4);
> +
> + /* Choose multiplier arbitrarily. */
> + TEST_VMUL_N(, int, s, 16, 4, 0x11);
> + TEST_VMUL_N(, int, s, 32, 2, 0x22);
> + TEST_VMUL_N(, uint, u, 16, 4, 0x33);
> + TEST_VMUL_N(, uint, u, 32, 2, 0x44);
> + TEST_VMUL_N(, float, f, 32, 2, 22.3f);
> + TEST_VMUL_N(q, int, s, 16, 8, 0x55);
> + TEST_VMUL_N(q, int, s, 32, 4, 0x66);
> + TEST_VMUL_N(q, uint, u, 16, 8, 0x77);
> + TEST_VMUL_N(q, uint, u, 32, 4, 0x88);
> + TEST_VMUL_N(q, float, f, 32, 4, 88.9f);
> +
> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> +
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 25/36] Add vmull tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
@ 2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:26 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
> new file mode 100644
> index 0000000..3fdd51e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull.c
> @@ -0,0 +1,75 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,16,8) [] = { 0x100, 0xe1, 0xc4, 0xa9,
> + 0x90, 0x79, 0x64, 0x51 };
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x100, 0xe1, 0xc4, 0xa9 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x100, 0xe1 };
> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xe100, 0xe2e1, 0xe4c4, 0xe6a9,
> + 0xe890, 0xea79, 0xec64, 0xee51 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffe00100, 0xffe200e1,
> + 0xffe400c4, 0xffe600a9 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffe000000100,
> + 0xffffffe2000000e1 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x5500, 0x5501, 0x5504, 0x5505,
> + 0x5510, 0x5511, 0x5514, 0x5515 };
> +
> +#define TEST_MSG "VMULL"
> +void exec_vmull (void)
> +{
> + /* Basic test: y=vmull(x,x), then store the result. */
> +#define TEST_VMULL(T1, T2, W, W2, N) \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + vmull_##T2##W(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector, T1, W, N)); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> +
> + DECL_VARIABLE(vector, int, 8, 8);
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 8, 8);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> + DECL_VARIABLE(vector, poly, 8, 8);
> + DECL_VARIABLE(vector_res, int, 16, 8);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> + DECL_VARIABLE(vector_res, uint, 16, 8);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> + DECL_VARIABLE(vector_res, poly, 16, 8);
> +
> + clean_results ();
> +
> + VLOAD(vector, buffer, , int, s, 8, 8);
> + VLOAD(vector, buffer, , int, s, 16, 4);
> + VLOAD(vector, buffer, , int, s, 32, 2);
> + VLOAD(vector, buffer, , uint, u, 8, 8);
> + VLOAD(vector, buffer, , uint, u, 16, 4);
> + VLOAD(vector, buffer, , uint, u, 32, 2);
> + VLOAD(vector, buffer, , poly, p, 8, 8);
> +
> + TEST_VMULL(int, s, 8, 16, 8);
> + TEST_VMULL(int, s, 16, 32, 4);
> + TEST_VMULL(int, s, 32, 64, 2);
> + TEST_VMULL(uint, u, 8, 16, 8);
> + TEST_VMULL(uint, u, 16, 32, 4);
> + TEST_VMULL(uint, u, 32, 64, 2);
> + TEST_VMULL(poly, p, 8, 16, 8);
> +
> + CHECK(TEST_MSG, int, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 16, 8, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, "");
> +}
> +
> +int main (void)
> +{
> + exec_vmull ();
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
@ 2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:28 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
> new file mode 100644
> index 0000000..d3aa879
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c
> @@ -0,0 +1,66 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x2000, 0x2000 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x4000, 0x4000, 0x4000, 0x4000 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x2000, 0x2000 };
> +
> +#define TEST_MSG "VMULL_LANE"
> +void exec_vmull_lane (void)
> +{
> + /* vector_res = vmull_lane(vector,vector2,lane), then store the result. */
> +#define TEST_VMULL_LANE(T1, T2, W, W2, N, L) \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + vmull##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
> + VECT_VAR(vector2, T1, W, N), \
> + L); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> +
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector2, uint, 16, 4);
> + DECL_VARIABLE(vector2, uint, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + /* Initialize vector. */
> + VDUP(vector, , int, s, 16, 4, 0x1000);
> + VDUP(vector, , int, s, 32, 2, 0x1000);
> + VDUP(vector, , uint, u, 16, 4, 0x1000);
> + VDUP(vector, , uint, u, 32, 2, 0x1000);
> +
> + /* Initialize vector2. */
> + VDUP(vector2, , int, s, 16, 4, 0x4);
> + VDUP(vector2, , int, s, 32, 2, 0x2);
> + VDUP(vector2, , uint, u, 16, 4, 0x4);
> + VDUP(vector2, , uint, u, 32, 2, 0x2);
> +
> + /* Choose lane arbitrarily. */
> + TEST_VMULL_LANE(int, s, 16, 32, 4, 2);
> + TEST_VMULL_LANE(int, s, 32, 64, 2, 1);
> + TEST_VMULL_LANE(uint, u, 16, 32, 4, 2);
> + TEST_VMULL_LANE(uint, u, 32, 64, 2, 1);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx32, expected, "");
> +}
> +
> +int main (void)
> +{
> + exec_vmull_lane ();
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
@ 2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:32 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
> new file mode 100644
> index 0000000..df28a94
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_n.c
> @@ -0,0 +1,61 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x11000, 0x11000, 0x11000, 0x11000 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0x22000, 0x22000 };
> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33000, 0x33000, 0x33000, 0x33000 };
> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x44000, 0x44000 };
> +
> +#define INSN_NAME vmull
> +#define TEST_MSG "VMULL_N"
> +void exec_vmull_n (void)
> +{
> + int i;
> +
> + /* vector_res = vmull_n(vector,val), then store the result. */
> +#define TEST_VMULL_N1(INSN, T1, T2, W, W2, N, L) \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + INSN##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
> + L); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
> +
> +#define TEST_VMULL_N(INSN, T1, T2, W, W2, N, L) \
> + TEST_VMULL_N1(INSN, T1, T2, W, W2, N, L)
> +
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> + DECL_VARIABLE(vector_res, uint, 32, 4);
> + DECL_VARIABLE(vector_res, uint, 64, 2);
> +
> + clean_results ();
> +
> + /* Initialize vector. */
> + VDUP(vector, , int, s, 16, 4, 0x1000);
> + VDUP(vector, , int, s, 32, 2, 0x1000);
> + VDUP(vector, , uint, u, 16, 4, 0x1000);
> + VDUP(vector, , uint, u, 32, 2, 0x1000);
> +
> + /* Choose multiplier arbitrarily. */
> + TEST_VMULL_N(INSN_NAME, int, s, 16, 32, 4, 0x11);
> + TEST_VMULL_N(INSN_NAME, int, s, 32, 64, 2, 0x22);
> + TEST_VMULL_N(INSN_NAME, uint, u, 16, 32, 4, 0x33);
> + TEST_VMULL_N(INSN_NAME, uint, u, 32, 64, 2, 0x44);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
> +}
> +
> +int main (void)
> +{
> + exec_vmull_n ();
> + return 0;
> +}
>
LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 28/36] Add vmnv tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
@ 2015-01-16 18:39 ` Tejas Belagod
2015-01-20 15:36 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:39 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
No float or poly16 for vmvn_*.
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 29/36] Add vpadal tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
@ 2015-01-16 18:41 ` Tejas Belagod
2015-01-20 15:39 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:41 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
No float or poly ops for VPADAL insns.
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
@ 2015-01-16 18:48 ` Tejas Belagod
2015-01-16 19:05 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:48 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33,
> + 0x33, 0x33, 0x33, 0x33 };
> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
> + 0x3333, 0x3333, 0x3333, 0x3333 };
> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
> + 0x33333333, 0x33333333 };
> +
No poly or float ops.
> +#define INSN_NAME vpaddl
> +#define TEST_MSG "VPADDL/VPADDLQ"
> +
> +#define FNNAME1(NAME) void exec_ ## NAME (void)
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +FNNAME (INSN_NAME)
> +{
> + /* Basic test: y=OP(x), then store the result. */
> +#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
> + VECT_VAR(vector_res, T1, W2, N2) = \
> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
> + vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
> + VECT_VAR(vector_res, T1, W2, N2))
> +
> +#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
> + TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
> +
> + /* No need for 64 bits variants. */
These look like 64-bit variants.
> + DECL_VARIABLE(vector, int, 8, 8);
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector, uint, 8, 8);
> + DECL_VARIABLE(vector, uint, 16, 4);
> + DECL_VARIABLE(vector, uint, 32, 2);
> + DECL_VARIABLE(vector, int, 8, 16);
> + DECL_VARIABLE(vector, int, 16, 8);
> + DECL_VARIABLE(vector, int, 32, 4);
> + DECL_VARIABLE(vector, uint, 8, 16);
> + DECL_VARIABLE(vector, uint, 16, 8);
> + DECL_VARIABLE(vector, uint, 32, 4);
> +
> + /* Apply a unary operator named INSN_NAME. */
Unary op?
> + TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
> + TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
> + TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
> + TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
> + TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
> + TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
> + TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
> + TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
> + TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
> + TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
> + TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
> + TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
> +
> + CHECK_RESULTS (TEST_MSG, "");
> +}
> +
> +int main (void)
> +{
> + exec_vpaddl ();
> + return 0;
> +}
>
Otherwise, LGTM.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests.
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
@ 2015-01-16 18:49 ` Tejas Belagod
2015-01-16 19:20 ` Christophe Lyon
2015-01-19 17:16 ` Marcus Shawcroft
1 sibling, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-16 18:49 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 13/01/15 15:18, Christophe Lyon wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
> new file mode 100644
> index 0000000..9e73009
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
> @@ -0,0 +1,92 @@
> +#include <arm_neon.h>
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected values of cumulative_saturation flag. */
> +int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
> +int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
> +
> +/* Expected results. */
> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x44000, 0x44000,
> + 0x44000, 0x44000 };
> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaa000, 0xaa000 };
> +
> +/* Expected values of cumulative_saturation flag when saturation
> + occurs. */
> +int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
> +int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
> +
> +/* Expected results when saturation occurs. */
> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
> + 0x7fffffff, 0x7fffffff };
> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffff,
> + 0x7fffffffffffffff };
> +
> +#define INSN_NAME vqdmull
> +#define TEST_MSG "VQDMULL_N"
> +
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1(NAME)
> +
> +void FNNAME (INSN_NAME) (void)
> +{
> + int i;
> +
> + /* vector_res = vqdmull_n(vector,val), then store the result. */
> +#define TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
> + VECT_VAR(vector_res, T1, W2, N) = \
> + INSN##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
> + L); \
> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), \
> + VECT_VAR(vector_res, T1, W2, N)); \
> + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> + /* Two auxliary macros are necessary to expand INSN. */
> +#define TEST_VQDMULL_N1(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
> + TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> +#define TEST_VQDMULL_N(T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT) \
> + TEST_VQDMULL_N1(INSN_NAME, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
> +
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> +
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
> +
> + clean_results ();
> +
> + /* Initialize vector. */
> + VDUP(vector, , int, s, 16, 4, 0x1000);
> + VDUP(vector, , int, s, 32, 2, 0x1000);
> +
> + /* Initialize vector2. */
> + VDUP(vector2, , int, s, 16, 4, 0x4);
> + VDUP(vector2, , int, s, 32, 2, 0x2);
> +
> + /* Choose multiplier arbitrarily. */
> + TEST_VQDMULL_N(int, s, 16, 32, 4, 0x22, expected_cumulative_sat, "");
> + TEST_VQDMULL_N(int, s, 32, 64, 2, 0x55, expected_cumulative_sat, "");
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
> +
> + VDUP(vector, , int, s, 16, 4, 0x8000);
> + VDUP(vector, , int, s, 32, 2, 0x80000000);
> +
> +#define TEST_MSG2 "with saturation"
> + TEST_VQDMULL_N(int, s, 16, 32, 4, 0x8000, expected_cumulative_sat2, TEST_MSG2);
> + TEST_VQDMULL_N(int, s, 32, 64, 2, 0x80000000, expected_cumulative_sat2, TEST_MSG2);
> +
> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
> +}
> +
> +int main (void)
> +{
> + FNNAME (INSN_NAME) ();
> + return 0;
> +}
>
Patches 31 to 36 also LGTM.
A general nit about all the patches. Code like:
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
A space before the '(' is required.
Thanks for working on these tests.
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-16 18:48 ` Tejas Belagod
@ 2015-01-16 19:05 ` Christophe Lyon
2015-01-16 20:34 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 19:05 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 19:33, Tejas Belagod <tejas.belagod@arm.com> wrote:
>
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>
>
> No poly or float ops.
>
>> +#define INSN_NAME vpaddl
>> +#define TEST_MSG "VPADDL/VPADDLQ"
>> +
>> +#define FNNAME1(NAME) void exec_ ## NAME (void)
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +FNNAME (INSN_NAME)
>> +{
>> + /* Basic test: y=OP(x), then store the result. */
>> +#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
>> + VECT_VAR(vector_res, T1, W2, N2) = \
>> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
>> + vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
>> + VECT_VAR(vector_res, T1, W2, N2))
>> +
>> +#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
>> + TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
>> +
>> + /* No need for 64 bits variants. */
>
>
> These look like 64-bit variants.
>
I mean no vector element of 64 bits.
>> + DECL_VARIABLE(vector, int, 8, 8);
>> + DECL_VARIABLE(vector, int, 16, 4);
>> + DECL_VARIABLE(vector, int, 32, 2);
>> + DECL_VARIABLE(vector, uint, 8, 8);
>> + DECL_VARIABLE(vector, uint, 16, 4);
>> + DECL_VARIABLE(vector, uint, 32, 2);
>> + DECL_VARIABLE(vector, int, 8, 16);
>> + DECL_VARIABLE(vector, int, 16, 8);
>> + DECL_VARIABLE(vector, int, 32, 4);
>> + DECL_VARIABLE(vector, uint, 8, 16);
>> + DECL_VARIABLE(vector, uint, 16, 8);
>> + DECL_VARIABLE(vector, uint, 32, 4);
>> +
>
>
>> + /* Apply a unary operator named INSN_NAME. */
>
> Unary op?
Cut & paste error, again.
>
>> + TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
>> + TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
>> + TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
>> + TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
>> + TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
>> + TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
>> + TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
>> + TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
>> + TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
>> + TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
>> + TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
>> + TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
>> +
>> + CHECK_RESULTS (TEST_MSG, "");
>> +}
>> +
>> +int main (void)
>> +{
>> + exec_vpaddl ();
>> + return 0;
>> +}
>>
>
>
> Otherwise, LGTM.
>
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests.
2015-01-16 18:49 ` Tejas Belagod
@ 2015-01-16 19:20 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 19:20 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 19:40, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
>>
>> diff --git
>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
>> new file mode 100644
>> index 0000000..9e73009
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c
>> @@ -0,0 +1,92 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected values of cumulative_saturation flag. */
>> +int VECT_VAR(expected_cumulative_sat,int,16,4) = 0;
>> +int VECT_VAR(expected_cumulative_sat,int,32,2) = 0;
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0x44000, 0x44000,
>> + 0x44000, 0x44000 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xaa000, 0xaa000 };
>> +
>> +/* Expected values of cumulative_saturation flag when saturation
>> + occurs. */
>> +int VECT_VAR(expected_cumulative_sat2,int,16,4) = 1;
>> +int VECT_VAR(expected_cumulative_sat2,int,32,2) = 1;
>> +
>> +/* Expected results when saturation occurs. */
>> +VECT_VAR_DECL(expected2,int,32,4) [] = { 0x7fffffff, 0x7fffffff,
>> + 0x7fffffff, 0x7fffffff };
>> +VECT_VAR_DECL(expected2,int,64,2) [] = { 0x7fffffffffffffff,
>> + 0x7fffffffffffffff };
>> +
>> +#define INSN_NAME vqdmull
>> +#define TEST_MSG "VQDMULL_N"
>> +
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1(NAME)
>> +
>> +void FNNAME (INSN_NAME) (void)
>> +{
>> + int i;
>> +
>> + /* vector_res = vqdmull_n(vector,val), then store the result. */
>> +#define TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L,
>> EXPECTED_CUMULATIVE_SAT, CMT) \
>> + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W2, N)); \
>> + VECT_VAR(vector_res, T1, W2, N) = \
>> + INSN##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
>> + L); \
>> + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), \
>> + VECT_VAR(vector_res, T1, W2, N)); \
>> + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT)
>> +
>> + /* Two auxliary macros are necessary to expand INSN. */
>> +#define TEST_VQDMULL_N1(INSN, T1, T2, W, W2, N, L,
>> EXPECTED_CUMULATIVE_SAT, CMT) \
>> + TEST_VQDMULL_N2(INSN, T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT,
>> CMT)
>> +
>> +#define TEST_VQDMULL_N(T1, T2, W, W2, N, L, EXPECTED_CUMULATIVE_SAT, CMT)
>> \
>> + TEST_VQDMULL_N1(INSN_NAME, T1, T2, W, W2, N, L,
>> EXPECTED_CUMULATIVE_SAT, CMT)
>> +
>> + DECL_VARIABLE(vector, int, 16, 4);
>> + DECL_VARIABLE(vector, int, 32, 2);
>> + DECL_VARIABLE(vector2, int, 16, 4);
>> + DECL_VARIABLE(vector2, int, 32, 2);
>> +
>> + DECL_VARIABLE(vector_res, int, 32, 4);
>> + DECL_VARIABLE(vector_res, int, 64, 2);
>> +
>> + clean_results ();
>> +
>> + /* Initialize vector. */
>> + VDUP(vector, , int, s, 16, 4, 0x1000);
>> + VDUP(vector, , int, s, 32, 2, 0x1000);
>> +
>> + /* Initialize vector2. */
>> + VDUP(vector2, , int, s, 16, 4, 0x4);
>> + VDUP(vector2, , int, s, 32, 2, 0x2);
>> +
>> + /* Choose multiplier arbitrarily. */
>> + TEST_VQDMULL_N(int, s, 16, 32, 4, 0x22, expected_cumulative_sat, "");
>> + TEST_VQDMULL_N(int, s, 32, 64, 2, 0x55, expected_cumulative_sat, "");
>> +
>> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
>> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
>> +
>> + VDUP(vector, , int, s, 16, 4, 0x8000);
>> + VDUP(vector, , int, s, 32, 2, 0x80000000);
>> +
>> +#define TEST_MSG2 "with saturation"
>> + TEST_VQDMULL_N(int, s, 16, 32, 4, 0x8000, expected_cumulative_sat2,
>> TEST_MSG2);
>> + TEST_VQDMULL_N(int, s, 32, 64, 2, 0x80000000, expected_cumulative_sat2,
>> TEST_MSG2);
>> +
>> + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2);
>> + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2);
>> +}
>> +
>> +int main (void)
>> +{
>> + FNNAME (INSN_NAME) ();
>> + return 0;
>> +}
>>
>
> Patches 31 to 36 also LGTM.
>
> A general nit about all the patches. Code like:
>
> + DECL_VARIABLE(vector, int, 16, 4);
> + DECL_VARIABLE(vector, int, 32, 2);
> + DECL_VARIABLE(vector2, int, 16, 4);
> + DECL_VARIABLE(vector2, int, 32, 2);
> + DECL_VARIABLE(vector_res, int, 32, 4);
> + DECL_VARIABLE(vector_res, int, 64, 2);
>
> A space before the '(' is required.
I should probably fix this in all the tests already committed too.
> Thanks for working on these tests.
Thanks for the review.
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-16 19:05 ` Christophe Lyon
@ 2015-01-16 20:34 ` Christophe Lyon
2015-01-20 15:50 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-16 20:34 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 16 January 2015 at 19:49, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 19:33, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>
>>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33 };
>>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>>> + 0x33333333, 0x33333333 };
>>> +
>>
>>
>> No poly or float ops.
>>
>>> +#define INSN_NAME vpaddl
>>> +#define TEST_MSG "VPADDL/VPADDLQ"
>>> +
>>> +#define FNNAME1(NAME) void exec_ ## NAME (void)
>>> +#define FNNAME(NAME) FNNAME1(NAME)
>>> +
>>> +FNNAME (INSN_NAME)
>>> +{
>>> + /* Basic test: y=OP(x), then store the result. */
>>> +#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
>>> + VECT_VAR(vector_res, T1, W2, N2) = \
>>> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
>>> + vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
>>> + VECT_VAR(vector_res, T1, W2, N2))
>>> +
>>> +#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
>>> + TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
>>> +
>>> + /* No need for 64 bits variants. */
>>
>>
>> These look like 64-bit variants.
>>
> I mean no vector element of 64 bits.
>
>>> + DECL_VARIABLE(vector, int, 8, 8);
>>> + DECL_VARIABLE(vector, int, 16, 4);
>>> + DECL_VARIABLE(vector, int, 32, 2);
>>> + DECL_VARIABLE(vector, uint, 8, 8);
>>> + DECL_VARIABLE(vector, uint, 16, 4);
>>> + DECL_VARIABLE(vector, uint, 32, 2);
>>> + DECL_VARIABLE(vector, int, 8, 16);
>>> + DECL_VARIABLE(vector, int, 16, 8);
>>> + DECL_VARIABLE(vector, int, 32, 4);
>>> + DECL_VARIABLE(vector, uint, 8, 16);
>>> + DECL_VARIABLE(vector, uint, 16, 8);
>>> + DECL_VARIABLE(vector, uint, 32, 4);
>>> +
>>
>>
>>> + /* Apply a unary operator named INSN_NAME. */
>>
>> Unary op?
>
> Cut & paste error, again.
>
Hmm changed my mind: vpaddl takes only one vector as input, although
it does add 2 vector elements.
>>
>>> + TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
>>> + TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
>>> + TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
>>> + TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
>>> + TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
>>> + TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
>>> + TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
>>> + TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
>>> + TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
>>> +
>>> + CHECK_RESULTS (TEST_MSG, "");
>>> +}
>>> +
>>> +int main (void)
>>> +{
>>> + exec_vpaddl ();
>>> + return 0;
>>> +}
>>>
>>
>>
>> Otherwise, LGTM.
>>
>> Tejas.
>>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-16 17:59 ` Christophe Lyon
@ 2015-01-19 13:34 ` Marcus Shawcroft
2015-01-19 15:49 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:34 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 16 January 2015 at 17:52, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> OK provided, as per the previous couple, that we don;t regression or
>> introduce new fails on aarch64[_be] or aarch32.
>
> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
> when the input is -NaN.
> It's a corner case, and my reading of the ARM ARM is that the result
> should the same as on aarch32.
> I haven't had time to look at it in more details though.
> So, not OK?
They should have the same behaviour in aarch32 and aarch64. Did you
test on HW or a model?
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-16 18:17 ` Christophe Lyon
@ 2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:39 UTC (permalink / raw)
To: Christophe Lyon, gcc-patches
On 16 January 2015 at 18:12, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 16:20, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
>>>
> Thanks, I should mention that this test fails on aarch64_be, because
> of pending Alan's patches.
>
OK, thanks /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
@ 2015-01-19 13:42 ` Marcus Shawcroft
2015-01-20 22:23 ` Christophe Lyon
1 sibling, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:42 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
OK with the the vmlx poly ops dropped /M
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
@ 2015-01-19 13:43 ` Marcus Shawcroft
2015-01-21 0:02 ` Christophe Lyon
1 sibling, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:43 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
> * gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
OK with Tejas' comment addressed. /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests.
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
@ 2015-01-19 13:51 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:51 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests.
2015-01-16 18:12 ` Christophe Lyon
@ 2015-01-19 13:52 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:52 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 16 January 2015 at 18:10, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 16:58, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>> * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vtrn.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Use code from
>>> vshuffle.inc.
>>> * gcc.target/aarch64/advsimd-intrinsics/vzip.c: Use code from
>>> vshuffle.inc.
>>
>> LGTM.
>>
> Thanks, I should mention that the new vtrn test fails on aarch64_be
> (like vzip and vuzp), because of pending Alan's patches to fix
> aarch64_be load/stores.
> So strictly speaking this patch show new fails.
>
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
@ 2015-01-19 13:53 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:53 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
@ 2015-01-19 13:54 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 13:54 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
@ 2015-01-19 14:11 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:11 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
@ 2015-01-19 14:13 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:13 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
@ 2015-01-19 14:14 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:14 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_n.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_n.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests.
2015-01-16 18:11 ` Tejas Belagod
@ 2015-01-19 14:15 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:15 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Christophe Lyon, gcc-patches
On 16 January 2015 at 18:06, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +
>> +void vsri_extra(void)
>> +{
>> + /* Test cases with maximum shift amount (this amount is different
>> + * from vsli. */
>> +
>
>
> Nit. Comment Formatting. Similarly, few other places.
>
> Otherwise, LGTM.
>
> Tejas.
>
w.r.t the unbalanced parenthesis then fair point. This suite of tests
has numerous gnu style inconsistencies. Given that Christophe is
importing a pre-existing body of code and that this is in testsuite it
seemed unreasonable to insist on a reformat. Christophe, fix up the
unbalanced parenthesis and this is OK. /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc.
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
@ 2015-01-19 14:37 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:37 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubl.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddl.c: Use code from
> vXXXl.inc.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
@ 2015-01-19 14:41 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:41 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
> vXXXw.inc.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 22/36] Add vmovn tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
@ 2015-01-19 14:44 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 14:44 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmovn.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
@ 2015-01-19 15:17 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 15:17 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: New file.
>
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
2015-01-16 18:24 ` Tejas Belagod
@ 2015-01-19 15:23 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 15:23 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmul_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 25/36] Add vmull tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
@ 2015-01-19 15:34 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 15:34 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
@ 2015-01-19 15:35 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 15:35 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_lane.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
@ 2015-01-19 15:35 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 15:35 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vmull_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-19 13:34 ` Marcus Shawcroft
@ 2015-01-19 15:49 ` Christophe Lyon
2015-01-19 17:33 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-19 15:49 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
On 19 January 2015 at 14:29, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 16 January 2015 at 17:52, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>
>>> OK provided, as per the previous couple, that we don;t regression or
>>> introduce new fails on aarch64[_be] or aarch32.
>>
>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>> when the input is -NaN.
>> It's a corner case, and my reading of the ARM ARM is that the result
>> should the same as on aarch32.
>> I haven't had time to look at it in more details though.
>> So, not OK?
>
> They should have the same behaviour in aarch32 and aarch64. Did you
> test on HW or a model?
>
I ran the tests on qemu for aarch32 and aarch64-linux, and on the
foundation model for aarch64*-elf.
> /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
@ 2015-01-19 16:46 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 16:46 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
@ 2015-01-19 16:47 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 16:47 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh_lane.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
@ 2015-01-19 16:48 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 16:48 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmulh_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests.
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
@ 2015-01-19 16:52 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 16:52 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests.
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
@ 2015-01-19 16:54 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 16:54 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_lane.c: New file.
OK
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests.
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
@ 2015-01-19 17:16 ` Marcus Shawcroft
1 sibling, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 17:16 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> * gcc.target/aarch64/advsimd-intrinsics/vqdmull_n.c: New file.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests.
2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
` (35 preceding siblings ...)
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
@ 2015-01-19 17:18 ` Marcus Shawcroft
2015-01-20 15:26 ` Christophe Lyon
36 siblings, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 17:18 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 13 January 2015 at 15:17, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> This patch series is a follow-up of the conversion of my existing
> testsuite into DejaGnu. It does not yet cover all the tests I wrote,
> but I chose to post this set to have a chance to have it accepted
> before stage 4. I will have 35 more files to convert after this set.
Christophe, can you respin 9,13,17,21,28,29,30 to address Tejas' comments?
Thanks
/Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-19 15:49 ` Christophe Lyon
@ 2015-01-19 17:33 ` Marcus Shawcroft
2015-01-21 16:35 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-19 17:33 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 19 January 2015 at 15:43, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 19 January 2015 at 14:29, Marcus Shawcroft
> <marcus.shawcroft@gmail.com> wrote:
>> On 16 January 2015 at 17:52, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>
>>>> OK provided, as per the previous couple, that we don;t regression or
>>>> introduce new fails on aarch64[_be] or aarch32.
>>>
>>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>>> when the input is -NaN.
>>> It's a corner case, and my reading of the ARM ARM is that the result
>>> should the same as on aarch32.
>>> I haven't had time to look at it in more details though.
>>> So, not OK?
>>
>> They should have the same behaviour in aarch32 and aarch64. Did you
>> test on HW or a model?
>>
> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
> foundation model for aarch64*-elf.
Leave this one out until we understand why it fails. /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests.
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
@ 2015-01-20 15:26 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:26 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
On 19 January 2015 at 17:52, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 13 January 2015 at 15:17, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> This patch series is a follow-up of the conversion of my existing
>> testsuite into DejaGnu. It does not yet cover all the tests I wrote,
>> but I chose to post this set to have a chance to have it accepted
>> before stage 4. I will have 35 more files to convert after this set.
>
> Christophe, can you respin 9,13,17,21,28,29,30 to address Tejas' comments?
Sure. Here they are.
> Thanks
> /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
2015-01-16 16:35 ` Christophe Lyon
@ 2015-01-20 15:30 ` Christophe Lyon
2015-01-26 14:03 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:30 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 2405 bytes --]
On 16 January 2015 at 17:30, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 17:07, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from
>>> vXXXhn.inc.
>>>
>>> diff --git
>>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>>> new file mode 100644
>>> index 0000000..0dbcc92
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
>>> @@ -0,0 +1,50 @@
>>> +#define FNNAME1(NAME) exec_ ## NAME
>>> +#define FNNAME(NAME) FNNAME1(NAME)
>>> +
>>> +void FNNAME (INSN_NAME) (void)
>>> +{
>>> + /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result.
>>> */
>>> +#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
>>> + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W,
>>> N), \
>>> + VECT_VAR(vector2, T1, W,
>>> N)); \
>>> + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2,
>>> N))
>>> +
>>> +#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
>>> + TEST_VADDHN1(INSN, T1, T2, W, W2, N)
>>> +
>>
>>
>> Minor nit. If this is a template file, maybe you should name this macro
>> TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is
>> confusing.
> Agreed.
>
>>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33 };
>>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>>> };
>>
>>
>> Though never used, poly seems to have sneaked in here too.
> Indeed, sorry for that.
> I rushed to have as many tests as possible ready before stage 4, but
> obviously I missed a few cleanups.
>
Here is an updated version, where I have removed a few more useless
variables than you noticed: the [u]int64x1 as well as the 128 bits
ones.
Christophe.
>> Otherwise, LGTM.
>>
>> Thanks,
>> Tejas.
>>
[-- Attachment #2: 0009-Add-vsubhn-vraddhn-and-vrsubhn-tests.-Split-vaddhn.c.patch --]
[-- Type: text/x-patch, Size: 10159 bytes --]
From 3acafe49a7402b859a88d1ef808b828a0acf96c4 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Tue, 2 Dec 2014 15:05:30 +0100
Subject: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn
tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other
new tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
new file mode 100644
index 0000000..5aabedd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc
@@ -0,0 +1,55 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: vec64=vXXXhn(vec128_a, vec128_b), then store the result. */
+#define TEST_VXXXHN1(INSN, T1, T2, W, W2, N) \
+ VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
+
+#define TEST_VXXXHN(INSN, T1, T2, W, W2, N) \
+ TEST_VXXXHN1(INSN, T1, T2, W, W2, N)
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector1);
+ DECL_VARIABLE_128BITS_VARIANTS(vector2);
+
+ clean_results ();
+
+ /* Fill input vector1 and vector2 with arbitrary values */
+ VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
+ VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
+ VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
+ VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
+ VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
+ VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
+
+ VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
+ VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
+ VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
+ VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
+
+ TEST_VXXXHN(INSN_NAME, int, s, 16, 8, 8);
+ TEST_VXXXHN(INSN_NAME, int, s, 32, 16, 4);
+ TEST_VXXXHN(INSN_NAME, int, s, 64, 32, 2);
+ TEST_VXXXHN(INSN_NAME, uint, u, 16, 8, 8);
+ TEST_VXXXHN(INSN_NAME, uint, u, 32, 16, 4);
+ TEST_VXXXHN(INSN_NAME, uint, u, 64, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
index 58fd5ea..96ae048 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c
@@ -8,100 +8,17 @@
#include <stdint.h>
#endif
+#define INSN_NAME vaddhn
+#define TEST_MSG "VADDHN"
+
/* Expected results. */
VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32 };
VECT_VAR_DECL(expected,int,16,4) [] = { 0x32, 0x32, 0x32, 0x32 };
VECT_VAR_DECL(expected,int,32,2) [] = { 0x18, 0x18 };
-VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
VECT_VAR_DECL(expected,uint,8,8) [] = { 0x3, 0x3, 0x3, 0x3,
0x3, 0x3, 0x3, 0x3 };
VECT_VAR_DECL(expected,uint,16,4) [] = { 0x37, 0x37, 0x37, 0x37 };
VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3, 0x3 };
-VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
-VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
- 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
- 0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
- 0x3333333333333333 };
-VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
- 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333,
- 0x33333333, 0x33333333 };
-VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
- 0x3333333333333333 };
-VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33,
- 0x33, 0x33, 0x33, 0x33 };
-VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
- 0x3333, 0x3333, 0x3333, 0x3333 };
-VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
- 0x33333333, 0x33333333 };
-
-#define INSN_NAME vaddhn
-#define TEST_MSG "VADDHN"
-
-#define FNNAME1(NAME) exec_ ## NAME
-#define FNNAME(NAME) FNNAME1(NAME)
-
-void FNNAME (INSN_NAME) (void)
-{
- /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */
-#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \
- VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \
- VECT_VAR(vector2, T1, W, N)); \
- vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N))
-
-#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \
- TEST_VADDHN1(INSN, T1, T2, W, W2, N)
-
- DECL_VARIABLE_64BITS_VARIANTS(vector64);
- DECL_VARIABLE_128BITS_VARIANTS(vector1);
- DECL_VARIABLE_128BITS_VARIANTS(vector2);
-
- clean_results ();
-
- /* Fill input vector1 and vector2 with arbitrary values */
- VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1));
- VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1));
- VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1));
- VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1));
- VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1));
- VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1));
-
- VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX);
- VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX);
- VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX);
- VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX);
-
- TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8);
- TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4);
- TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2);
- TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8);
- TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4);
- TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2);
-
- CHECK_RESULTS (TEST_MSG, "");
-}
-int main (void)
-{
- FNNAME (INSN_NAME) ();
- return 0;
-}
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
new file mode 100644
index 0000000..12bb3ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vraddhn
+#define TEST_MSG "VRADDHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
+ 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x33, 0x33, 0x33, 0x33 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4,
+ 0x4, 0x4, 0x4, 0x4 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x38, 0x38, 0x38, 0x38 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x4, 0x4 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
new file mode 100644
index 0000000..1ac1b17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vrsubhn
+#define TEST_MSG "VRSUBHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+ 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+
+#include "vXXXhn.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
new file mode 100644
index 0000000..acecf41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c
@@ -0,0 +1,24 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#if defined(__cplusplus)
+#include <cstdint>
+#else
+#include <stdint.h>
+#endif
+
+#define INSN_NAME vsubhn
+#define TEST_MSG "VSUBHN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31,
+ 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 };
+
+#include "vXXXhn.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
2015-01-16 16:30 ` Tejas Belagod
@ 2015-01-20 15:33 ` Christophe Lyon
2015-01-26 14:08 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:33 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 460 bytes --]
On 16 January 2015 at 17:24, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>
>
> No poly vmlx_n, otherwise LGTM.
>
Here is a new version, with a bit more cleanup than requested, since
only 16x4 and 32x2 variants are supported.
> Tejas.
>
>
[-- Attachment #2: 0013-Add-vmla_n-and-vmls_n-tests.patch --]
[-- Type: text/x-patch, Size: 6366 bytes --]
From 2b9d1ba0f54086dc6511766cbf19883b2439ca49 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Thu, 4 Dec 2014 00:37:35 +0100
Subject: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
new file mode 100644
index 0000000..375023a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc
@@ -0,0 +1,87 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_N(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, float, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 4)
+
+ /* vector_res = vmlx_n(vector, vector2, val),
+ then store the result. */
+#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ V); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V) \
+ TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)
+
+ DECL_VMLX_N(vector);
+ DECL_VMLX_N(vector2);
+ DECL_VMLX_N(vector_res);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+ VDUP(vector2, , float, f, 32, 2, 55.2f);
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+ VDUP(vector2, q, float, f, 32, 4, 55.9f);
+
+ /* Choose multiplier arbitrarily. */
+ TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11);
+ TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33);
+ TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44);
+ TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55);
+ TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77);
+ TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88);
+ TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
new file mode 100644
index 0000000..8e88aad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
@@ -0,0 +1,23 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c,
+ 0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776,
+ 0x2777, 0x2778, 0x2779, 0x277a };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b,
+ 0x4568287b, 0x4568387b };
+
+#include "vmlX_n.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
new file mode 100644
index 0000000..228673b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
@@ -0,0 +1,25 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_N"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba,
+ 0xe3bb, 0xe3bc, 0xe3bd, 0xe3be };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13,
+ 0xffffde14, 0xffffde15 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870,
+ 0xd871, 0xd872, 0xd873, 0xd874 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9,
+ 0xffffd2ca, 0xffffd2cb };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b,
+ 0xc569e87b, 0xc569d87b };
+
+#include "vmlX_n.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
2015-01-16 18:02 ` Christophe Lyon
@ 2015-01-20 15:34 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:34 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 7275 bytes --]
On 16 January 2015 at 18:54, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 18:52, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 13/01/15 15:18, Christophe Lyon wrote:
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpadd.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpmax.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vpmin.c: New file.
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> new file mode 100644
>>> index 0000000..7ac2ed4
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
>>> @@ -0,0 +1,67 @@
>>> +#define FNNAME1(NAME) exec_ ## NAME
>>> +#define FNNAME(NAME) FNNAME1(NAME)
>>> +
>>> +void FNNAME (INSN_NAME) (void)
>>> +{
>>> + /* Basic test: y=OP(x), then store the result. */
>>> +#define TEST_VPADD1(INSN, T1, T2, W, N)
>>> \
>>> + VECT_VAR(vector_res, T1, W, N) = \
>>> + INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
>>> + VECT_VAR(vector, T1, W, N)); \
>>> + vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
>>> + VECT_VAR(vector_res, T1, W, N))
>>> +
>>> +#define TEST_VPADD(INSN, T1, T2, W, N) \
>>> + TEST_VPADD1(INSN, T1, T2, W, N) \
>>> +
>>> + /* No need for 64 bits variants. */
>>> + DECL_VARIABLE(vector, int, 8, 8);
>>> + DECL_VARIABLE(vector, int, 16, 4);
>>> + DECL_VARIABLE(vector, int, 32, 2);
>>> + DECL_VARIABLE(vector, uint, 8, 8);
>>> + DECL_VARIABLE(vector, uint, 16, 4);
>>> + DECL_VARIABLE(vector, uint, 32, 2);
>>> + DECL_VARIABLE(vector, float, 32, 2);
>>> +
>>> + DECL_VARIABLE(vector_res, int, 8, 8);
>>> + DECL_VARIABLE(vector_res, int, 16, 4);
>>> + DECL_VARIABLE(vector_res, int, 32, 2);
>>> + DECL_VARIABLE(vector_res, uint, 8, 8);
>>> + DECL_VARIABLE(vector_res, uint, 16, 4);
>>> + DECL_VARIABLE(vector_res, uint, 32, 2);
>>> + DECL_VARIABLE(vector_res, float, 32, 2);
>>> +
>>> + clean_results ();
>>> +
>>> + /* Initialize input "vector" from "buffer". */
>>> + VLOAD(vector, buffer, , int, s, 8, 8);
>>> + VLOAD(vector, buffer, , int, s, 16, 4);
>>> + VLOAD(vector, buffer, , int, s, 32, 2);
>>> + VLOAD(vector, buffer, , uint, u, 8, 8);
>>> + VLOAD(vector, buffer, , uint, u, 16, 4);
>>> + VLOAD(vector, buffer, , uint, u, 32, 2);
>>> + VLOAD(vector, buffer, , float, f, 32, 2);
>>> +
>>> + /* Apply a unary operator named INSN_NAME. */
>>
>>
>> Unary op?
>>
> Hmm cut & paste issue. Thanks
>
Here is an updated versoin, also renaming VPADD into VPXXX, since it's
in a template.
>>
>>> + TEST_VPADD(INSN_NAME, int, s, 8, 8);
>>> + TEST_VPADD(INSN_NAME, int, s, 16, 4);
>>> + TEST_VPADD(INSN_NAME, int, s, 32, 2);
>>> + TEST_VPADD(INSN_NAME, uint, u, 8, 8);
>>> + TEST_VPADD(INSN_NAME, uint, u, 16, 4);
>>> + TEST_VPADD(INSN_NAME, uint, u, 32, 2);
>>> + TEST_VPADD(INSN_NAME, float, f, 32, 2);
>>> +
>>> + CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
>>> + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
>>> + CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
>>> + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
>>> + CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
>>> +}
>>> +
>>> +int main (void)
>>> +{
>>> + FNNAME (INSN_NAME) ();
>>> + return 0;
>>> +}
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> new file mode 100644
>>> index 0000000..5ddfd3d
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
>>> @@ -0,0 +1,19 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +#define INSN_NAME vpadd
>>> +#define TEST_MSG "VPADD"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>>> + 0xe1, 0xe5, 0xe9, 0xed };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
>>> + 0xe1, 0xe5, 0xe9, 0xed };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
>>> +
>>> +#include "vpXXX.inc"
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> new file mode 100644
>>> index 0000000..f27a9a9
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
>>> @@ -0,0 +1,20 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +
>>> +#define INSN_NAME vpmax
>>> +#define TEST_MSG "VPMAX"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
>>> + 0xf1, 0xf3, 0xf5, 0xf7 };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
>>> +
>>> +#include "vpXXX.inc"
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> new file mode 100644
>>> index 0000000..a7cb696
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
>>> @@ -0,0 +1,20 @@
>>> +#include <arm_neon.h>
>>> +#include "arm-neon-ref.h"
>>> +#include "compute-ref-data.h"
>>> +
>>> +
>>> +#define INSN_NAME vpmin
>>> +#define TEST_MSG "VPMIN"
>>> +
>>> +/* Expected results. */
>>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
>>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
>>> + 0xf0, 0xf2, 0xf4, 0xf6 };
>>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2
>>> };
>>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
>>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
>>> +
>>> +#include "vpXXX.inc"
>>>
>>
>> Otherwise LGTM.
>>
>> Tejas.
>>
[-- Attachment #2: 0017-Add-vpadd-vpmax-and-vpmin-tests.patch --]
[-- Type: text/x-patch, Size: 5887 bytes --]
From 3a8d5a974d49332cd4de6675aa0d58501b967518 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Tue, 9 Dec 2014 22:27:01 +0100
Subject: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
new file mode 100644
index 0000000..c1b7235
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc
@@ -0,0 +1,67 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPXXX1(INSN, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector, T1, W, N)); \
+ vst1##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VPXXX(INSN, T1, T2, W, N) \
+ TEST_VPXXX1(INSN, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, float, 32, 2);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, float, 32, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+
+ /* Apply a binary operator named INSN_NAME. */
+ TEST_VPXXX(INSN_NAME, int, s, 8, 8);
+ TEST_VPXXX(INSN_NAME, int, s, 16, 4);
+ TEST_VPXXX(INSN_NAME, int, s, 32, 2);
+ TEST_VPXXX(INSN_NAME, uint, u, 8, 8);
+ TEST_VPXXX(INSN_NAME, uint, u, 16, 4);
+ TEST_VPXXX(INSN_NAME, uint, u, 32, 2);
+ TEST_VPXXX(INSN_NAME, float, f, 32, 2);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
new file mode 100644
index 0000000..5ddfd3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadd.c
@@ -0,0 +1,19 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vpadd
+#define TEST_MSG "VPADD"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xe1, 0xe5, 0xe9, 0xed,
+ 0xe1, 0xe5, 0xe9, 0xed };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffe1, 0xffe5, 0xffe1, 0xffe5 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffe1, 0xffffffe1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1f80000, 0xc1f80000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
new file mode 100644
index 0000000..f27a9a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmax.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmax
+#define TEST_MSG "VPMAX"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7,
+ 0xf1, 0xf3, 0xf5, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff3, 0xfff1, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 };
+
+#include "vpXXX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
new file mode 100644
index 0000000..a7cb696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpmin.c
@@ -0,0 +1,20 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+
+#define INSN_NAME vpmin
+#define TEST_MSG "VPMIN"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf2, 0xf4, 0xf6,
+ 0xf0, 0xf2, 0xf4, 0xf6 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff2, 0xfff0, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 };
+
+#include "vpXXX.inc"
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
2015-01-16 18:18 ` Tejas Belagod
@ 2015-01-20 15:35 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:35 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 3610 bytes --]
On 16 January 2015 at 19:15, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file.
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> new file mode 100644
>> index 0000000..427c9ba
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> @@ -0,0 +1,77 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
>> + 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3
>> };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>
>
> No poly or float for vmovl.
>
Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2
variants are necessary.
> Otherwise, LGTM.
>
> Tejas.
>
>
[-- Attachment #2: 0021-Add-vmovl-tests.patch --]
[-- Type: text/x-patch, Size: 2271 bytes --]
From 2f56acd54cee2d9b9b62de9e624fb2a64f114101 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed, 10 Dec 2014 17:24:48 +0100
Subject: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
new file mode 100644
index 0000000..fd94d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
+
+#define TEST_MSG "VMOVL"
+void exec_vmovl (void)
+{
+ /* Basic test: vec128=vmovl(vec64), then store the result. */
+#define TEST_VMOVL(T1, T2, W, W2, N) \
+ VECT_VAR(vector128, T1, W2, N) = \
+ vmovl_##T2##W(VECT_VAR(vector64, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector128, T1, W2, N))
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector128);
+
+ TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64, buffer);
+
+ clean_results ();
+
+ TEST_VMOVL(int, s, 8, 16, 8);
+ TEST_VMOVL(int, s, 16, 32, 4);
+ TEST_VMOVL(int, s, 32, 64, 2);
+ TEST_VMOVL(uint, u, 8, 16, 8);
+ TEST_VMOVL(uint, u, 16, 32, 4);
+ TEST_VMOVL(uint, u, 32, 64, 2);
+
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vmovl ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 28/36] Add vmnv tests.
2015-01-16 18:39 ` Tejas Belagod
@ 2015-01-20 15:36 ` Christophe Lyon
2015-01-26 14:30 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:36 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 499 bytes --]
On 16 January 2015 at 19:27, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>
>
> No float or poly16 for vmvn_*.
>
Updated as attached, removed 64x1 and 64x2 too.
> Otherwise, LGTM.
>
> Tejas.
>
>
[-- Attachment #2: 0028-Add-vmnv-tests.patch --]
[-- Type: text/x-patch, Size: 5799 bytes --]
From f4902098b0379fd445ceda7d2202b93f56c6129f Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed, 10 Dec 2014 23:07:25 +0100
Subject: [[ARM/AArch64][testsuite] 28/36] Add vmnv tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
new file mode 100644
index 0000000..268a707
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmvn.c
@@ -0,0 +1,137 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xf, 0xe };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xf, 0xe };
+VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xf, 0xe, 0xd, 0xc };
+VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf, 0xe, 0xd, 0xc,
+ 0xb, 0xa, 0x9, 0x8,
+ 0x7, 0x6, 0x5, 0x4,
+ 0x3, 0x2, 0x1, 0x0 };
+
+#define INSN_NAME vmvn
+#define TEST_MSG "VMVN/VMVNQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_UNARY_OP(INSN, Q, T1, T2, W, N) \
+ TEST_UNARY_OP1(INSN, Q, T1, T2, W, N) \
+
+ /* No need for 64 bits variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, poly, 8, 8);
+ DECL_VARIABLE(vector, int, 8, 16);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, uint, 8, 16);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, poly, 8, 16);
+
+ DECL_VARIABLE(vector_res, int, 8, 8);
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 8, 8);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, poly, 8, 8);
+ DECL_VARIABLE(vector_res, int, 8, 16);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 8, 16);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, poly, 8, 16);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , poly, p, 8, 8);
+ VLOAD(vector, buffer, q, int, s, 8, 16);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 8, 16);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, poly, p, 8, 16);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_UNARY_OP(INSN_NAME, , int, s, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, , int, s, 16, 4);
+ TEST_UNARY_OP(INSN_NAME, , int, s, 32, 2);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 16, 4);
+ TEST_UNARY_OP(INSN_NAME, , uint, u, 32, 2);
+ TEST_UNARY_OP(INSN_NAME, , poly, p, 8, 8);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 8, 16);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 16, 8);
+ TEST_UNARY_OP(INSN_NAME, q, int, s, 32, 4);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 8, 16);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 16, 8);
+ TEST_UNARY_OP(INSN_NAME, q, uint, u, 32, 4);
+ TEST_UNARY_OP(INSN_NAME, q, poly, p, 8, 16);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, "");
+}
+
+int main (void)
+{
+ exec_vmvn ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 29/36] Add vpadal tests.
2015-01-16 18:41 ` Tejas Belagod
@ 2015-01-20 15:39 ` Christophe Lyon
2015-01-26 14:34 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:39 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 795 bytes --]
On 16 January 2015 at 19:29, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>
>
> No float or poly ops for VPADAL insns.
>
int8 variants are not necessary either, updated as attached.
> Otherwise, LGTM.
>
> Tejas.
>
>
[-- Attachment #2: 0029-Add-vpadal-tests.patch --]
[-- Type: text/x-patch, Size: 6220 bytes --]
From 15f312aaaa9b408c6e70af3f78cf18ffc340d361 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed, 10 Dec 2014 23:21:27 +0100
Subject: [[ARM/AArch64][testsuite] 29/36] Add vpadal tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
new file mode 100644
index 0000000..0bffc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpadal.c
@@ -0,0 +1,141 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffd1, 0xffd6, 0xffdb, 0xffe0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffd1, 0xffffffd6 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffd1 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1d1, 0x1d6, 0x1db, 0x1e0 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1ffd1, 0x1ffd6 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffd1 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffd1, 0xffd6, 0xffdb, 0xffe0,
+ 0xffe5, 0xffea, 0xffef, 0xfff4 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffd1, 0xffffffd6,
+ 0xffffffdb, 0xffffffe0 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffd1, 0xffffffffffffffd6 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1d1, 0x1d6, 0x1db, 0x1e0,
+ 0x1e5, 0x1ea, 0x1ef, 0x1f4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1ffd1, 0x1ffd6, 0x1ffdb, 0x1ffe0 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x1ffffffd1, 0x1ffffffd6 };
+
+#define INSN_NAME vpadal
+#define TEST_MSG "VPADAL/VPADALQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADAL1(INSN, Q, T1, T2, W, N, W2, N2) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W2, N2), VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VPADAL(INSN, Q, T1, T2, W, N, W2, N2) \
+ TEST_VPADAL1(INSN, Q, T1, T2, W, N, W2, N2)
+
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, int, 64, 1);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, uint, 64, 1);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, int, 64, 2);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+ DECL_VARIABLE(vector, uint, 64, 2);
+
+ DECL_VARIABLE(vector2, int, 8, 8);
+ DECL_VARIABLE(vector2, int, 16, 4);
+ DECL_VARIABLE(vector2, int, 32, 2);
+ DECL_VARIABLE(vector2, uint, 8, 8);
+ DECL_VARIABLE(vector2, uint, 16, 4);
+ DECL_VARIABLE(vector2, uint, 32, 2);
+ DECL_VARIABLE(vector2, int, 8, 16);
+ DECL_VARIABLE(vector2, int, 16, 8);
+ DECL_VARIABLE(vector2, int, 32, 4);
+ DECL_VARIABLE(vector2, uint, 8, 16);
+ DECL_VARIABLE(vector2, uint, 16, 8);
+ DECL_VARIABLE(vector2, uint, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 1);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 1);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , int, s, 64, 1);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 64, 1);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, int, s, 64, 2);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 64, 2);
+
+ /* Initialize input "vector2" from "buffer". */
+ VLOAD(vector2, buffer, , int, s, 8, 8);
+ VLOAD(vector2, buffer, , int, s, 16, 4);
+ VLOAD(vector2, buffer, , int, s, 32, 2);
+ VLOAD(vector2, buffer, , uint, u, 8, 8);
+ VLOAD(vector2, buffer, , uint, u, 16, 4);
+ VLOAD(vector2, buffer, , uint, u, 32, 2);
+ VLOAD(vector2, buffer, q, int, s, 8, 16);
+ VLOAD(vector2, buffer, q, int, s, 16, 8);
+ VLOAD(vector2, buffer, q, int, s, 32, 4);
+ VLOAD(vector2, buffer, q, uint, u, 8, 16);
+ VLOAD(vector2, buffer, q, uint, u, 16, 8);
+ VLOAD(vector2, buffer, q, uint, u, 32, 4);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADAL(INSN_NAME, , int, s, 8, 8, 16, 4);
+ TEST_VPADAL(INSN_NAME, , int, s, 16, 4, 32, 2);
+ TEST_VPADAL(INSN_NAME, , int, s, 32, 2, 64 ,1);
+ TEST_VPADAL(INSN_NAME, , uint, u, 8, 8, 16, 4);
+ TEST_VPADAL(INSN_NAME, , uint, u, 16, 4, 32, 2);
+ TEST_VPADAL(INSN_NAME, , uint, u, 32, 2, 64, 1);
+ TEST_VPADAL(INSN_NAME, q, int, s, 8, 16, 16, 8);
+ TEST_VPADAL(INSN_NAME, q, int, s, 16, 8, 32, 4);
+ TEST_VPADAL(INSN_NAME, q, int, s, 32, 4, 64 ,2);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
+ TEST_VPADAL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vpadal ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-16 20:34 ` Christophe Lyon
@ 2015-01-20 15:50 ` Christophe Lyon
2015-01-26 14:47 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 15:50 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 3427 bytes --]
On 16 January 2015 at 20:41, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 19:49, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> On 16 January 2015 at 19:33, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>
>>>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>>>> + 0x33, 0x33, 0x33, 0x33,
>>>> + 0x33, 0x33, 0x33, 0x33,
>>>> + 0x33, 0x33, 0x33, 0x33 };
>>>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>>>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>>>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>>>> + 0x33333333, 0x33333333 };
>>>> +
>>>
>>>
>>> No poly or float ops.
>>>
>>>> +#define INSN_NAME vpaddl
>>>> +#define TEST_MSG "VPADDL/VPADDLQ"
>>>> +
>>>> +#define FNNAME1(NAME) void exec_ ## NAME (void)
>>>> +#define FNNAME(NAME) FNNAME1(NAME)
>>>> +
>>>> +FNNAME (INSN_NAME)
>>>> +{
>>>> + /* Basic test: y=OP(x), then store the result. */
>>>> +#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
>>>> + VECT_VAR(vector_res, T1, W2, N2) = \
>>>> + INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
>>>> + vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
>>>> + VECT_VAR(vector_res, T1, W2, N2))
>>>> +
>>>> +#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
>>>> + TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
>>>> +
>>>> + /* No need for 64 bits variants. */
>>>
>>>
>>> These look like 64-bit variants.
>>>
>> I mean no vector element of 64 bits.
>>
>>>> + DECL_VARIABLE(vector, int, 8, 8);
>>>> + DECL_VARIABLE(vector, int, 16, 4);
>>>> + DECL_VARIABLE(vector, int, 32, 2);
>>>> + DECL_VARIABLE(vector, uint, 8, 8);
>>>> + DECL_VARIABLE(vector, uint, 16, 4);
>>>> + DECL_VARIABLE(vector, uint, 32, 2);
>>>> + DECL_VARIABLE(vector, int, 8, 16);
>>>> + DECL_VARIABLE(vector, int, 16, 8);
>>>> + DECL_VARIABLE(vector, int, 32, 4);
>>>> + DECL_VARIABLE(vector, uint, 8, 16);
>>>> + DECL_VARIABLE(vector, uint, 16, 8);
>>>> + DECL_VARIABLE(vector, uint, 32, 4);
>>>> +
>>>
>>>
>>>> + /* Apply a unary operator named INSN_NAME. */
>>>
>>> Unary op?
>>
>> Cut & paste error, again.
>>
> Hmm changed my mind: vpaddl takes only one vector as input, although
> it does add 2 vector elements.
>
Here is an updated version, removing poly, float and int8 variants.
>
>>>
>>>> + TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
>>>> + TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
>>>> + TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
>>>> + TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
>>>> + TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
>>>> + TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
>>>> + TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
>>>> + TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
>>>> + TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
>>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
>>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
>>>> + TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
>>>> +
>>>> + CHECK_RESULTS (TEST_MSG, "");
>>>> +}
>>>> +
>>>> +int main (void)
>>>> +{
>>>> + exec_vpaddl ();
>>>> + return 0;
>>>> +}
>>>>
>>>
>>>
>>> Otherwise, LGTM.
>>>
>>> Tejas.
>>>
[-- Attachment #2: 0030-Add-vpaddl-tests.patch --]
[-- Type: text/x-patch, Size: 5167 bytes --]
From 394f2023994b56413e3fc40412e9cc36ed0e05a7 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.lyon@linaro.org>
Date: Wed, 10 Dec 2014 23:31:29 +0100
Subject: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
new file mode 100644
index 0000000..8dc768d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vpaddl.c
@@ -0,0 +1,116 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffffe1, 0xffffffe5 };
+VECT_VAR_DECL(expected,int,64,1) [] = { 0xffffffffffffffe1 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x1e1, 0x1e5, 0x1e9, 0x1ed };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1ffe1, 0x1ffe5 };
+VECT_VAR_DECL(expected,uint,64,1) [] = { 0x1ffffffe1 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xffe1, 0xffe5, 0xffe9, 0xffed,
+ 0xfff1, 0xfff5, 0xfff9, 0xfffd };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffe1, 0xffffffe5,
+ 0xffffffe9, 0xffffffed };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffffffe1,
+ 0xffffffffffffffe5 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x1e1, 0x1e5, 0x1e9, 0x1ed,
+ 0x1f1, 0x1f5, 0x1f9, 0x1fd };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x1ffe1, 0x1ffe5, 0x1ffe9, 0x1ffed };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0x1ffffffe1, 0x1ffffffe5 };
+
+#define INSN_NAME vpaddl
+#define TEST_MSG "VPADDL/VPADDLQ"
+
+#define FNNAME1(NAME) void exec_ ## NAME (void)
+#define FNNAME(NAME) FNNAME1(NAME)
+
+FNNAME (INSN_NAME)
+{
+ /* Basic test: y=OP(x), then store the result. */
+#define TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2) \
+ VECT_VAR(vector_res, T1, W2, N2) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \
+ vst1##Q##_##T2##W2(VECT_VAR(result, T1, W2, N2), \
+ VECT_VAR(vector_res, T1, W2, N2))
+
+#define TEST_VPADDL(INSN, Q, T1, T2, W, N, W2, N2) \
+ TEST_VPADDL1(INSN, Q, T1, T2, W, N, W2, N2)
+
+ /* No need for 64 bits elements variants. */
+ DECL_VARIABLE(vector, int, 8, 8);
+ DECL_VARIABLE(vector, int, 16, 4);
+ DECL_VARIABLE(vector, int, 32, 2);
+ DECL_VARIABLE(vector, uint, 8, 8);
+ DECL_VARIABLE(vector, uint, 16, 4);
+ DECL_VARIABLE(vector, uint, 32, 2);
+ DECL_VARIABLE(vector, int, 8, 16);
+ DECL_VARIABLE(vector, int, 16, 8);
+ DECL_VARIABLE(vector, int, 32, 4);
+ DECL_VARIABLE(vector, uint, 8, 16);
+ DECL_VARIABLE(vector, uint, 16, 8);
+ DECL_VARIABLE(vector, uint, 32, 4);
+
+ DECL_VARIABLE(vector_res, int, 16, 4);
+ DECL_VARIABLE(vector_res, int, 32, 2);
+ DECL_VARIABLE(vector_res, int, 64, 1);
+ DECL_VARIABLE(vector_res, uint, 16, 4);
+ DECL_VARIABLE(vector_res, uint, 32, 2);
+ DECL_VARIABLE(vector_res, uint, 64, 1);
+ DECL_VARIABLE(vector_res, int, 16, 8);
+ DECL_VARIABLE(vector_res, int, 32, 4);
+ DECL_VARIABLE(vector_res, int, 64, 2);
+ DECL_VARIABLE(vector_res, uint, 16, 8);
+ DECL_VARIABLE(vector_res, uint, 32, 4);
+ DECL_VARIABLE(vector_res, uint, 64, 2);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ VLOAD(vector, buffer, , int, s, 8, 8);
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 8, 8);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 8, 16);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 8, 16);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+
+ /* Apply a unary operator named INSN_NAME. */
+ TEST_VPADDL(INSN_NAME, , int, s, 8, 8, 16, 4);
+ TEST_VPADDL(INSN_NAME, , int, s, 16, 4, 32, 2);
+ TEST_VPADDL(INSN_NAME, , int, s, 32, 2, 64, 1);
+ TEST_VPADDL(INSN_NAME, , uint, u, 8, 8, 16, 4);
+ TEST_VPADDL(INSN_NAME, , uint, u, 16, 4, 32, 2);
+ TEST_VPADDL(INSN_NAME, , uint, u, 32, 2, 64, 1);
+ TEST_VPADDL(INSN_NAME, q, int, s, 8, 16, 16, 8);
+ TEST_VPADDL(INSN_NAME, q, int, s, 16, 8, 32, 4);
+ TEST_VPADDL(INSN_NAME, q, int, s, 32, 4, 64, 2);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 8, 16, 16, 8);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 16, 8, 32, 4);
+ TEST_VPADDL(INSN_NAME, q, uint, u, 32, 4, 64, 2);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vpaddl ();
+ return 0;
+}
--
2.1.0
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests.
2015-01-19 13:42 ` Marcus Shawcroft
@ 2015-01-20 22:23 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-20 22:23 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 545 bytes --]
On 19 January 2015 at 14:35, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
>
> OK with the the vmlx poly ops dropped /M
Thanks, here is what I have committed (I removed the 64 bits elements
vectors, in addition to the poly ones).
Christophe
[-- Attachment #2: vmlX.patch --]
[-- Type: text/x-patch, Size: 9145 bytes --]
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog (revision 219916)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -1,5 +1,11 @@
2015-01-20 Christophe Lyon <christophe.lyon@linaro.org>
+ * gcc.target/aarch64/advsimd-intrinsics/vmlX.inc: New file.
+ * gcc.target/aarch64/advsimd-intrinsics/vmla.c: New file.
+ * gcc.target/aarch64/advsimd-intrinsics/vmls.c: New file.
+
+2015-01-20 Christophe Lyon <christophe.lyon@linaro.org>
+
* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: New file.
2015-01-20 Jakub Jelinek <jakub@redhat.com>
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX.inc (working copy)
@@ -0,0 +1,123 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX(T, W, N) \
+ DECL_VARIABLE(vector1, T, W, N); \
+ DECL_VARIABLE(vector2, T, W, N); \
+ DECL_VARIABLE(vector3, T, W, N); \
+ DECL_VARIABLE(vector_res, T, W, N)
+
+ /* vector_res = vmla(vector, vector3, vector4),
+ then store the result. */
+#define TEST_VMLX1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector1, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ VECT_VAR(vector3, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX(INSN, Q, T1, T2, W, N) \
+ TEST_VMLX1(INSN, Q, T1, T2, W, N)
+
+ DECL_VMLX(int, 8, 8);
+ DECL_VMLX(int, 16, 4);
+ DECL_VMLX(int, 32, 2);
+ DECL_VMLX(uint, 8, 8);
+ DECL_VMLX(uint, 16, 4);
+ DECL_VMLX(uint, 32, 2);
+ DECL_VMLX(float, 32, 2);
+ DECL_VMLX(int, 8, 16);
+ DECL_VMLX(int, 16, 8);
+ DECL_VMLX(int, 32, 4);
+ DECL_VMLX(uint, 8, 16);
+ DECL_VMLX(uint, 16, 8);
+ DECL_VMLX(uint, 32, 4);
+ DECL_VMLX(float, 32, 4);
+
+ clean_results ();
+
+ VLOAD(vector1, buffer, , int, s, 8, 8);
+ VLOAD(vector1, buffer, , int, s, 16, 4);
+ VLOAD(vector1, buffer, , int, s, 32, 2);
+ VLOAD(vector1, buffer, , uint, u, 8, 8);
+ VLOAD(vector1, buffer, , uint, u, 16, 4);
+ VLOAD(vector1, buffer, , uint, u, 32, 2);
+ VLOAD(vector1, buffer, , float, f, 32, 2);
+ VLOAD(vector1, buffer, q, int, s, 8, 16);
+ VLOAD(vector1, buffer, q, int, s, 16, 8);
+ VLOAD(vector1, buffer, q, int, s, 32, 4);
+ VLOAD(vector1, buffer, q, uint, u, 8, 16);
+ VLOAD(vector1, buffer, q, uint, u, 16, 8);
+ VLOAD(vector1, buffer, q, uint, u, 32, 4);
+ VLOAD(vector1, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 8, 8, 0x11);
+ VDUP(vector2, , int, s, 16, 4, 0x22);
+ VDUP(vector2, , int, s, 32, 2, 0x33);
+ VDUP(vector2, , uint, u, 8, 8, 0x44);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x66);
+ VDUP(vector2, , float, f, 32, 2, 33.1f);
+ VDUP(vector2, q, int, s, 8, 16, 0x77);
+ VDUP(vector2, q, int, s, 16, 8, 0x88);
+ VDUP(vector2, q, int, s, 32, 4, 0x99);
+ VDUP(vector2, q, uint, u, 8, 16, 0xAA);
+ VDUP(vector2, q, uint, u, 16, 8, 0xBB);
+ VDUP(vector2, q, uint, u, 32, 4, 0xCC);
+ VDUP(vector2, q, float, f, 32, 4, 99.2f);
+
+ VDUP(vector3, , int, s, 8, 8, 0xFF);
+ VDUP(vector3, , int, s, 16, 4, 0xEE);
+ VDUP(vector3, , int, s, 32, 2, 0xDD);
+ VDUP(vector3, , uint, u, 8, 8, 0xCC);
+ VDUP(vector3, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0xAA);
+ VDUP(vector3, , float, f, 32, 2, 10.23f);
+ VDUP(vector3, q, int, s, 8, 16, 0x99);
+ VDUP(vector3, q, int, s, 16, 8, 0x88);
+ VDUP(vector3, q, int, s, 32, 4, 0x77);
+ VDUP(vector3, q, uint, u, 8, 16, 0x66);
+ VDUP(vector3, q, uint, u, 16, 8, 0x55);
+ VDUP(vector3, q, uint, u, 32, 4, 0x44);
+ VDUP(vector3, q, float, f, 32, 4, 77.8f);
+
+ TEST_VMLX(INSN_NAME, , int, s, 8, 8);
+ TEST_VMLX(INSN_NAME, , int, s, 16, 4);
+ TEST_VMLX(INSN_NAME, , int, s, 32, 2);
+ TEST_VMLX(INSN_NAME, , uint, u, 8, 8);
+ TEST_VMLX(INSN_NAME, , uint, u, 16, 4);
+ TEST_VMLX(INSN_NAME, , uint, u, 32, 2);
+ TEST_VMLX(INSN_NAME, , float, f, 32, 2);
+ TEST_VMLX(INSN_NAME, q, int, s, 8, 16);
+ TEST_VMLX(INSN_NAME, q, int, s, 16, 8);
+ TEST_VMLX(INSN_NAME, q, int, s, 32, 4);
+ TEST_VMLX(INSN_NAME, q, uint, u, 8, 16);
+ TEST_VMLX(INSN_NAME, q, uint, u, 16, 8);
+ TEST_VMLX(INSN_NAME, q, uint, u, 32, 4);
+ TEST_VMLX(INSN_NAME, q, float, f, 32, 4);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
+
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla.c (working copy)
@@ -0,0 +1,35 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xdf, 0xe0, 0xe1, 0xe2,
+ 0xe3, 0xe4, 0xe5, 0xe6 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x1f8c, 0x1f8d, 0x1f8e, 0x1f8f };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x2bf7, 0x2bf8 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0x20, 0x21, 0x22, 0x23,
+ 0x24, 0x25, 0x26, 0x27 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x43ac, 0x43ad };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x43a14e76, 0x43a1ce76 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf, 0x10, 0x11, 0x12,
+ 0x13, 0x14, 0x15, 0x16,
+ 0x17, 0x18, 0x19, 0x1a,
+ 0x1b, 0x1c, 0x1d, 0x1e };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x4830, 0x4831, 0x4832, 0x4833,
+ 0x4834, 0x4835, 0x4836, 0x4837 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x470f, 0x4710, 0x4711, 0x4712 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xac, 0xad, 0xae, 0xaf,
+ 0xb0, 0xb1, 0xb2, 0xb3,
+ 0xb4, 0xb5, 0xb6, 0xb7,
+ 0xb8, 0xb9, 0xba, 0xbb };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3620, 0x3621, 0x3622, 0x3623 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x45f0ae15, 0x45f0b615,
+ 0x45f0be15, 0x45f0c615 };
+
+#include "vmlX.inc"
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls.c (working copy)
@@ -0,0 +1,37 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0x1, 0x2, 0x3, 0x4,
+ 0x5, 0x6, 0x7, 0x8 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xe054, 0xe055, 0xe056, 0xe057 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffd3e9, 0xffffd3ea };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xc0, 0xc1, 0xc2, 0xc3,
+ 0xc4, 0xc5, 0xc6, 0xc7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffbc34, 0xffffbc35 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc3b14e76, 0xc3b0ce76 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xd1, 0xd2, 0xd3, 0xd4,
+ 0xd5, 0xd6, 0xd7, 0xd8,
+ 0xd9, 0xda, 0xdb, 0xdc,
+ 0xdd, 0xde, 0xdf, 0xe0 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xb7b0, 0xb7b1, 0xb7b2, 0xb7b3,
+ 0xb7b4, 0xb7b5, 0xb7b6, 0xb7b7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffb8d1, 0xffffb8d2,
+ 0xffffb8d3, 0xffffb8d4 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0x34, 0x35, 0x36, 0x37,
+ 0x38, 0x39, 0x3a, 0x3b,
+ 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x40, 0x41, 0x42, 0x43 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc9c0, 0xffffc9c1,
+ 0xffffc9c2, 0xffffc9c3 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc5f1ae15, 0xc5f1a615,
+ 0xc5f19e15, 0xc5f19615 };
+
+#include "vmlX.inc"
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests.
2015-01-19 13:43 ` Marcus Shawcroft
@ 2015-01-21 0:02 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-21 0:02 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 524 bytes --]
On 19 January 2015 at 14:39, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 13 January 2015 at 15:18, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c: New file.
>
> OK with Tejas' comment addressed. /Marcus
Here is what I have committed (removed poly, int8 and int64 variants).
Christophe.
[-- Attachment #2: vmlX_lane.patch --]
[-- Type: text/x-patch, Size: 6738 bytes --]
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlX_lane.inc (working copy)
@@ -0,0 +1,100 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+#define DECL_VMLX_LANE(VAR) \
+ DECL_VARIABLE(VAR, int, 16, 4); \
+ DECL_VARIABLE(VAR, int, 32, 2); \
+ DECL_VARIABLE(VAR, uint, 16, 4); \
+ DECL_VARIABLE(VAR, uint, 32, 2); \
+ DECL_VARIABLE(VAR, float, 32, 2); \
+ DECL_VARIABLE(VAR, int, 16, 8); \
+ DECL_VARIABLE(VAR, int, 32, 4); \
+ DECL_VARIABLE(VAR, uint, 16, 8); \
+ DECL_VARIABLE(VAR, uint, 32, 4); \
+ DECL_VARIABLE(VAR, float, 32, 4)
+
+ /* vector_res = vmlx_lane(vector, vector2, vector3, lane),
+ then store the result. */
+#define TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, L) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N), \
+ VECT_VAR(vector3, T1, W, N2), \
+ L); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
+ VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_VMLX_LANE(INSN, Q, T1, T2, W, N, N2, V) \
+ TEST_VMLX_LANE1(INSN, Q, T1, T2, W, N, N2, V)
+
+ DECL_VMLX_LANE(vector);
+ DECL_VMLX_LANE(vector2);
+ DECL_VMLX_LANE(vector_res);
+
+ DECL_VARIABLE(vector3, int, 16, 4);
+ DECL_VARIABLE(vector3, int, 32, 2);
+ DECL_VARIABLE(vector3, uint, 16, 4);
+ DECL_VARIABLE(vector3, uint, 32, 2);
+ DECL_VARIABLE(vector3, float, 32, 2);
+
+ clean_results ();
+
+ VLOAD(vector, buffer, , int, s, 16, 4);
+ VLOAD(vector, buffer, , int, s, 32, 2);
+ VLOAD(vector, buffer, , uint, u, 16, 4);
+ VLOAD(vector, buffer, , uint, u, 32, 2);
+ VLOAD(vector, buffer, q, int, s, 16, 8);
+ VLOAD(vector, buffer, q, int, s, 32, 4);
+ VLOAD(vector, buffer, q, uint, u, 16, 8);
+ VLOAD(vector, buffer, q, uint, u, 32, 4);
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+
+ VDUP(vector2, , int, s, 16, 4, 0x55);
+ VDUP(vector2, , int, s, 32, 2, 0x55);
+ VDUP(vector2, , uint, u, 16, 4, 0x55);
+ VDUP(vector2, , uint, u, 32, 2, 0x55);
+ VDUP(vector2, , float, f, 32, 2, 55.3f);
+ VDUP(vector2, q, int, s, 16, 8, 0x55);
+ VDUP(vector2, q, int, s, 32, 4, 0x55);
+ VDUP(vector2, q, uint, u, 16, 8, 0x55);
+ VDUP(vector2, q, uint, u, 32, 4, 0x55);
+ VDUP(vector2, q, float, f, 32, 4, 55.8f);
+
+ VDUP(vector3, , int, s, 16, 4, 0xBB);
+ VDUP(vector3, , int, s, 32, 2, 0xBB);
+ VDUP(vector3, , uint, u, 16, 4, 0xBB);
+ VDUP(vector3, , uint, u, 32, 2, 0xBB);
+ VDUP(vector3, , float, f, 32, 2, 11.34f);
+
+ /* Choose lane arbitrarily. */
+ TEST_VMLX_LANE(INSN_NAME, , int, s, 16, 4, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, , int, s, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, , uint, u, 16, 4, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, , uint, u, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, , float, f, 32, 2, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, int, s, 16, 8, 4, 3);
+ TEST_VMLX_LANE(INSN_NAME, q, int, s, 32, 4, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, uint, u, 16, 8, 4, 2);
+ TEST_VMLX_LANE(INSN_NAME, q, uint, u, 32, 4, 2, 1);
+ TEST_VMLX_LANE(INSN_NAME, q, float, f, 32, 4, 2, 1);
+
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_lane.c (working copy)
@@ -0,0 +1,23 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmla
+#define TEST_MSG "VMLA_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3e07, 0x3e08 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4418c687, 0x44190687 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a,
+ 0x3e0b, 0x3e0c, 0x3e0d, 0x3e0e };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0x3e07, 0x3e08, 0x3e09, 0x3e0a };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x441a3168, 0x441a7168,
+ 0x441ab168, 0x441af168 };
+
+#include "vmlX_lane.inc"
Index: gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_lane.c (working copy)
@@ -0,0 +1,25 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmls
+#define TEST_MSG "VMLS_LANE"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xffffc1d9, 0xffffc1da };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffc1d9, 0xffffc1da };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc420c687, 0xc4208687 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xc1d9, 0xc1da, 0xc1db, 0xc1dc,
+ 0xc1dd, 0xc1de, 0xc1df, 0xc1e0 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffc1d9, 0xffffc1da,
+ 0xffffc1db, 0xffffc1dc };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc4223168, 0xc421f168,
+ 0xc421b168, 0xc4217168 };
+
+#include "vmlX_lane.inc"
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-19 17:33 ` Marcus Shawcroft
@ 2015-01-21 16:35 ` Christophe Lyon
2015-01-22 12:37 ` Tejas Belagod
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-21 16:35 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
On 19 January 2015 at 17:54, Marcus Shawcroft
<marcus.shawcroft@gmail.com> wrote:
> On 19 January 2015 at 15:43, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> On 19 January 2015 at 14:29, Marcus Shawcroft
>> <marcus.shawcroft@gmail.com> wrote:
>>> On 16 January 2015 at 17:52, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>>
>>>>> OK provided, as per the previous couple, that we don;t regression or
>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>
>>>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>>>> when the input is -NaN.
>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>> should the same as on aarch32.
>>>> I haven't had time to look at it in more details though.
>>>> So, not OK?
>>>
>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>> test on HW or a model?
>>>
>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>> foundation model for aarch64*-elf.
>
> Leave this one out until we understand why it fails. /Marcus
I've looked at this a bit more.
We have
fmax v0.4s, v0.4s, v1.4s
where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
The output is still -NaN (0xffc00000), while the test expects
defaultNaN (0x7fc00000).
I have executed the test under GDB on AArch64 HW, and noticed that fpcr was 0.
I forced it to have DN==1:
set $fpcr=0x1000000
but this didn't change the result.
Does setting fpcr.dn under gdb actually work?
Christophe.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-21 16:35 ` Christophe Lyon
@ 2015-01-22 12:37 ` Tejas Belagod
2015-01-22 14:42 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-22 12:37 UTC (permalink / raw)
To: Christophe Lyon, Marcus Shawcroft; +Cc: gcc-patches
On 21/01/15 15:07, Christophe Lyon wrote:
> On 19 January 2015 at 17:54, Marcus Shawcroft
> <marcus.shawcroft@gmail.com> wrote:
>> On 19 January 2015 at 15:43, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>> <marcus.shawcroft@gmail.com> wrote:
>>>> On 16 January 2015 at 17:52, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>>>
>>>>>> OK provided, as per the previous couple, that we don;t regression or
>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>
>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>>>>> when the input is -NaN.
>>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>>> should the same as on aarch32.
>>>>> I haven't had time to look at it in more details though.
>>>>> So, not OK?
>>>>
>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>> test on HW or a model?
>>>>
>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>> foundation model for aarch64*-elf.
>>
>> Leave this one out until we understand why it fails. /Marcus
>
> I've looked at this a bit more.
> We have
> fmax v0.4s, v0.4s, v1.4s
> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>
> The output is still -NaN (0xffc00000), while the test expects
> defaultNaN (0x7fc00000).
>
In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
the DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
AArch64 execution state, result of Advanced SIMD FP arithmetic
operations depend on the value of the DN-bit i.e. either propagate the
input NaN or generate DefaultNaN depending on the value of DN.
If you're running your test in the AArch64 execution state, you'd want
to define the DN bit and modify the expected results accordingly or have
the test poll at runtime what the DN-bit is set to and check expected
results dynamically.
I think the test already has expected behaviour for AArch32 execution
state by expecting DefaultNaN regardless.
> I have executed the test under GDB on AArch64 HW, and noticed that fpcr was 0.
> I forced it to have DN==1:
> set $fpcr=0x1000000
> but this didn't change the result.
>
> Does setting fpcr.dn under gdb actually work?
>
It should. Possibly a bug, patches welcome :-).
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-22 12:37 ` Tejas Belagod
@ 2015-01-22 14:42 ` Christophe Lyon
2015-01-22 15:58 ` Tejas Belagod
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-22 14:42 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 21/01/15 15:07, Christophe Lyon wrote:
>>
>> On 19 January 2015 at 17:54, Marcus Shawcroft
>> <marcus.shawcroft@gmail.com> wrote:
>>>
>>> On 19 January 2015 at 15:43, Christophe Lyon <christophe.lyon@linaro.org>
>>> wrote:
>>>>
>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>
>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>
>>>>>>> OK provided, as per the previous couple, that we don;t regression or
>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>
>>>>>>
>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>>>>>> when the input is -NaN.
>>>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>>>> should the same as on aarch32.
>>>>>> I haven't had time to look at it in more details though.
>>>>>> So, not OK?
>>>>>
>>>>>
>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>> test on HW or a model?
>>>>>
>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>> foundation model for aarch64*-elf.
>>>
>>>
>>> Leave this one out until we understand why it fails. /Marcus
>>
>>
>> I've looked at this a bit more.
>> We have
>> fmax v0.4s, v0.4s, v1.4s
>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>
>> The output is still -NaN (0xffc00000), while the test expects
>> defaultNaN (0x7fc00000).
>>
>
> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses the
> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In AArch64
> execution state, result of Advanced SIMD FP arithmetic operations depend on
> the value of the DN-bit i.e. either propagate the input NaN or generate
> DefaultNaN depending on the value of DN.
Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
can see only the latter (no diff between aarch32 and aarch64 in
FPProcessNan pseudo-code)
> If you're running your test in the AArch64 execution state, you'd want to
> define the DN bit and modify the expected results accordingly or have the
> test poll at runtime what the DN-bit is set to and check expected results
> dynamically.
Makes sense, I hadn't noticed the different aarch64 spec here.
> I think the test already has expected behaviour for AArch32 execution state
> by expecting DefaultNaN regardless.
Yes.
>> I have executed the test under GDB on AArch64 HW, and noticed that fpcr
>> was 0.
>> I forced it to have DN==1:
>> set $fpcr=0x1000000
>> but this didn't change the result.
>>
>> Does setting fpcr.dn under gdb actually work?
>>
>
> It should. Possibly a bug, patches welcome :-).
>
:-)
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-22 14:42 ` Christophe Lyon
@ 2015-01-22 15:58 ` Tejas Belagod
2015-01-22 23:10 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-22 15:58 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Marcus Shawcroft, gcc-patches
On 22/01/15 14:28, Christophe Lyon wrote:
> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>
>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>> <marcus.shawcroft@gmail.com> wrote:
>>>>
>>>> On 19 January 2015 at 15:43, Christophe Lyon <christophe.lyon@linaro.org>
>>>> wrote:
>>>>>
>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>
>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>
>>>>>>>> OK provided, as per the previous couple, that we don;t regression or
>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>
>>>>>>>
>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and vmin
>>>>>>> when the input is -NaN.
>>>>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>>>>> should the same as on aarch32.
>>>>>>> I haven't had time to look at it in more details though.
>>>>>>> So, not OK?
>>>>>>
>>>>>>
>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>> test on HW or a model?
>>>>>>
>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>> foundation model for aarch64*-elf.
>>>>
>>>>
>>>> Leave this one out until we understand why it fails. /Marcus
>>>
>>>
>>> I've looked at this a bit more.
>>> We have
>>> fmax v0.4s, v0.4s, v1.4s
>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>
>>> The output is still -NaN (0xffc00000), while the test expects
>>> defaultNaN (0x7fc00000).
>>>
>>
>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses the
>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In AArch64
>> execution state, result of Advanced SIMD FP arithmetic operations depend on
>> the value of the DN-bit i.e. either propagate the input NaN or generate
>> DefaultNaN depending on the value of DN.
>
> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
> can see only the latter (no diff between aarch32 and aarch64 in
> FPProcessNan pseudo-code)
>
If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
under DN:
"The value of this bit only controls scalar floating-point arithmetic.
Advanced SIMD arithmetic always uses the Default NaN setting, regardless
of the value of the DN bit."
Also on page 3180 for the description of VMAX(vector FP), it says:
"
* max(+0.0, -0.0) = +0.0
* If any input is a NaN, the corresponding result element is the default
NaN.
"
The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
FPMax() which is on pg. 2285
// StandardFPSCRValue()
// ====================
FPCRType StandardFPSCRValue()
return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
Here bit-25(FPSCR.DN) is set to 1.
Thanks,
Tejas.
>> If you're running your test in the AArch64 execution state, you'd want to
>> define the DN bit and modify the expected results accordingly or have the
>> test poll at runtime what the DN-bit is set to and check expected results
>> dynamically.
> Makes sense, I hadn't noticed the different aarch64 spec here.
>
>> I think the test already has expected behaviour for AArch32 execution state
>> by expecting DefaultNaN regardless.
> Yes.
>
>>> I have executed the test under GDB on AArch64 HW, and noticed that fpcr
>>> was 0.
>>> I forced it to have DN==1:
>>> set $fpcr=0x1000000
>>> but this didn't change the result.
>>>
>>> Does setting fpcr.dn under gdb actually work?
>>>
>>
>> It should. Possibly a bug, patches welcome :-).
>>
> :-)
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
@ 2015-01-22 16:32 ` Tejas Belagod
2015-01-22 22:23 ` Christophe Lyon
1 sibling, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-22 16:32 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
>>>
>>
>> LGTM.
>>
> Thanks, I should mention that this test fails on aarch64_be, because
> of pending Alan's patches.
A few big-endian fixes were checked in last night. Do you mean this?
r219957 | rsandifo | 2015-01-21 17:53:04 +0000 (Wed, 21 Jan 2015) | 6 lines
gcc/
2015-01-25 Alan Hayward <alan.hayward@arm.com>
* rtlanal.c (subreg_get_info): Exit early for simple and common
cases.
Thanks,
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test.
2015-01-22 16:32 ` Tejas Belagod
@ 2015-01-22 22:23 ` Christophe Lyon
0 siblings, 0 replies; 144+ messages in thread
From: Christophe Lyon @ 2015-01-22 22:23 UTC (permalink / raw)
To: Tejas Belagod; +Cc: gcc-patches
On 22 January 2015 at 17:17, Tejas Belagod <tejas.belagod@arm.com> wrote:
>
>>>>
>>>
>>> LGTM.
>>>
>> Thanks, I should mention that this test fails on aarch64_be, because
>> of pending Alan's patches.
>
>
> A few big-endian fixes were checked in last night. Do you mean this?
>
> r219957 | rsandifo | 2015-01-21 17:53:04 +0000 (Wed, 21 Jan 2015) | 6 lines
>
> gcc/
> 2015-01-25 Alan Hayward <alan.hayward@arm.com>
>
> * rtlanal.c (subreg_get_info): Exit early for simple and common
> cases.
>
Yes. I committed my test as r219914 and saw my automatic validation
results as FAIL for aarch64_be.
I expect them to move to PASS when r219957 will be validated. If not,
I'll let you know :-)
>
> Thanks,
> Tejas.
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-22 15:58 ` Tejas Belagod
@ 2015-01-22 23:10 ` Christophe Lyon
2015-01-23 11:02 ` Tejas Belagod
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-22 23:10 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 22/01/15 14:28, Christophe Lyon wrote:
>>
>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>
>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>
>>>>
>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>
>>>>>
>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>> <christophe.lyon@linaro.org>
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>
>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>> or
>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>> vmin
>>>>>>>> when the input is -NaN.
>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>>>>>> should the same as on aarch32.
>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>> So, not OK?
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>> test on HW or a model?
>>>>>>>
>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>> foundation model for aarch64*-elf.
>>>>>
>>>>>
>>>>>
>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>
>>>>
>>>>
>>>> I've looked at this a bit more.
>>>> We have
>>>> fmax v0.4s, v0.4s, v1.4s
>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>
>>>> The output is still -NaN (0xffc00000), while the test expects
>>>> defaultNaN (0x7fc00000).
>>>>
>>>
>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>> the
>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>> AArch64
>>> execution state, result of Advanced SIMD FP arithmetic operations depend
>>> on
>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>> DefaultNaN depending on the value of DN.
>>
>>
>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>> can see only the latter (no diff between aarch32 and aarch64 in
>> FPProcessNan pseudo-code)
>>
>
> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
> under DN:
>
> "The value of this bit only controls scalar floating-point arithmetic.
> Advanced SIMD arithmetic always uses the Default NaN setting, regardless of
> the value of the DN bit."
>
> Also on page 3180 for the description of VMAX(vector FP), it says:
> "
> * max(+0.0, -0.0) = +0.0
> * If any input is a NaN, the corresponding result element is the default
> NaN.
> "
>
Oops I was looking at FMAX (vector) pg 936.
> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
> FPMax() which is on pg. 2285
>
> // StandardFPSCRValue()
> // ====================
> FPCRType StandardFPSCRValue()
> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>
> Here bit-25(FPSCR.DN) is set to 1.
>
So, we should get defaultNaN too on aarch64, and no need to try to
force DN to 1 in gdb?
What can be wrong?
> Thanks,
> Tejas.
>
>
>>> If you're running your test in the AArch64 execution state, you'd want to
>>> define the DN bit and modify the expected results accordingly or have the
>>> test poll at runtime what the DN-bit is set to and check expected results
>>> dynamically.
>>
>> Makes sense, I hadn't noticed the different aarch64 spec here.
>>
>>> I think the test already has expected behaviour for AArch32 execution
>>> state
>>> by expecting DefaultNaN regardless.
>>
>> Yes.
>>
>>>> I have executed the test under GDB on AArch64 HW, and noticed that fpcr
>>>> was 0.
>>>> I forced it to have DN==1:
>>>> set $fpcr=0x1000000
>>>> but this didn't change the result.
>>>>
>>>> Does setting fpcr.dn under gdb actually work?
>>>>
>>>
>>> It should. Possibly a bug, patches welcome :-).
>>>
>> :-)
>>
>
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-22 23:10 ` Christophe Lyon
@ 2015-01-23 11:02 ` Tejas Belagod
2015-01-23 12:08 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-23 11:02 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Marcus Shawcroft, gcc-patches
On 22/01/15 21:31, Christophe Lyon wrote:
> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>
>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>>
>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>
>>>>>
>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>
>>>>>>
>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>> <christophe.lyon@linaro.org>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>
>>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>>> or
>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>>> vmin
>>>>>>>>> when the input is -NaN.
>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the result
>>>>>>>>> should the same as on aarch32.
>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>> So, not OK?
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>>> test on HW or a model?
>>>>>>>>
>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>>> foundation model for aarch64*-elf.
>>>>>>
>>>>>>
>>>>>>
>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>
>>>>>
>>>>>
>>>>> I've looked at this a bit more.
>>>>> We have
>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>
>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>> defaultNaN (0x7fc00000).
>>>>>
>>>>
>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>>> the
>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>> AArch64
>>>> execution state, result of Advanced SIMD FP arithmetic operations depend
>>>> on
>>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>>> DefaultNaN depending on the value of DN.
>>>
>>>
>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>> can see only the latter (no diff between aarch32 and aarch64 in
>>> FPProcessNan pseudo-code)
>>>
>>
>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
>> under DN:
>>
>> "The value of this bit only controls scalar floating-point arithmetic.
>> Advanced SIMD arithmetic always uses the Default NaN setting, regardless of
>> the value of the DN bit."
>>
>> Also on page 3180 for the description of VMAX(vector FP), it says:
>> "
>> * max(+0.0, -0.0) = +0.0
>> * If any input is a NaN, the corresponding result element is the default
>> NaN.
>> "
>>
> Oops I was looking at FMAX (vector) pg 936.
>
>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
>> FPMax() which is on pg. 2285
>>
>> // StandardFPSCRValue()
>> // ====================
>> FPCRType StandardFPSCRValue()
>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>
>> Here bit-25(FPSCR.DN) is set to 1.
>>
>
> So, we should get defaultNaN too on aarch64, and no need to try to
> force DN to 1 in gdb?
>
> What can be wrong?
>
On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're
reading the same document.
Regardless of the page number, if you see the pseudocode for
VMAX(FPSIMD) for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed
to FPMax() which means generate DefaultNaN() regardless.
OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
pseudocode gets just FPCR.
Thanks,
Tejas.
>> Thanks,
>> Tejas.
>>
>>
>>>> If you're running your test in the AArch64 execution state, you'd want to
>>>> define the DN bit and modify the expected results accordingly or have the
>>>> test poll at runtime what the DN-bit is set to and check expected results
>>>> dynamically.
>>>
>>> Makes sense, I hadn't noticed the different aarch64 spec here.
>>>
>>>> I think the test already has expected behaviour for AArch32 execution
>>>> state
>>>> by expecting DefaultNaN regardless.
>>>
>>> Yes.
>>>
>>>>> I have executed the test under GDB on AArch64 HW, and noticed that fpcr
>>>>> was 0.
>>>>> I forced it to have DN==1:
>>>>> set $fpcr=0x1000000
>>>>> but this didn't change the result.
>>>>>
>>>>> Does setting fpcr.dn under gdb actually work?
>>>>>
>>>>
>>>> It should. Possibly a bug, patches welcome :-).
>>>>
>>> :-)
>>>
>>
>>
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-23 11:02 ` Tejas Belagod
@ 2015-01-23 12:08 ` Christophe Lyon
2015-01-23 15:21 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-23 12:08 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 22/01/15 21:31, Christophe Lyon wrote:
>>
>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>
>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>
>>>>
>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>> wrote:
>>>>>
>>>>>
>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>> <christophe.lyon@linaro.org>
>>>>>>> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>
>>>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>>>> or
>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>>>> vmin
>>>>>>>>>> when the input is -NaN.
>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>> result
>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>> So, not OK?
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>>>> test on HW or a model?
>>>>>>>>>
>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> I've looked at this a bit more.
>>>>>> We have
>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>
>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>> defaultNaN (0x7fc00000).
>>>>>>
>>>>>
>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>>>> the
>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>> AArch64
>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>> depend
>>>>> on
>>>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>>>> DefaultNaN depending on the value of DN.
>>>>
>>>>
>>>>
>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>> FPProcessNan pseudo-code)
>>>>
>>>
>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
>>> under DN:
>>>
>>> "The value of this bit only controls scalar floating-point arithmetic.
>>> Advanced SIMD arithmetic always uses the Default NaN setting, regardless
>>> of
>>> the value of the DN bit."
>>>
>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>> "
>>> * max(+0.0, -0.0) = +0.0
>>> * If any input is a NaN, the corresponding result element is the default
>>> NaN.
>>> "
>>>
>> Oops I was looking at FMAX (vector) pg 936.
>>
>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
>>> FPMax() which is on pg. 2285
>>>
>>> // StandardFPSCRValue()
>>> // ====================
>>> FPCRType StandardFPSCRValue()
>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>
>>> Here bit-25(FPSCR.DN) is set to 1.
>>>
>>
>> So, we should get defaultNaN too on aarch64, and no need to try to
>> force DN to 1 in gdb?
>>
>> What can be wrong?
>>
>
> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're reading
> the same document.
>
> Regardless of the page number, if you see the pseudocode for VMAX(FPSIMD)
> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax() which
> means generate DefaultNaN() regardless.
>
> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
> pseudocode gets just FPCR.
>
>
Ok, that was my initial understanding but our discussion confused me.
And that's why I tried to force DN = 1 in gdb before single-stepping over
fmax v0.4s, v0.4s, v1.4s
but it changed nothing :-(
Hence my question about a gdb possible bug or misuse.
I'll try modifying the test to have it force DN=1.
> Thanks,
> Tejas.
>
>
>>> Thanks,
>>> Tejas.
>>>
>>>
>>>>> If you're running your test in the AArch64 execution state, you'd want
>>>>> to
>>>>> define the DN bit and modify the expected results accordingly or have
>>>>> the
>>>>> test poll at runtime what the DN-bit is set to and check expected
>>>>> results
>>>>> dynamically.
>>>>
>>>>
>>>> Makes sense, I hadn't noticed the different aarch64 spec here.
>>>>
>>>>> I think the test already has expected behaviour for AArch32 execution
>>>>> state
>>>>> by expecting DefaultNaN regardless.
>>>>
>>>>
>>>> Yes.
>>>>
>>>>>> I have executed the test under GDB on AArch64 HW, and noticed that
>>>>>> fpcr
>>>>>> was 0.
>>>>>> I forced it to have DN==1:
>>>>>> set $fpcr=0x1000000
>>>>>> but this didn't change the result.
>>>>>>
>>>>>> Does setting fpcr.dn under gdb actually work?
>>>>>>
>>>>>
>>>>> It should. Possibly a bug, patches welcome :-).
>>>>>
>>>> :-)
>>>>
>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-23 12:08 ` Christophe Lyon
@ 2015-01-23 15:21 ` Christophe Lyon
2015-01-25 22:51 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-23 15:21 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 23 January 2015 at 12:42, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 22/01/15 21:31, Christophe Lyon wrote:
>>>
>>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>>
>>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>>
>>>>>
>>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>>> <christophe.lyon@linaro.org>
>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>>
>>>>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>>>>> or
>>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>>>>> vmin
>>>>>>>>>>> when the input is -NaN.
>>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>>> result
>>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>>> So, not OK?
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>>>>> test on HW or a model?
>>>>>>>>>>
>>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> I've looked at this a bit more.
>>>>>>> We have
>>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>>
>>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>>> defaultNaN (0x7fc00000).
>>>>>>>
>>>>>>
>>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>>>>> the
>>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>>> AArch64
>>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>>> depend
>>>>>> on
>>>>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>>>>> DefaultNaN depending on the value of DN.
>>>>>
>>>>>
>>>>>
>>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>>> FPProcessNan pseudo-code)
>>>>>
>>>>
>>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
>>>> under DN:
>>>>
>>>> "The value of this bit only controls scalar floating-point arithmetic.
>>>> Advanced SIMD arithmetic always uses the Default NaN setting, regardless
>>>> of
>>>> the value of the DN bit."
>>>>
>>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>>> "
>>>> * max(+0.0, -0.0) = +0.0
>>>> * If any input is a NaN, the corresponding result element is the default
>>>> NaN.
>>>> "
>>>>
>>> Oops I was looking at FMAX (vector) pg 936.
>>>
>>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
>>>> FPMax() which is on pg. 2285
>>>>
>>>> // StandardFPSCRValue()
>>>> // ====================
>>>> FPCRType StandardFPSCRValue()
>>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>>
>>>> Here bit-25(FPSCR.DN) is set to 1.
>>>>
>>>
>>> So, we should get defaultNaN too on aarch64, and no need to try to
>>> force DN to 1 in gdb?
>>>
>>> What can be wrong?
>>>
>>
>> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're reading
>> the same document.
>>
>> Regardless of the page number, if you see the pseudocode for VMAX(FPSIMD)
>> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax() which
>> means generate DefaultNaN() regardless.
>>
>> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
>> pseudocode gets just FPCR.
>>
>>
> Ok, that was my initial understanding but our discussion confused me.
>
> And that's why I tried to force DN = 1 in gdb before single-stepping over
> fmax v0.4s, v0.4s, v1.4s
>
> but it changed nothing :-(
> Hence my question about a gdb possible bug or misuse.
Hmm... user error, I missed one bit
set $fpcr=0x2000000
works under gdb.
> I'll try modifying the test to have it force DN=1.
>
Forcing DN=1 in the test makes it pass.
I am going to look at adding that cleanly to my test, and resubmit it.
Thanks, and sorry for the noise.
>> Thanks,
>> Tejas.
>>
>>
>>>> Thanks,
>>>> Tejas.
>>>>
>>>>
>>>>>> If you're running your test in the AArch64 execution state, you'd want
>>>>>> to
>>>>>> define the DN bit and modify the expected results accordingly or have
>>>>>> the
>>>>>> test poll at runtime what the DN-bit is set to and check expected
>>>>>> results
>>>>>> dynamically.
>>>>>
>>>>>
>>>>> Makes sense, I hadn't noticed the different aarch64 spec here.
>>>>>
>>>>>> I think the test already has expected behaviour for AArch32 execution
>>>>>> state
>>>>>> by expecting DefaultNaN regardless.
>>>>>
>>>>>
>>>>> Yes.
>>>>>
>>>>>>> I have executed the test under GDB on AArch64 HW, and noticed that
>>>>>>> fpcr
>>>>>>> was 0.
>>>>>>> I forced it to have DN==1:
>>>>>>> set $fpcr=0x1000000
>>>>>>> but this didn't change the result.
>>>>>>>
>>>>>>> Does setting fpcr.dn under gdb actually work?
>>>>>>>
>>>>>>
>>>>>> It should. Possibly a bug, patches welcome :-).
>>>>>>
>>>>> :-)
>>>>>
>>>>
>>>>
>>>
>>
>>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-23 15:21 ` Christophe Lyon
@ 2015-01-25 22:51 ` Christophe Lyon
2015-01-26 13:23 ` Tejas Belagod
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-25 22:51 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 7172 bytes --]
On 23 January 2015 at 14:44, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 23 January 2015 at 12:42, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>> On 22/01/15 21:31, Christophe Lyon wrote:
>>>>
>>>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>>>
>>>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>>>
>>>>>>
>>>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>>>> <christophe.lyon@linaro.org>
>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>>>>>> or
>>>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>>>>>> vmin
>>>>>>>>>>>> when the input is -NaN.
>>>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>>>> result
>>>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>>>> So, not OK?
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>>>>>> test on HW or a model?
>>>>>>>>>>>
>>>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> I've looked at this a bit more.
>>>>>>>> We have
>>>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>>>
>>>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>>>> defaultNaN (0x7fc00000).
>>>>>>>>
>>>>>>>
>>>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>>>>>> the
>>>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>>>> AArch64
>>>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>>>> depend
>>>>>>> on
>>>>>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>>>>>> DefaultNaN depending on the value of DN.
>>>>>>
>>>>>>
>>>>>>
>>>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>>>> FPProcessNan pseudo-code)
>>>>>>
>>>>>
>>>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
>>>>> under DN:
>>>>>
>>>>> "The value of this bit only controls scalar floating-point arithmetic.
>>>>> Advanced SIMD arithmetic always uses the Default NaN setting, regardless
>>>>> of
>>>>> the value of the DN bit."
>>>>>
>>>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>>>> "
>>>>> * max(+0.0, -0.0) = +0.0
>>>>> * If any input is a NaN, the corresponding result element is the default
>>>>> NaN.
>>>>> "
>>>>>
>>>> Oops I was looking at FMAX (vector) pg 936.
>>>>
>>>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
>>>>> FPMax() which is on pg. 2285
>>>>>
>>>>> // StandardFPSCRValue()
>>>>> // ====================
>>>>> FPCRType StandardFPSCRValue()
>>>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>>>
>>>>> Here bit-25(FPSCR.DN) is set to 1.
>>>>>
>>>>
>>>> So, we should get defaultNaN too on aarch64, and no need to try to
>>>> force DN to 1 in gdb?
>>>>
>>>> What can be wrong?
>>>>
>>>
>>> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're reading
>>> the same document.
>>>
>>> Regardless of the page number, if you see the pseudocode for VMAX(FPSIMD)
>>> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax() which
>>> means generate DefaultNaN() regardless.
>>>
>>> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
>>> pseudocode gets just FPCR.
>>>
>>>
>> Ok, that was my initial understanding but our discussion confused me.
>>
>> And that's why I tried to force DN = 1 in gdb before single-stepping over
>> fmax v0.4s, v0.4s, v1.4s
>>
>> but it changed nothing :-(
>> Hence my question about a gdb possible bug or misuse.
>
> Hmm... user error, I missed one bit
> set $fpcr=0x2000000
> works under gdb.
>
>> I'll try modifying the test to have it force DN=1.
>>
> Forcing DN=1 in the test makes it pass.
>
> I am going to look at adding that cleanly to my test, and resubmit it.
>
> Thanks, and sorry for the noise.
>
Here is the updated version:
- Now I set DN=1 on AArch64 in clean_results, as it is the main
initialization function.
- I removed the double negative :-)
- I removed the useless [u]int64 and poly variants
Christophe.
2015-01-25 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(_ARM_FPSRC): Add DN and AHP fields.
(clean_results): Force DN=1 on AArch64.
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
>>> Thanks,
>>> Tejas.
>>>
>>>
>>>>> Thanks,
>>>>> Tejas.
>>>>>
>>>>>
>>>>>>> If you're running your test in the AArch64 execution state, you'd want
>>>>>>> to
>>>>>>> define the DN bit and modify the expected results accordingly or have
>>>>>>> the
>>>>>>> test poll at runtime what the DN-bit is set to and check expected
>>>>>>> results
>>>>>>> dynamically.
>>>>>>
>>>>>>
>>>>>> Makes sense, I hadn't noticed the different aarch64 spec here.
>>>>>>
>>>>>>> I think the test already has expected behaviour for AArch32 execution
>>>>>>> state
>>>>>>> by expecting DefaultNaN regardless.
>>>>>>
>>>>>>
>>>>>> Yes.
>>>>>>
>>>>>>>> I have executed the test under GDB on AArch64 HW, and noticed that
>>>>>>>> fpcr
>>>>>>>> was 0.
>>>>>>>> I forced it to have DN==1:
>>>>>>>> set $fpcr=0x1000000
>>>>>>>> but this didn't change the result.
>>>>>>>>
>>>>>>>> Does setting fpcr.dn under gdb actually work?
>>>>>>>>
>>>>>>>
>>>>>>> It should. Possibly a bug, patches welcome :-).
>>>>>>>
>>>>>> :-)
>>>>>>
>>>>>
>>>>>
>>>>
>>>
>>>
[-- Attachment #2: vmax.patch --]
[-- Type: text/x-patch, Size: 16879 bytes --]
commit 187f34bdf94cfd2fbe7d439d12956edb69a3c131
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date: Sun Nov 30 22:29:57 2014 +0100
Add vmax, vmin, vhadd, vhsub and vrhadd tests.
On AArch64, force FPCR.DN=1 to get the same results as on AArch32
(DefaultNaN).
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
index 2730a66..5b0c1e7 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
@@ -230,7 +230,9 @@ extern ARRAY(expected, hfloat, 32, 4);
typedef union {
struct {
- int _xxx:27;
+ int _xxx:25;
+ unsigned int DN:1;
+ unsigned int AHP:1;
unsigned int QC:1;
int V:1;
int C:1;
@@ -249,7 +251,9 @@ typedef union {
int C:1;
int V:1;
unsigned int QC:1;
- int _dnm:27;
+ unsigned int AHP:1;
+ unsigned int DN:1;
+ int _dnm:25;
} b;
unsigned int word;
} _ARM_FPSCR;
@@ -382,6 +386,15 @@ static void clean_results (void)
CLEAN(result, poly, 8, 16);
CLEAN(result, poly, 16, 8);
CLEAN(result, float, 32, 4);
+
+#if defined(__aarch64__)
+ /* On AArch64, make sure to return DefaultNaN to have the same
+ results as on AArch32. */
+ _ARM_FPSCR _afpscr_for_dn;
+ asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
+ _afpscr_for_dn.b.DN = 1;
+ asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
+#endif
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
new file mode 100644
index 0000000..1eb9271
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc
@@ -0,0 +1,134 @@
+/* Can't use the standard binary_op.inc template because vmax has no
+ 64 bits variant. */
+
+#include <math.h>
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1(NAME)
+
+void FNNAME (INSN_NAME) (void)
+{
+ int i;
+
+ /* Basic test: y=vmax(x,x), then store the result. */
+#define TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+ VECT_VAR(vector_res, T1, W, N) = \
+ INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
+ VECT_VAR(vector2, T1, W, N)); \
+ vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N))
+
+#define TEST_BINARY_OP(INSN, Q, T1, T2, W, N) \
+ TEST_BINARY_OP1(INSN, Q, T1, T2, W, N) \
+
+ DECL_VARIABLE_ALL_VARIANTS(vector);
+ DECL_VARIABLE_ALL_VARIANTS(vector2);
+ DECL_VARIABLE_ALL_VARIANTS(vector_res);
+
+ clean_results ();
+
+ /* Initialize input "vector" from "buffer". */
+ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer);
+#ifdef HAS_FLOAT_VARIANT
+ VLOAD(vector, buffer, , float, f, 32, 2);
+ VLOAD(vector, buffer, q, float, f, 32, 4);
+#endif
+
+ /* Choose init value arbitrarily, will be used as comparison value. */
+ VDUP(vector2, , int, s, 8, 8, -13);
+ VDUP(vector2, , int, s, 16, 4, -14);
+ VDUP(vector2, , int, s, 32, 2, -16);
+ VDUP(vector2, , uint, u, 8, 8, 0xf3);
+ VDUP(vector2, , uint, u, 16, 4, 0xfff1);
+ VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
+ VDUP(vector2, q, int, s, 8, 16, -12);
+ VDUP(vector2, q, int, s, 16, 8, -13);
+ VDUP(vector2, q, int, s, 32, 4, -15);
+ VDUP(vector2, q, uint, u, 8, 16, 0xf9);
+ VDUP(vector2, q, uint, u, 16, 8, 0xfff2);
+ VDUP(vector2, q, uint, u, 32, 4, 0xfffffff1);
+#ifdef HAS_FLOAT_VARIANT
+ VDUP(vector2, , float, f, 32, 2, -15.5f);
+ VDUP(vector2, q, float, f, 32, 4, -14.5f);
+#endif
+
+#ifdef HAS_FLOAT_VARIANT
+#define FLOAT_VARIANT(MACRO, VAR) \
+ MACRO(VAR, , float, f, 32, 2); \
+ MACRO(VAR, q, float, f, 32, 4)
+#else
+#define FLOAT_VARIANT(MACRO, VAR)
+#endif
+
+#define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR) \
+ MACRO(VAR, , int, s, 8, 8); \
+ MACRO(VAR, , int, s, 16, 4); \
+ MACRO(VAR, , int, s, 32, 2); \
+ MACRO(VAR, , uint, u, 8, 8); \
+ MACRO(VAR, , uint, u, 16, 4); \
+ MACRO(VAR, , uint, u, 32, 2); \
+ MACRO(VAR, q, int, s, 8, 16); \
+ MACRO(VAR, q, int, s, 16, 8); \
+ MACRO(VAR, q, int, s, 32, 4); \
+ MACRO(VAR, q, uint, u, 8, 16); \
+ MACRO(VAR, q, uint, u, 16, 8); \
+ MACRO(VAR, q, uint, u, 32, 4); \
+ FLOAT_VARIANT(MACRO, VAR)
+
+ /* Apply a binary operator named INSN_NAME. */
+ TEST_MACRO_NO64BIT_VARIANT_1_5(TEST_BINARY_OP, INSN_NAME);
+
+ CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+
+#ifdef HAS_FLOAT_VARIANT
+ CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
+
+ /* Extra FP tests with special values (NaN, ....) */
+ VDUP(vector, q, float, f, 32, 4, 1.0f);
+ VDUP(vector2, q, float, f, 32, 4, NAN);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_nan, " FP special (NaN)");
+
+ VDUP(vector, q, float, f, 32, 4, -NAN);
+ VDUP(vector2, q, float, f, 32, 4, 1.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_mnan, " FP special (-NaN)");
+
+ VDUP(vector, q, float, f, 32, 4, 1.0f);
+ VDUP(vector2, q, float, f, 32, 4, HUGE_VALF);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_inf, " FP special (inf)");
+
+ VDUP(vector, q, float, f, 32, 4, -HUGE_VALF);
+ VDUP(vector2, q, float, f, 32, 4, 1.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_minf, " FP special (-inf)");
+
+ VDUP(vector, q, float, f, 32, 4, 0.0f);
+ VDUP(vector2, q, float, f, 32, 4, -0.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero1, " FP special (-0.0)");
+
+ VDUP(vector, q, float, f, 32, 4, -0.0f);
+ VDUP(vector2, q, float, f, 32, 4, 0.0f);
+ TEST_BINARY_OP(INSN_NAME, q, float, f, 32, 4);
+ CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_zero2, " FP special (-0.0)");
+#endif
+}
+
+int main (void)
+{
+ FNNAME (INSN_NAME) ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c
new file mode 100644
index 0000000..d8a09ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhadd.c
@@ -0,0 +1,34 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vhadd
+#define TEST_MSG "VHADD/VHADDQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf1, 0xf2, 0xf2, 0xf3,
+ 0xf3, 0xf4, 0xf4, 0xf5 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf1, 0xf2, 0xf2, 0xf3,
+ 0xf3, 0xf4, 0xf4, 0xf5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5,
+ 0xf6, 0xf6, 0xf7, 0xf7,
+ 0xf8, 0xf8, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff4, 0xfff4, 0xfff5 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff2 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf4, 0xf5, 0xf5, 0xf6,
+ 0xf6, 0xf7, 0xf7, 0xf8,
+ 0xf8, 0xf9, 0xf9, 0xfa,
+ 0xfa, 0xfb, 0xfb, 0xfc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2,
+ 0xfff3, 0xfff3, 0xfff4, 0xfff4 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff2 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c
new file mode 100644
index 0000000..0fe8080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vhsub.c
@@ -0,0 +1,32 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vhsub
+#define TEST_MSG "VHSUB/VHSUBQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xfe, 0xff, 0xff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xffff, 0xffff, 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xfe, 0xff, 0xff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xffff, 0x0, 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xfe, 0xfe, 0xff, 0xff,
+ 0x0, 0x0, 0x1, 0x1,
+ 0x2, 0x2, 0x3, 0x3,
+ 0x4, 0x4, 0x5, 0x5 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffe, 0xffff, 0xffff, 0x0,
+ 0x0, 0x1, 0x1, 0x2 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0x0, 0x0, 0x1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xfb, 0xfc, 0xfc, 0xfd,
+ 0xfd, 0xfe, 0xfe, 0xff,
+ 0xff, 0x0, 0x0, 0x1,
+ 0x1, 0x2, 0x2, 0x3 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xffff, 0xffff, 0x0, 0x0,
+ 0x1, 0x1, 0x2, 0x2 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0x0, 0x0, 0x1 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
new file mode 100644
index 0000000..830603d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmax.c
@@ -0,0 +1,51 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmax
+#define TEST_MSG "VMAX/VMAXQ"
+
+#define HAS_FLOAT_VARIANT
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf3, 0xf3, 0xf3, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1780000, 0xc1700000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff3, 0xfff3, 0xfff3, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf9, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xfa, 0xfb,
+ 0xfc, 0xfd, 0xfe, 0xff };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1680000, 0xc1680000,
+ 0xc1600000, 0xc1500000 };
+
+/* Expected results with special FP values. */
+VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x7f800000, 0x7f800000,
+ 0x7f800000, 0x7f800000 };
+VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
+ 0x3f800000, 0x3f800000 };
+VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
new file mode 100644
index 0000000..8ad2703
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmin.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vmin
+#define TEST_MSG "VMIN/VMINQ"
+
+#define HAS_FLOAT_VARIANT
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf3, 0xf3, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf3, 0xf3, 0xf3, 0xf3 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff0, 0xfff1, 0xfff1, 0xfff1 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff0 };
+VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1780000 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf4, 0xf4, 0xf4,
+ 0xf4, 0xf4, 0xf4, 0xf4 };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff3, 0xfff3, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7,
+ 0xf8, 0xf9, 0xf9, 0xf9,
+ 0xf9, 0xf9, 0xf9, 0xf9 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff2,
+ 0xfff2, 0xfff2, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff1, 0xfffffff1 };
+VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000,
+ 0xc1680000, 0xc1680000 };
+/* Expected results with special FP values. */
+VECT_VAR_DECL(expected_nan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_mnan,hfloat,32,4) [] = { 0x7fc00000, 0x7fc00000,
+ 0x7fc00000, 0x7fc00000 };
+VECT_VAR_DECL(expected_inf,hfloat,32,4) [] = { 0x3f800000, 0x3f800000,
+ 0x3f800000, 0x3f800000 };
+VECT_VAR_DECL(expected_minf,hfloat,32,4) [] = { 0xff800000, 0xff800000,
+ 0xff800000, 0xff800000 };
+VECT_VAR_DECL(expected_zero1,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+VECT_VAR_DECL(expected_zero2,hfloat,32,4) [] = { 0x80000000, 0x80000000,
+ 0x80000000, 0x80000000 };
+
+#include "binary_op_no64.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c
new file mode 100644
index 0000000..eb82002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrhadd.c
@@ -0,0 +1,34 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+#define INSN_NAME vrhadd
+#define TEST_MSG "VRHADD/VRHADDQ"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected,int,16,4) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,uint,8,8) [] = { 0xf2, 0xf2, 0xf3, 0xf3,
+ 0xf4, 0xf4, 0xf5, 0xf5 };
+VECT_VAR_DECL(expected,uint,16,4) [] = { 0xfff1, 0xfff1, 0xfff2, 0xfff2 };
+VECT_VAR_DECL(expected,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 };
+VECT_VAR_DECL(expected,int,8,16) [] = { 0xf2, 0xf3, 0xf3, 0xf4,
+ 0xf4, 0xf5, 0xf5, 0xf6,
+ 0xf6, 0xf7, 0xf7, 0xf8,
+ 0xf8, 0xf9, 0xf9, 0xfa };
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff2, 0xfff2, 0xfff3, 0xfff3,
+ 0xfff4, 0xfff4, 0xfff5, 0xfff5 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff2 };
+VECT_VAR_DECL(expected,uint,8,16) [] = { 0xf5, 0xf5, 0xf6, 0xf6,
+ 0xf7, 0xf7, 0xf8, 0xf8,
+ 0xf9, 0xf9, 0xfa, 0xfa,
+ 0xfb, 0xfb, 0xfc, 0xfc };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfff1, 0xfff2, 0xfff2, 0xfff3,
+ 0xfff3, 0xfff4, 0xfff4, 0xfff5 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffffff1, 0xfffffff1,
+ 0xfffffff2, 0xfffffff2 };
+
+#include "binary_op_no64.inc"
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-25 22:51 ` Christophe Lyon
@ 2015-01-26 13:23 ` Tejas Belagod
2015-01-26 13:57 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Tejas Belagod @ 2015-01-26 13:23 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Marcus Shawcroft, gcc-patches
On 25/01/15 21:05, Christophe Lyon wrote:
> On 23 January 2015 at 14:44, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> On 23 January 2015 at 12:42, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>> On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>> On 22/01/15 21:31, Christophe Lyon wrote:
>>>>>
>>>>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>>>>>
>>>>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>>>>> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>>>>> <christophe.lyon@linaro.org>
>>>>>>>>>> wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>>> OK provided, as per the previous couple, that we don;t regression
>>>>>>>>>>>>>> or
>>>>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax and
>>>>>>>>>>>>> vmin
>>>>>>>>>>>>> when the input is -NaN.
>>>>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>>>>> result
>>>>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>>>>> So, not OK?
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did you
>>>>>>>>>>>> test on HW or a model?
>>>>>>>>>>>>
>>>>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on the
>>>>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> I've looked at this a bit more.
>>>>>>>>> We have
>>>>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>>>>
>>>>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>>>>> defaultNaN (0x7fc00000).
>>>>>>>>>
>>>>>>>>
>>>>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always uses
>>>>>>>> the
>>>>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>>>>> AArch64
>>>>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>>>>> depend
>>>>>>>> on
>>>>>>>> the value of the DN-bit i.e. either propagate the input NaN or generate
>>>>>>>> DefaultNaN depending on the value of DN.
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>>>>> FPProcessNan pseudo-code)
>>>>>>>
>>>>>>
>>>>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec -
>>>>>> under DN:
>>>>>>
>>>>>> "The value of this bit only controls scalar floating-point arithmetic.
>>>>>> Advanced SIMD arithmetic always uses the Default NaN setting, regardless
>>>>>> of
>>>>>> the value of the DN bit."
>>>>>>
>>>>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>>>>> "
>>>>>> * max(+0.0, -0.0) = +0.0
>>>>>> * If any input is a NaN, the corresponding result element is the default
>>>>>> NaN.
>>>>>> "
>>>>>>
>>>>> Oops I was looking at FMAX (vector) pg 936.
>>>>>
>>>>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue() to
>>>>>> FPMax() which is on pg. 2285
>>>>>>
>>>>>> // StandardFPSCRValue()
>>>>>> // ====================
>>>>>> FPCRType StandardFPSCRValue()
>>>>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>>>>
>>>>>> Here bit-25(FPSCR.DN) is set to 1.
>>>>>>
>>>>>
>>>>> So, we should get defaultNaN too on aarch64, and no need to try to
>>>>> force DN to 1 in gdb?
>>>>>
>>>>> What can be wrong?
>>>>>
>>>>
>>>> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're reading
>>>> the same document.
>>>>
>>>> Regardless of the page number, if you see the pseudocode for VMAX(FPSIMD)
>>>> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax() which
>>>> means generate DefaultNaN() regardless.
>>>>
>>>> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
>>>> pseudocode gets just FPCR.
>>>>
>>>>
>>> Ok, that was my initial understanding but our discussion confused me.
>>>
>>> And that's why I tried to force DN = 1 in gdb before single-stepping over
>>> fmax v0.4s, v0.4s, v1.4s
>>>
>>> but it changed nothing :-(
>>> Hence my question about a gdb possible bug or misuse.
>>
>> Hmm... user error, I missed one bit
>> set $fpcr=0x2000000
>> works under gdb.
>>
>>> I'll try modifying the test to have it force DN=1.
>>>
>> Forcing DN=1 in the test makes it pass.
>>
>> I am going to look at adding that cleanly to my test, and resubmit it.
>>
>> Thanks, and sorry for the noise.
>>
> Here is the updated version:
> - Now I set DN=1 on AArch64 in clean_results, as it is the main
> initialization function.
> - I removed the double negative :-)
> - I removed the useless [u]int64 and poly variants
>
> Christophe.
>
> 2015-01-25 Christophe Lyon <christophe.lyon@linaro.org>
>
> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
> (_ARM_FPSRC): Add DN and AHP fields.
> (clean_results): Force DN=1 on AArch64.
> * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
> * gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
>
I guess you don't need the fake dependency fix for this as this is
mostly called only once?
+ _ARM_FPSCR _afpscr_for_dn;
+ asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
+ _afpscr_for_dn.b.DN = 1;
+ asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
Otherwise, your patch looks OK to me(but I can't approve it).
Thanks,
Tejas.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-26 13:23 ` Tejas Belagod
@ 2015-01-26 13:57 ` Christophe Lyon
2015-02-02 10:39 ` Christophe Lyon
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-01-26 13:57 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 26 January 2015 at 13:10, Tejas Belagod <tejas.belagod@arm.com> wrote:
> On 25/01/15 21:05, Christophe Lyon wrote:
>>
>> On 23 January 2015 at 14:44, Christophe Lyon <christophe.lyon@linaro.org>
>> wrote:
>>>
>>> On 23 January 2015 at 12:42, Christophe Lyon <christophe.lyon@linaro.org>
>>> wrote:
>>>>
>>>> On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com>
>>>> wrote:
>>>>>
>>>>> On 22/01/15 21:31, Christophe Lyon wrote:
>>>>>>
>>>>>>
>>>>>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com>
>>>>>> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>>>>>> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>>>>>> <christophe.lyon@linaro.org>
>>>>>>>>>>> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>>>> OK provided, as per the previous couple, that we don;t
>>>>>>>>>>>>>>> regression
>>>>>>>>>>>>>>> or
>>>>>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax
>>>>>>>>>>>>>> and
>>>>>>>>>>>>>> vmin
>>>>>>>>>>>>>> when the input is -NaN.
>>>>>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>>>>>> result
>>>>>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>>>>>> So, not OK?
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did
>>>>>>>>>>>>> you
>>>>>>>>>>>>> test on HW or a model?
>>>>>>>>>>>>>
>>>>>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on
>>>>>>>>>>>> the
>>>>>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> I've looked at this a bit more.
>>>>>>>>>> We have
>>>>>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>>>>>
>>>>>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>>>>>> defaultNaN (0x7fc00000).
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always
>>>>>>>>> uses
>>>>>>>>> the
>>>>>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>>>>>> AArch64
>>>>>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>>>>>> depend
>>>>>>>>> on
>>>>>>>>> the value of the DN-bit i.e. either propagate the input NaN or
>>>>>>>>> generate
>>>>>>>>> DefaultNaN depending on the value of DN.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>>>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>>>>>> FPProcessNan pseudo-code)
>>>>>>>>
>>>>>>>
>>>>>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec
>>>>>>> -
>>>>>>> under DN:
>>>>>>>
>>>>>>> "The value of this bit only controls scalar floating-point
>>>>>>> arithmetic.
>>>>>>> Advanced SIMD arithmetic always uses the Default NaN setting,
>>>>>>> regardless
>>>>>>> of
>>>>>>> the value of the DN bit."
>>>>>>>
>>>>>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>>>>>> "
>>>>>>> * max(+0.0, -0.0) = +0.0
>>>>>>> * If any input is a NaN, the corresponding result element is the
>>>>>>> default
>>>>>>> NaN.
>>>>>>> "
>>>>>>>
>>>>>> Oops I was looking at FMAX (vector) pg 936.
>>>>>>
>>>>>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue()
>>>>>>> to
>>>>>>> FPMax() which is on pg. 2285
>>>>>>>
>>>>>>> // StandardFPSCRValue()
>>>>>>> // ====================
>>>>>>> FPCRType StandardFPSCRValue()
>>>>>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>>>>>
>>>>>>> Here bit-25(FPSCR.DN) is set to 1.
>>>>>>>
>>>>>>
>>>>>> So, we should get defaultNaN too on aarch64, and no need to try to
>>>>>> force DN to 1 in gdb?
>>>>>>
>>>>>> What can be wrong?
>>>>>>
>>>>>
>>>>> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're
>>>>> reading
>>>>> the same document.
>>>>>
>>>>> Regardless of the page number, if you see the pseudocode for
>>>>> VMAX(FPSIMD)
>>>>> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax()
>>>>> which
>>>>> means generate DefaultNaN() regardless.
>>>>>
>>>>> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
>>>>> pseudocode gets just FPCR.
>>>>>
>>>>>
>>>> Ok, that was my initial understanding but our discussion confused me.
>>>>
>>>> And that's why I tried to force DN = 1 in gdb before single-stepping
>>>> over
>>>> fmax v0.4s, v0.4s, v1.4s
>>>>
>>>> but it changed nothing :-(
>>>> Hence my question about a gdb possible bug or misuse.
>>>
>>>
>>> Hmm... user error, I missed one bit
>>> set $fpcr=0x2000000
>>> works under gdb.
>>>
>>>> I'll try modifying the test to have it force DN=1.
>>>>
>>> Forcing DN=1 in the test makes it pass.
>>>
>>> I am going to look at adding that cleanly to my test, and resubmit it.
>>>
>>> Thanks, and sorry for the noise.
>>>
>> Here is the updated version:
>> - Now I set DN=1 on AArch64 in clean_results, as it is the main
>> initialization function.
>> - I removed the double negative :-)
>> - I removed the useless [u]int64 and poly variants
>>
>> Christophe.
>>
>> 2015-01-25 Christophe Lyon <christophe.lyon@linaro.org>
>>
>> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
>> (_ARM_FPSRC): Add DN and AHP fields.
>> (clean_results): Force DN=1 on AArch64.
>> * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
>> * gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
>>
>
> I guess you don't need the fake dependency fix for this as this is mostly
> called only once?
>
Yes, that is my current assumption: for the time being there is no
other code which can potentially change this value.
> + _ARM_FPSCR _afpscr_for_dn;
> + asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
> + _afpscr_for_dn.b.DN = 1;
> + asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
Maybe in the future we'll want to check that DN=0 means that we
actually forward a NaN != DefaultNaN, but that can be a further
improvement to this patch.
> Otherwise, your patch looks OK to me(but I can't approve it).
Thanks for the review.
> Thanks,
> Tejas.
>
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests.
2015-01-20 15:30 ` Christophe Lyon
@ 2015-01-26 14:03 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:03 UTC (permalink / raw)
To: Christophe Lyon; +Cc: gcc-patches
On 20 January 2015 at 15:24, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> Here is an updated version, where I have removed a few more useless
> variables than you noticed: the [u]int64x1 as well as the 128 bits
> ones.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests.
2015-01-20 15:33 ` Christophe Lyon
@ 2015-01-26 14:08 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:08 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:28, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 17:24, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33 };
>>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>>> };
>>
>>
>> No poly vmlx_n, otherwise LGTM.
>>
> Here is a new version, with a bit more cleanup than requested, since
> only 16x4 and 32x2 variants are supported.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests.
2015-01-20 15:34 ` Christophe Lyon
@ 2015-01-26 14:19 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:19 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:30, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>>>> + /* Apply a unary operator named INSN_NAME. */
>>>
>>>
>>> Unary op?
>>>
>> Hmm cut & paste issue. Thanks
>>
> Here is an updated versoin, also renaming VPADD into VPXXX, since it's
> in a template.
Updated version is OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
2015-01-20 15:35 ` Christophe Lyon
@ 2015-01-26 14:19 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:19 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:32, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> No poly or float for vmovl.
>>
> Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2
> variants are necessary.
This version is OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 28/36] Add vmnv tests.
2015-01-20 15:36 ` Christophe Lyon
@ 2015-01-26 14:30 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:30 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:33, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 19:27, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>>> + 0x33333333, 0x33333333 };
>>> +
>>
>>
>> No float or poly16 for vmvn_*.
>>
> Updated as attached, removed 64x1 and 64x2 too.
>
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 29/36] Add vpadal tests.
2015-01-20 15:39 ` Christophe Lyon
@ 2015-01-26 14:34 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:34 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:34, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 16 January 2015 at 19:29, Tejas Belagod <tejas.belagod@arm.com> wrote:
>>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33,
>>> + 0x33, 0x33, 0x33, 0x33 };
>>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>>> + 0x33333333, 0x33333333 };
>>> +
>>
>>
>> No float or poly ops for VPADAL insns.
>>
> int8 variants are not necessary either, updated as attached.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests.
2015-01-20 15:50 ` Christophe Lyon
@ 2015-01-26 14:47 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-01-26 14:47 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
On 20 January 2015 at 15:35, Christophe Lyon <christophe.lyon@linaro.org> wrote:
>> Hmm changed my mind: vpaddl takes only one vector as input, although
>> it does add 2 vector elements.
>>
> Here is an updated version, removing poly, float and int8 variants.
OK /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-01-26 13:57 ` Christophe Lyon
@ 2015-02-02 10:39 ` Christophe Lyon
2015-02-02 15:38 ` Marcus Shawcroft
0 siblings, 1 reply; 144+ messages in thread
From: Christophe Lyon @ 2015-02-02 10:39 UTC (permalink / raw)
To: Tejas Belagod; +Cc: Marcus Shawcroft, gcc-patches
On 26 January 2015 at 14:23, Christophe Lyon <christophe.lyon@linaro.org> wrote:
> On 26 January 2015 at 13:10, Tejas Belagod <tejas.belagod@arm.com> wrote:
>> On 25/01/15 21:05, Christophe Lyon wrote:
>>>
>>> On 23 January 2015 at 14:44, Christophe Lyon <christophe.lyon@linaro.org>
>>> wrote:
>>>>
>>>> On 23 January 2015 at 12:42, Christophe Lyon <christophe.lyon@linaro.org>
>>>> wrote:
>>>>>
>>>>> On 23 January 2015 at 11:18, Tejas Belagod <tejas.belagod@arm.com>
>>>>> wrote:
>>>>>>
>>>>>> On 22/01/15 21:31, Christophe Lyon wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 22 January 2015 at 16:22, Tejas Belagod <tejas.belagod@arm.com>
>>>>>>> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>> On 22/01/15 14:28, Christophe Lyon wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On 22 January 2015 at 12:19, Tejas Belagod <tejas.belagod@arm.com>
>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 21/01/15 15:07, Christophe Lyon wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> On 19 January 2015 at 17:54, Marcus Shawcroft
>>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> On 19 January 2015 at 15:43, Christophe Lyon
>>>>>>>>>>>> <christophe.lyon@linaro.org>
>>>>>>>>>>>> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> On 19 January 2015 at 14:29, Marcus Shawcroft
>>>>>>>>>>>>> <marcus.shawcroft@gmail.com> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> On 16 January 2015 at 17:52, Christophe Lyon
>>>>>>>>>>>>>> <christophe.lyon@linaro.org> wrote:
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> OK provided, as per the previous couple, that we don;t
>>>>>>>>>>>>>>>> regression
>>>>>>>>>>>>>>>> or
>>>>>>>>>>>>>>>> introduce new fails on aarch64[_be] or aarch32.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> This patch shows failures on aarch64 and aarch64_be for vmax
>>>>>>>>>>>>>>> and
>>>>>>>>>>>>>>> vmin
>>>>>>>>>>>>>>> when the input is -NaN.
>>>>>>>>>>>>>>> It's a corner case, and my reading of the ARM ARM is that the
>>>>>>>>>>>>>>> result
>>>>>>>>>>>>>>> should the same as on aarch32.
>>>>>>>>>>>>>>> I haven't had time to look at it in more details though.
>>>>>>>>>>>>>>> So, not OK?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> They should have the same behaviour in aarch32 and aarch64. Did
>>>>>>>>>>>>>> you
>>>>>>>>>>>>>> test on HW or a model?
>>>>>>>>>>>>>>
>>>>>>>>>>>>> I ran the tests on qemu for aarch32 and aarch64-linux, and on
>>>>>>>>>>>>> the
>>>>>>>>>>>>> foundation model for aarch64*-elf.
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> Leave this one out until we understand why it fails. /Marcus
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> I've looked at this a bit more.
>>>>>>>>>>> We have
>>>>>>>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>>>>>>> where v0 is a vector of -NaN (0xffc00000) and v1 is a vector of 1.
>>>>>>>>>>>
>>>>>>>>>>> The output is still -NaN (0xffc00000), while the test expects
>>>>>>>>>>> defaultNaN (0x7fc00000).
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> In the AArch32 execution state, Advanced SIMD FP arithmetic always
>>>>>>>>>> uses
>>>>>>>>>> the
>>>>>>>>>> DefaultNaN setting regardless of the DN-bit value in the FPSCR. In
>>>>>>>>>> AArch64
>>>>>>>>>> execution state, result of Advanced SIMD FP arithmetic operations
>>>>>>>>>> depend
>>>>>>>>>> on
>>>>>>>>>> the value of the DN-bit i.e. either propagate the input NaN or
>>>>>>>>>> generate
>>>>>>>>>> DefaultNaN depending on the value of DN.
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Maybe I'm using an outdated doc. On page 2282 of ARMv8 ARM rev C, I
>>>>>>>>> can see only the latter (no diff between aarch32 and aarch64 in
>>>>>>>>> FPProcessNan pseudo-code)
>>>>>>>>>
>>>>>>>>
>>>>>>>> If you see pg. 4005 in the same doc(rev C), you'll see the FPSCR spec
>>>>>>>> -
>>>>>>>> under DN:
>>>>>>>>
>>>>>>>> "The value of this bit only controls scalar floating-point
>>>>>>>> arithmetic.
>>>>>>>> Advanced SIMD arithmetic always uses the Default NaN setting,
>>>>>>>> regardless
>>>>>>>> of
>>>>>>>> the value of the DN bit."
>>>>>>>>
>>>>>>>> Also on page 3180 for the description of VMAX(vector FP), it says:
>>>>>>>> "
>>>>>>>> * max(+0.0, -0.0) = +0.0
>>>>>>>> * If any input is a NaN, the corresponding result element is the
>>>>>>>> default
>>>>>>>> NaN.
>>>>>>>> "
>>>>>>>>
>>>>>>> Oops I was looking at FMAX (vector) pg 936.
>>>>>>>
>>>>>>>> The pseudocode for FPMax () on pg. 3180 passes StandardFPSCRValue()
>>>>>>>> to
>>>>>>>> FPMax() which is on pg. 2285
>>>>>>>>
>>>>>>>> // StandardFPSCRValue()
>>>>>>>> // ====================
>>>>>>>> FPCRType StandardFPSCRValue()
>>>>>>>> return ‘00000’ : FPSCR.AHP : ‘11000000000000000000000000’
>>>>>>>>
>>>>>>>> Here bit-25(FPSCR.DN) is set to 1.
>>>>>>>>
>>>>>>>
>>>>>>> So, we should get defaultNaN too on aarch64, and no need to try to
>>>>>>> force DN to 1 in gdb?
>>>>>>>
>>>>>>> What can be wrong?
>>>>>>>
>>>>>>
>>>>>> On pg 3180, I see VMAX(FPSIMD) for A32/T32, not A64. I hope we're
>>>>>> reading
>>>>>> the same document.
>>>>>>
>>>>>> Regardless of the page number, if you see the pseudocode for
>>>>>> VMAX(FPSIMD)
>>>>>> for AArch32, StandardFPSCRValue() (i.e. DN = 1) is passed to FPMax()
>>>>>> which
>>>>>> means generate DefaultNaN() regardless.
>>>>>>
>>>>>> OTOH, on pg 936, you have FMAX(vector) for A64 where FPMax() in the
>>>>>> pseudocode gets just FPCR.
>>>>>>
>>>>>>
>>>>> Ok, that was my initial understanding but our discussion confused me.
>>>>>
>>>>> And that's why I tried to force DN = 1 in gdb before single-stepping
>>>>> over
>>>>> fmax v0.4s, v0.4s, v1.4s
>>>>>
>>>>> but it changed nothing :-(
>>>>> Hence my question about a gdb possible bug or misuse.
>>>>
>>>>
>>>> Hmm... user error, I missed one bit
>>>> set $fpcr=0x2000000
>>>> works under gdb.
>>>>
>>>>> I'll try modifying the test to have it force DN=1.
>>>>>
>>>> Forcing DN=1 in the test makes it pass.
>>>>
>>>> I am going to look at adding that cleanly to my test, and resubmit it.
>>>>
>>>> Thanks, and sorry for the noise.
>>>>
>>> Here is the updated version:
>>> - Now I set DN=1 on AArch64 in clean_results, as it is the main
>>> initialization function.
>>> - I removed the double negative :-)
>>> - I removed the useless [u]int64 and poly variants
>>>
>>> Christophe.
>>>
>>> 2015-01-25 Christophe Lyon <christophe.lyon@linaro.org>
>>>
>>> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
>>> (_ARM_FPSRC): Add DN and AHP fields.
>>> (clean_results): Force DN=1 on AArch64.
>>> * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
>>> * gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
>>>
>>
>> I guess you don't need the fake dependency fix for this as this is mostly
>> called only once?
>>
> Yes, that is my current assumption: for the time being there is no
> other code which can potentially change this value.
>
>> + _ARM_FPSCR _afpscr_for_dn;
>> + asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
>> + _afpscr_for_dn.b.DN = 1;
>> + asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
>
> Maybe in the future we'll want to check that DN=0 means that we
> actually forward a NaN != DefaultNaN, but that can be a further
> improvement to this patch.
>
Marcus,
Is it OK to commit this one?
This is the only remaining one from this series.
Thanks,
Christophe.
>> Otherwise, your patch looks OK to me(but I can't approve it).
> Thanks for the review.
>
>> Thanks,
>> Tejas.
>>
>>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests.
2015-02-02 10:39 ` Christophe Lyon
@ 2015-02-02 15:38 ` Marcus Shawcroft
0 siblings, 0 replies; 144+ messages in thread
From: Marcus Shawcroft @ 2015-02-02 15:38 UTC (permalink / raw)
To: Christophe Lyon; +Cc: Tejas Belagod, gcc-patches
>>>> 2015-01-25 Christophe Lyon <christophe.lyon@linaro.org>
>>>>
>>>> * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
>>>> (_ARM_FPSRC): Add DN and AHP fields.
>>>> (clean_results): Force DN=1 on AArch64.
>>>> * gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc: New file.
>>>> * gcc.target/aarch64/advsimd-intrinsics/vhadd.c: New file.
>>>> * gcc.target/aarch64/advsimd-intrinsics/vhsub.c: New file.
>>>> * gcc.target/aarch64/advsimd-intrinsics/vmax.c: New file.
>>>> * gcc.target/aarch64/advsimd-intrinsics/vmin.c: New file.
>>>> * gcc.target/aarch64/advsimd-intrinsics/vrhadd.c: New file.
>>>>
>>>
>>> I guess you don't need the fake dependency fix for this as this is mostly
>>> called only once?
>>>
>> Yes, that is my current assumption: for the time being there is no
>> other code which can potentially change this value.
>>
>>> + _ARM_FPSCR _afpscr_for_dn;
>>> + asm volatile ("mrs %0,fpcr" : "=r" (_afpscr_for_dn));
>>> + _afpscr_for_dn.b.DN = 1;
>>> + asm volatile ("msr fpcr,%0" : : "r" (_afpscr_for_dn));
>>
>> Maybe in the future we'll want to check that DN=0 means that we
>> actually forward a NaN != DefaultNaN, but that can be a further
>> improvement to this patch.
>>
> Marcus,
> Is it OK to commit this one?
> This is the only remaining one from this series.
Yep, that's ok /Marcus
^ permalink raw reply [flat|nested] 144+ messages in thread
end of thread, other threads:[~2015-02-02 15:38 UTC | newest]
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2015-01-13 15:19 [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 26/36] Add vmull_lane tests Christophe Lyon
2015-01-16 18:28 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 13/36] Add vmla_n and vmls_n tests Christophe Lyon
2015-01-16 16:30 ` Tejas Belagod
2015-01-20 15:33 ` Christophe Lyon
2015-01-26 14:08 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 11/36] Add vmlal_lane and vmlsl_lane tests Christophe Lyon
2015-01-16 16:23 ` Tejas Belagod
2015-01-19 13:53 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 24/36] Add vmul_n tests Christophe Lyon
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2015-01-19 15:23 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 33/36] Add vqdmulh_n tests Christophe Lyon
2015-01-19 16:48 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 15/36] Add vqdmlal_lane and vqdmlsl_lane tests Christophe Lyon
2015-01-16 16:52 ` Tejas Belagod
2015-01-19 14:13 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 18/36] Add vsli_n and vsri_n tests Christophe Lyon
2015-01-16 18:11 ` Tejas Belagod
2015-01-19 14:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 34/36] Add vqdmull tests Christophe Lyon
2015-01-19 16:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 21/36] Add vmovl tests Christophe Lyon
2015-01-16 18:18 ` Tejas Belagod
2015-01-20 15:35 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 05/36] Add vldX_dup test Christophe Lyon
2015-01-16 15:35 ` Tejas Belagod
2015-01-16 18:17 ` Christophe Lyon
2015-01-19 13:39 ` Marcus Shawcroft
2015-01-22 16:32 ` Tejas Belagod
2015-01-22 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 06/36] Add vmla and vmls tests Christophe Lyon
2015-01-16 15:52 ` Tejas Belagod
2015-01-16 16:32 ` Christophe Lyon
2015-01-19 13:42 ` Marcus Shawcroft
2015-01-20 22:23 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 31/36] Add vqdmulh tests Christophe Lyon
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2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 28/36] Add vmnv tests Christophe Lyon
2015-01-16 18:39 ` Tejas Belagod
2015-01-20 15:36 ` Christophe Lyon
2015-01-26 14:30 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 07/36] Add vmla_lane and vmls_lane tests Christophe Lyon
2015-01-16 15:57 ` Tejas Belagod
2015-01-19 13:43 ` Marcus Shawcroft
2015-01-21 0:02 ` Christophe Lyon
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 12/36] Add vmlal_n and vmlsl_n tests Christophe Lyon
2015-01-16 16:29 ` Tejas Belagod
2015-01-19 13:54 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 22/36] Add vmovn tests Christophe Lyon
2015-01-16 18:21 ` Tejas Belagod
2015-01-19 14:44 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 04/36] Add vld1_lane tests Christophe Lyon
2015-01-16 14:31 ` Tejas Belagod
2015-01-16 16:31 ` Christophe Lyon
2015-01-16 17:22 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests Christophe Lyon
2015-01-16 16:21 ` Tejas Belagod
2015-01-16 16:35 ` Christophe Lyon
2015-01-20 15:30 ` Christophe Lyon
2015-01-26 14:03 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 20/36] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc Christophe Lyon
2015-01-16 18:16 ` Tejas Belagod
2015-01-19 14:41 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 01/36] Add explicit dependency on Neon Cumulative Saturation flag (QC) Christophe Lyon
2015-01-16 13:43 ` Tejas Belagod
2015-01-16 17:15 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 03/36] Add vmax, vmin, vhadd, vhsub and vrhadd tests Christophe Lyon
2015-01-16 14:08 ` Tejas Belagod
2015-01-16 16:23 ` Christophe Lyon
2015-01-16 17:20 ` Marcus Shawcroft
2015-01-16 17:59 ` Christophe Lyon
2015-01-19 13:34 ` Marcus Shawcroft
2015-01-19 15:49 ` Christophe Lyon
2015-01-19 17:33 ` Marcus Shawcroft
2015-01-21 16:35 ` Christophe Lyon
2015-01-22 12:37 ` Tejas Belagod
2015-01-22 14:42 ` Christophe Lyon
2015-01-22 15:58 ` Tejas Belagod
2015-01-22 23:10 ` Christophe Lyon
2015-01-23 11:02 ` Tejas Belagod
2015-01-23 12:08 ` Christophe Lyon
2015-01-23 15:21 ` Christophe Lyon
2015-01-25 22:51 ` Christophe Lyon
2015-01-26 13:23 ` Tejas Belagod
2015-01-26 13:57 ` Christophe Lyon
2015-02-02 10:39 ` Christophe Lyon
2015-02-02 15:38 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 14/36] Add vqdmlal and vqdmlsl tests Christophe Lyon
2015-01-16 16:45 ` Tejas Belagod
2015-01-19 14:11 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 29/36] Add vpadal tests Christophe Lyon
2015-01-16 18:41 ` Tejas Belagod
2015-01-20 15:39 ` Christophe Lyon
2015-01-26 14:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 16/36] Add vqdmlal_n and vqdmlsl_n tests Christophe Lyon
2015-01-16 17:26 ` Tejas Belagod
2015-01-19 14:14 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 27/36] Add vmull_n tests Christophe Lyon
2015-01-16 18:32 ` Tejas Belagod
2015-01-19 15:35 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 30/36] Add vpaddl tests Christophe Lyon
2015-01-16 18:48 ` Tejas Belagod
2015-01-16 19:05 ` Christophe Lyon
2015-01-16 20:34 ` Christophe Lyon
2015-01-20 15:50 ` Christophe Lyon
2015-01-26 14:47 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 08/36] Add vtrn tests. Refactor vzup and vzip tests Christophe Lyon
2015-01-16 16:06 ` Tejas Belagod
2015-01-16 18:12 ` Christophe Lyon
2015-01-19 13:52 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 23/36] Add vmul_lane tests Christophe Lyon
2015-01-16 18:23 ` Tejas Belagod
2015-01-19 15:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 25/36] Add vmull tests Christophe Lyon
2015-01-16 18:26 ` Tejas Belagod
2015-01-19 15:34 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 02/36] Be more verbose, and actually confirm that a test was checked Christophe Lyon
2015-01-16 13:46 ` Tejas Belagod
2015-01-16 17:17 ` Marcus Shawcroft
2015-01-13 15:19 ` [[ARM/AArch64][testsuite] 32/36] Add vqdmulh_lane tests Christophe Lyon
2015-01-19 16:47 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 10/36] Add vmlal and vmlsl tests Christophe Lyon
2015-01-16 16:22 ` Tejas Belagod
2015-01-19 13:51 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 19/36] Add vsubl tests, put most of the code in common with vaddl in vXXXl.inc Christophe Lyon
2015-01-16 18:12 ` Tejas Belagod
2015-01-19 14:37 ` Marcus Shawcroft
2015-01-13 15:20 ` [[ARM/AArch64][testsuite] 17/36] Add vpadd, vpmax and vpmin tests Christophe Lyon
2015-01-16 17:54 ` Tejas Belagod
2015-01-16 18:02 ` Christophe Lyon
2015-01-20 15:34 ` Christophe Lyon
2015-01-26 14:19 ` Marcus Shawcroft
2015-01-13 15:21 ` [[ARM/AArch64][testsuite] 35/36] Add vqdmull_lane tests Christophe Lyon
2015-01-19 16:54 ` Marcus Shawcroft
2015-01-13 15:22 ` [[ARM/AArch64][testsuite] 36/36] Add vqdmull_n tests Christophe Lyon
2015-01-16 18:49 ` Tejas Belagod
2015-01-16 19:20 ` Christophe Lyon
2015-01-19 17:16 ` Marcus Shawcroft
2015-01-19 17:18 ` [[ARM/AArch64][testsuite] 00/36] More Neon intrinsics tests Marcus Shawcroft
2015-01-20 15:26 ` Christophe Lyon
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